soc/intel/cannonlake: Add lpc pci driver

1.Add common ITSS support as part of LPC driver init code.
2.Add LPC pci driver for CNL

Change-Id: I6c810fd7158e1498664b77eecae22132e2f6878f
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/cannonlake/chip.h

@@ -194,6 +194,9 @@ struct soc_intel_cannonlake_config {
 
 	/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
 	uint8_t eist_enable;
+
+	/* Statically clock gate 8254 PIT. */
+	uint8_t clock_gate_8254;
 	/* Enable C6 DRAM */
 	uint8_t enable_c6dram;
 	/*