From a55e829ae3c12dc6b606ec2e8df9738a2956da43 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Tue, 21 Mar 2023 13:39:23 -0600 Subject: [PATCH] soc/intel/alderlake: Correct PCH-S XHCI port information Change-Id: I405b4f73584f4391152941bbd32e828a2bd0e6aa --- src/soc/intel/alderlake/xhci.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c index 36d1491faa..3044a3ff84 100644 --- a/src/soc/intel/alderlake/xhci.c +++ b/src/soc/intel/alderlake/xhci.c @@ -9,10 +9,17 @@ * as well as doc# 626817, ADL-P PCH EDS Vol. 1 */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define PCH_XHCI_USB2_PORT_STATUS_REG 0x480 +#define PCH_XHCI_USB3_PORT_STATUS_REG 0x580 +#define PCH_XHCI_USB2_PORT_NUM 14 +#define PCH_XHCI_USB3_PORT_NUM 10 +#else #define PCH_XHCI_USB2_PORT_STATUS_REG 0x480 #define PCH_XHCI_USB3_PORT_STATUS_REG 0x540 #define PCH_XHCI_USB2_PORT_NUM 10 #define PCH_XHCI_USB3_PORT_NUM 4 +#endif #define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480 #define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490