sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brya: USB2 Port 9 for integrated BT on Trulo baseboard

Browse Source 
This patch moves the configuration for integrated Bluetooth
functionality (USB2 Port 9) from Orisa variant to the Trulo baseboard.

This change is necessary to support the CNVi BT module on Trulo
variants. The configuration is skipped for Orisa.

Trulo: USB2 Port 9 is now configured as USB2_PORT_MID(OC_SKIP) to
       support the CNVi BT module.
Orisa: The previous configuration of USB2 Port 9 as a Bluetooth port for
       CNVi WLAN has been removed.

This change ensures proper Bluetooth connectivity is applicable for all
Trulo variants including Orisa and Trulo.

BUG=b:351976770
TEST=Builds successfully for google/trulo.

Change-Id: I760a82cb6f6c98db7249caf1ba7e6d6c5dc8f2c4
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83663
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik
2024-07-26 16:06:32 +05:30
parent c694522b52
commit a5aa6cb0b2
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb
View File

@ -15,7 +15,8 @@ chip soc/intel/alderlake
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 6
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 7
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8 register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 8
register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 9 # USB 2.0 Port #10 must be used for integrated BT with Intel CNVi
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10 register "usb2_ports[10]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 10
register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11 register "usb2_ports[11]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 11
register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12 register "usb2_ports[12]" = "USB2_PORT_EMPTY" # Disable USB2.0 Port 12

1
src/mainboard/google/brya/variants/orisa/overridetree.cb
View File

@ -91,7 +91,6 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7 register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 7
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8 register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port 8
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A0
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A port A1