soc/intel/tigerlake: Add chipset devicetree
Add aliases for devices and set most of them to off with the exception of some essential devices. Set a default register value as an example. Change-Id: If50269808645ddc019e0d94fa8296df58ab7c367 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44038 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
committed by
Furquan Shaikh
parent
e335c2e02f
commit
a5bb31f069
@@ -86,6 +86,10 @@ config FSP_TEMP_RAM_SIZE
|
||||
Refer to Platform FSP integration guide document to know
|
||||
the exact FSP requirement for Heap setup.
|
||||
|
||||
config CHIPSET_DEVICETREE
|
||||
string
|
||||
default "soc/intel/tigerlake/chipset.cb"
|
||||
|
||||
config IFD_CHIPSET
|
||||
string
|
||||
default "tgl"
|
||||
|
Reference in New Issue
Block a user