AGESA boards: Rename files containing OEM configuration
There are other things besides PCIe port configuration that require board specific hooks. Change-Id: I0923651487b9ed5f6f7569ce08e02d993fa5f976 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14527 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
230
src/mainboard/amd/thatcher/OemCustomize.c
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230
src/mainboard/amd/thatcher/OemCustomize.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "AGESA.h"
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#include "amdlib.h"
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#include "Ids.h"
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#include "heapManager.h"
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#include "Filecode.h"
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#include <northbridge/amd/agesa/agesawrapper.h>
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#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
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/*
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* Lane ID Mapping (from Fam15h BKDG: Table 45: Lane Id Mapping)
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*
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* Lane Id
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* 0 P_UMI_[T,R]X[P,N]0 - southbridge link, connect via dev 8
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* 1 P_UMI_[T,R]X[P,N]1 - southbridge link, connect via dev 8
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* 2 P_UMI_[T,R]X[P,N]2 - southbridge link, connect via dev 8
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* 3 P_UMI_[T,R]X[P,N]3 - southbridge link, connect via dev 8
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* 4 P_GPP_[T,R]X[P,N]0 - may connect to PCI dev 4 - 7
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* 5 P_GPP_[T,R]X[P,N]1 - may connect to PCI dev 4 - 7
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* 6 P_GPP_[T,R]X[P,N]2 - may connect to PCI dev 4 - 7
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* 7 P_GPP_[T,R]X[P,N]3 - may connect to PCI dev 4 - 7
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* 8 P_GFX_[T,R]X[P,N]0 - may be used to form GFX slot or DDI
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* 9 P_GFX_[T,R]X[P,N]1 - may be used to form GFX slot or DDI
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* 10 P_GFX_[T,R]X[P,N]2 - may be used to form GFX slot or DDI
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* 11 P_GFX_[T,R]X[P,N]3 - may be used to form GFX slot or DDI
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* 12 P_GFX_[T,R]X[P,N]4 - may be used to form GFX slot or DDI
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* 13 P_GFX_[T,R]X[P,N]5 - may be used to form GFX slot or DDI
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* 14 P_GFX_[T,R]X[P,N]6 - may be used to form GFX slot or DDI
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* 15 P_GFX_[T,R]X[P,N]7 - may be used to form GFX slot or DDI
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* 16 P_GFX_[T,R]X[P,N]8 - may be used to form GFX slot or DDI
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* 17 P_GFX_[T,R]X[P,N]9 - may be used to form GFX slot or DDI
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* 18 P_GFX_[T,R]X[P,N]10 - may be used to form GFX slot or DDI
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* 19 P_GFX_[T,R]X[P,N]11 - may be used to form GFX slot or DDI
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* 20 P_GFX_[T,R]X[P,N]12 - may be used to form GFX slot or DDI
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* 21 P_GFX_[T,R]X[P,N]13 - may be used to form GFX slot or DDI
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* 22 P_GFX_[T,R]X[P,N]14 - may be used to form GFX slot or DDI
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* 23 P_GFX_[T,R]X[P,N]15 - may be used to form GFX slot or DDI
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* 24 DP0_TX[P,N]0 - rest is just for DDI (graphics outputs)
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* 25 DP0_TX[P,N]1
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* 26 DP0_TX[P,N]2
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* 27 DP0_TX[P,N]3
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* 28 DP1_TX[P,N]0
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* 29 DP1_TX[P,N]1
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* 30 DP1_TX[P,N]2
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* 31 DP1_TX[P,N]3
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* 32 DP2_TX[P,N]0
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* 33 DP2_TX[P,N]1
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* 34 DP2_TX[P,N]2
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* 35 DP2_TX[P,N]3
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* 36 DP2_TX[P,N]4
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* 37 DP2_TX[P,N]5
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* 38 DP2_TX[P,N]6
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*/
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static const PCIe_PORT_DESCRIPTOR PortList [] = {
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/* PCIe port, Lanes 15:8, PCI Device Number 2, PCIE SLOT x8 */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 15, 8),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieUnusedEngine, 16, 23),
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PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 4, PCI Device Number 4, LAN */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 7, PCI Device Number 7, Disabled */
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7),
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PCIE_PORT_DATA_INITIALIZER (PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1)
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},
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/* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3),
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PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
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},
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};
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static const PCIe_DDI_DESCRIPTOR DdiList [] = {
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// DP0 to HDMI0/DP0
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
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},
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// DP1 to HDMI1/DP1
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{
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0,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2)
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},
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// DP2 to MINI-DDI Card
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{
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DESCRIPTOR_TERMINATE_LIST,
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PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
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PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux3, Hdp3)
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},
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};
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static const PCIe_COMPLEX_DESCRIPTOR Trinity = {
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DESCRIPTOR_TERMINATE_LIST,
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0,
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&PortList[0],
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&DdiList[0]
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};
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/*---------------------------------------------------------------------------------------*/
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/**
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* OemCustomizeInitEarly
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*
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* Description:
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* This stub function will call the host environment through the binary block
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* interface (call-out port) to provide a user hook opportunity
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*
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* Parameters:
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* @param[in] *InitEarly
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*
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* @retval VOID
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*
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**/
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/*---------------------------------------------------------------------------------------*/
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static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
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{
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AGESA_STATUS Status;
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VOID *TrinityPcieComplexListPtr;
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VOID *TrinityPciePortPtr;
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VOID *TrinityPcieDdiPtr;
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ALLOCATE_HEAP_PARAMS AllocHeapParams;
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// GNB PCIe topology Porting
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//
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// Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
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//
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AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
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AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
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AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
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Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader);
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ASSERT(Status == AGESA_SUCCESS);
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TrinityPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr;
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AllocHeapParams.BufferPtr += sizeof(Trinity);
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TrinityPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr;
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AllocHeapParams.BufferPtr += sizeof(PortList);
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TrinityPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr;
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LibAmdMemFill (TrinityPcieComplexListPtr,
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0,
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sizeof(Trinity),
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&InitEarly->StdHeader);
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LibAmdMemFill (TrinityPciePortPtr,
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0,
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sizeof(PortList),
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&InitEarly->StdHeader);
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LibAmdMemFill (TrinityPcieDdiPtr,
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0,
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sizeof(DdiList),
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&InitEarly->StdHeader);
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LibAmdMemCopy (TrinityPcieComplexListPtr, &Trinity, sizeof(Trinity), &InitEarly->StdHeader);
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LibAmdMemCopy (TrinityPciePortPtr, &PortList[0], sizeof(PortList), &InitEarly->StdHeader);
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LibAmdMemCopy (TrinityPcieDdiPtr, &DdiList[0], sizeof(DdiList), &InitEarly->StdHeader);
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((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)TrinityPciePortPtr;
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((PCIe_COMPLEX_DESCRIPTOR*)TrinityPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)TrinityPcieDdiPtr;
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InitEarly->GnbConfig.PcieComplexList = TrinityPcieComplexListPtr;
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return AGESA_SUCCESS;
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}
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static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid)
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{
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/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */
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InitMid->GnbMidConfiguration.iGpuVgaMode = 0;
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return AGESA_SUCCESS;
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}
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const struct OEM_HOOK OemCustomize = {
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.InitEarly = OemInitEarly,
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.InitMid = OemInitMid,
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};
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