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mb/amd,google/*/devicetree: drop CPU cluster device for Stoneyridge

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Since commit 60e9114c62 ("include/device: ensure valid link/bus is
passed to mp_cpu_bus_init"), no dummy LAPIC device is required under the
CPU cluster device. Since the CPU cluster device is already present in
the Stoneyridge chipset devicetree, drop the whole CPU cluster part from
the mainboard's devicetrees.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8918c14be25ac9756926a9c6a2806a3dceced42a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68317
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held
2022-10-12 19:07:15 +02:00
parent b68e22409d
commit a5f11ebdd7
8 changed files with 0 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/amd/gardenia/devicetree.cb
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@ -7,9 +7,6 @@ chip soc/amd/stoneyridge
{ {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1
}" }"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1410 inherit subsystemid 0x1022 0x1410 inherit
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex

4
src/mainboard/amd/padmelon/devicetree.cb
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@ -3,10 +3,6 @@
chip soc/amd/stoneyridge chip soc/amd/stoneyridge
register "uma_mode" = "UMAMODE_AUTO_LEGACY" register "uma_mode" = "UMAMODE_AUTO_LEGACY"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
subsystemid 0x1022 0x1410 inherit subsystemid 0x1022 0x1410 inherit
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex

3
src/mainboard/google/kahlee/variants/aleena/devicetree.cb
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@ -44,9 +44,6 @@ chip soc/amd/stoneyridge
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL" GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 0.2 off end # IOMMU (Disabled for performance and battery)

3
src/mainboard/google/kahlee/variants/careena/devicetree.cb
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@ -44,9 +44,6 @@ chip soc/amd/stoneyridge
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL" GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 0.2 off end # IOMMU (Disabled for performance and battery)

3
src/mainboard/google/kahlee/variants/grunt/devicetree.cb
View File

@ -44,9 +44,6 @@ chip soc/amd/stoneyridge
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL" GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 0.2 off end # IOMMU (Disabled for performance and battery)

3
src/mainboard/google/kahlee/variants/liara/devicetree.cb
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@ -43,9 +43,6 @@ chip soc/amd/stoneyridge
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL" GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 0.2 off end # IOMMU (Disabled for performance and battery)

3
src/mainboard/google/kahlee/variants/nuwani/devicetree.cb
View File

@ -47,9 +47,6 @@ chip soc/amd/stoneyridge
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL" GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 0.2 off end # IOMMU (Disabled for performance and battery)

3
src/mainboard/google/kahlee/variants/treeya/devicetree.cb
View File

@ -47,9 +47,6 @@ chip soc/amd/stoneyridge
register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \ register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | \
GPIO_I2C2_SCL | GPIO_I2C3_SCL" GPIO_I2C2_SCL | GPIO_I2C3_SCL"
device cpu_cluster 0 on
device lapic 10 on end
end
device domain 0 on device domain 0 on
device pci 0.0 on end # Root Complex device pci 0.0 on end # Root Complex
device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 0.2 off end # IOMMU (Disabled for performance and battery)