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soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freq

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Factor out the get_pstate_core_freq function from the SoC's acpi.c files
to both avoid duplication and to also be able to use the same function
in the TSC frequency calculation in a follow-up patch. The family 17h
and 19h SoCs use the same frequency encoding in the P state MSRs while
the family 1Ah SoCs use a different encoding. The family 15h and 16h
SoCs use another encoding, but since this isn't implemented in
Stoneyridge's acpi.c, this will be added in a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit is contained in:
Felix Held
2023-03-24 16:30:55 +01:00
parent c08d804f01
commit a63f859553
19 changed files with 99 additions and 191 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/amd/cezanne/Kconfig
View File

@@ -39,6 +39,7 @@ config SOC_AMD_CEZANNE
select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_APOB_HASH
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_EMMC
select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_GRAPHICS

39
src/soc/amd/cezanne/acpi.c
View File

@@ -13,11 +13,9 @@
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/cpuid.h> #include <cpu/amd/cpuid.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/msr.h>
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
@@ -95,43 +93,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
} }
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
/* Core frequency divisor ID */
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div == 0) {
return 0;
} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
&& (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
/* Allow 1/8 integer steps for this range */
valid_freq_divisor = true;
} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
&& (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
/* Only allow 1/4 integer steps for this range */
valid_freq_divisor = true;
} else {
valid_freq_divisor = false;
}
if (valid_freq_divisor) {
/* 25 * core_freq_mul / (core_freq_div / 8) */
core_freq =
((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
} else {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
core_freq_div);
core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
}
return core_freq;
}
const acpi_cstate_t cstate_cfg_table[] = { const acpi_cstate_t cstate_cfg_table[] = {
[0] = { [0] = {
.ctype = 1, .ctype = 1,

5
src/soc/amd/cezanne/include/soc/msr.h
View File

@@ -17,11 +17,6 @@ union pstate_msr {
uint64_t raw; uint64_t raw;
}; };
#define PSTATE_DEF_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_CORE_FREQ_BASE 25
#define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16

12
src/soc/amd/common/block/cpu/Kconfig
View File

@@ -39,6 +39,18 @@ config ACPI_CPU_STRING
endif # SOC_AMD_COMMON_BLOCK_NONCAR endif # SOC_AMD_COMMON_BLOCK_NONCAR
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
bool
help
Select this option to include code to calculate the CPU frequency
from the P state MSR values on AMD CPU families 17h and 19h.
config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
bool
help
Select this option to include code to calculate the CPU frequency
from the P state MSR values on AMD CPU family 1Ah.
config SOC_AMD_COMMON_BLOCK_MCA_COMMON config SOC_AMD_COMMON_BLOCK_MCA_COMMON
bool bool
help help

16
src/soc/amd/common/block/cpu/tsc/Makefile.inc
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@@ -1,4 +1,20 @@
## SPDX-License-Identifier: GPL-2.0-only ## SPDX-License-Identifier: GPL-2.0-only
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y) ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y)
bootblock-y += tsc_freq.c bootblock-y += tsc_freq.c

48
src/soc/amd/common/block/cpu/tsc/cpufreq_17_19.c Normal file
View File

@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h>
#include <console/console.h>
#include <soc/msr.h>
#include <types.h>
#define PSTATE_DEF_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_CORE_FREQ_BASE 25
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
/* Core frequency divisor ID */
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div == 0) {
return 0;
} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
&& (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
/* Allow 1/8 integer steps for this range */
valid_freq_divisor = true;
} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
&& (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
/* Only allow 1/4 integer steps for this range */
valid_freq_divisor = true;
} else {
valid_freq_divisor = false;
}
if (valid_freq_divisor) {
/* 25 * core_freq_mul / (core_freq_div / 8) */
core_freq =
((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
} else {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
core_freq_div);
core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
}
return core_freq;
}

18
src/soc/amd/common/block/cpu/tsc/cpufreq_1a.c Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <amdblocks/cpu.h>
#include <soc/msr.h>
#include <types.h>
#define PSTATE_DEF_CORE_FREQ_BASE 5
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq_mul;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_11;
/* CPU frequency is 5 * core_freq_mul */
return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul;
}

1
src/soc/amd/glinda/Kconfig
View File

@@ -44,6 +44,7 @@ config SOC_AMD_GLINDA
select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct

13
src/soc/amd/glinda/acpi.c
View File

@@ -16,11 +16,9 @@
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/cpuid.h> #include <cpu/amd/cpuid.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/msr.h>
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
@@ -98,17 +96,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
} }
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq_mul;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_11;
/* CPU frequency is 5 * core_freq_mul */
return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul;
}
const acpi_cstate_t cstate_cfg_table[] = { const acpi_cstate_t cstate_cfg_table[] = {
[0] = { [0] = {
.ctype = 1, .ctype = 1,

2
src/soc/amd/glinda/include/soc/msr.h
View File

@@ -20,8 +20,6 @@ union pstate_msr {
uint64_t raw; uint64_t raw;
}; };
#define PSTATE_DEF_CORE_FREQ_BASE 5
#define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16

1
src/soc/amd/mendocino/Kconfig
View File

@@ -43,6 +43,7 @@ config SOC_AMD_REMBRANDT_BASE
select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_APOB_HASH
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_EMMC
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES

39
src/soc/amd/mendocino/acpi.c
View File

@@ -15,11 +15,9 @@
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/cpuid.h> #include <cpu/amd/cpuid.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/msr.h>
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
@@ -97,43 +95,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
} }
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
/* Core frequency divisor ID */
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div == 0) {
return 0;
} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
&& (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
/* Allow 1/8 integer steps for this range */
valid_freq_divisor = true;
} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
&& (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
/* Only allow 1/4 integer steps for this range */
valid_freq_divisor = true;
} else {
valid_freq_divisor = false;
}
if (valid_freq_divisor) {
/* 25 * core_freq_mul / (core_freq_div / 8) */
core_freq =
((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
} else {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
core_freq_div);
core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
}
return core_freq;
}
const acpi_cstate_t cstate_cfg_table[] = { const acpi_cstate_t cstate_cfg_table[] = {
[0] = { [0] = {
.ctype = 1, .ctype = 1,

5
src/soc/amd/mendocino/include/soc/msr.h
View File

@@ -18,11 +18,6 @@ union pstate_msr {
uint64_t raw; uint64_t raw;
}; };
#define PSTATE_DEF_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_CORE_FREQ_BASE 25
#define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16

1
src/soc/amd/phoenix/Kconfig
View File

@@ -44,6 +44,7 @@ config SOC_AMD_PHOENIX
select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_APOB_HASH
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct

39
src/soc/amd/phoenix/acpi.c
View File

@@ -16,11 +16,9 @@
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <console/console.h> #include <console/console.h>
#include <cpu/amd/cpuid.h> #include <cpu/amd/cpuid.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/iomap.h> #include <soc/iomap.h>
#include <soc/msr.h>
#include <types.h> #include <types.h>
#include "chip.h" #include "chip.h"
@@ -98,43 +96,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */
} }
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
/* Core frequency divisor ID */
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div == 0) {
return 0;
} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
&& (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
/* Allow 1/8 integer steps for this range */
valid_freq_divisor = true;
} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
&& (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
/* Only allow 1/4 integer steps for this range */
valid_freq_divisor = true;
} else {
valid_freq_divisor = false;
}
if (valid_freq_divisor) {
/* 25 * core_freq_mul / (core_freq_div / 8) */
core_freq =
((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
} else {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
core_freq_div);
core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
}
return core_freq;
}
const acpi_cstate_t cstate_cfg_table[] = { const acpi_cstate_t cstate_cfg_table[] = {
[0] = { [0] = {
.ctype = 1, .ctype = 1,

5
src/soc/amd/phoenix/include/soc/msr.h
View File

@@ -20,11 +20,6 @@ union pstate_msr {
uint64_t raw; uint64_t raw;
}; };
#define PSTATE_DEF_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_CORE_FREQ_BASE 25
#define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define MSR_CPPC_CAPABILITY_1 0xc00102b0
#define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24
#define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16

1
src/soc/amd/picasso/Kconfig
View File

@@ -36,6 +36,7 @@ config SOC_AMD_PICASSO
select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_AOAC
select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS
select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_GRAPHICS
select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_HAS_ESPI

39
src/soc/amd/picasso/acpi.c
View File

@@ -11,7 +11,6 @@
#include <arch/ioapic.h> #include <arch/ioapic.h>
#include <arch/smp/mpspec.h> #include <arch/smp/mpspec.h>
#include <cpu/amd/cpuid.h> #include <cpu/amd/cpuid.h>
#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h> #include <cpu/x86/smm.h>
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
@@ -23,7 +22,6 @@
#include <amdblocks/ioapic.h> #include <amdblocks/ioapic.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <soc/msr.h>
#include <soc/southbridge.h> #include <soc/southbridge.h>
#include <version.h> #include <version.h>
#include "chip.h" #include "chip.h"
@@ -99,43 +97,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */
} }
uint32_t get_pstate_core_freq(union pstate_msr pstate_reg)
{
uint32_t core_freq, core_freq_mul, core_freq_div;
bool valid_freq_divisor;
/* Core frequency multiplier */
core_freq_mul = pstate_reg.cpu_fid_0_7;
/* Core frequency divisor ID */
core_freq_div = pstate_reg.cpu_dfs_id;
if (core_freq_div == 0) {
return 0;
} else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN)
&& (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) {
/* Allow 1/8 integer steps for this range */
valid_freq_divisor = true;
} else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX)
&& (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) {
/* Only allow 1/4 integer steps for this range */
valid_freq_divisor = true;
} else {
valid_freq_divisor = false;
}
if (valid_freq_divisor) {
/* 25 * core_freq_mul / (core_freq_div / 8) */
core_freq =
((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div));
} else {
printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n",
core_freq_div);
core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul);
}
return core_freq;
}
const acpi_cstate_t cstate_cfg_table[] = { const acpi_cstate_t cstate_cfg_table[] = {
[0] = { [0] = {
.ctype = 1, .ctype = 1,

5
src/soc/amd/picasso/include/soc/msr.h
View File

@@ -21,9 +21,4 @@ union pstate_msr {
uint64_t raw; uint64_t raw;
}; };
#define PSTATE_DEF_FREQ_DIV_MIN 0x8
#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A
#define PSTATE_DEF_FREQ_DIV_MAX 0x3E
#define PSTATE_DEF_CORE_FREQ_BASE 25
#endif /* AMD_PICASSO_MSR_H */ #endif /* AMD_PICASSO_MSR_H */