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Whitespace fixes.

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Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2008-10-06 21:00:46 +00:00
parent 69e9cc4fbd
commit a643ea3beb
30 changed files with 1385 additions and 1412 deletions
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338
src/mainboard/nvidia/l1_2pvv/Config.lb
View File

@ -40,7 +40,7 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## ##
@ -82,48 +82,48 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o #object reset.o
if HAVE_ACPI_TABLES if HAVE_ACPI_TABLES
object acpi_tables.o object acpi_tables.o
object fadt.o object fadt.o
makerule dsdt.c makerule dsdt.c
depends "$(MAINBOARD)/dx/dsdt_lb.dsl" depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl" action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
action "mv dsdt_lb.hex dsdt.c" action "mv dsdt_lb.hex dsdt.c"
end end
object ./dsdt.o object ./dsdt.o
#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
if ACPI_SSDTX_NUM if ACPI_SSDTX_NUM
makerule ssdt6.c makerule ssdt6.c
depends "$(MAINBOARD)/dx/pci6.asl" depends "$(MAINBOARD)/dx/pci6.asl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl" action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci6.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex" action "perl -pi -e 's/AmlCode/AmlCode_ssdt6/g' pci6.hex"
action "mv pci6.hex ssdt6.c" action "mv pci6.hex ssdt6.c"
end end
object ./ssdt6.o object ./ssdt6.o
makerule ssdt5.c makerule ssdt5.c
depends "$(MAINBOARD)/dx/pci5.asl" depends "$(MAINBOARD)/dx/pci5.asl"
action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl" action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci5.asl"
action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex" action "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
action "mv pci5.hex ssdt5.c" action "mv pci5.hex ssdt5.c"
end end
object ./ssdt5.o object ./ssdt5.o
end end
end end
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end end
else else
makerule ./cache_as_ram_auto.inc makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end end
end end
@ -132,11 +132,11 @@ end
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
else else
if CONFIG_AP_CODE_IN_CAR if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h" depends "$(MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end end
ldscript /arch/i386/init/ldscript_apc.lb ldscript /arch/i386/init/ldscript_apc.lb
end end
end end
@ -159,13 +159,13 @@ end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
end end
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds ldscript /cpu/amd/car/cache_as_ram.lds
end end
end end
@ -257,162 +257,162 @@ if CONFIG_CHIP_NAME
end end
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_F chip cpu/amd/socket_F
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on device pci 18.0 on
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/mcp55 chip southbridge/nvidia/mcp55
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627ehg chip superio/winbond/w83627ehg
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off # Com2 device pnp 2e.3 off # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO_GAME_MIDI device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm 0-1-0 chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm 0-1-1 chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic #dimm 1-0-0 chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic #dimm 1-0-1 chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic #dimm 1-1-0 chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic #dimm 1-1-1 chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end # SM end # SM
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1 # chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic #PCIXB Slot1 # chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic #PCIXB Slot2 # chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic #PCI Slot1 # chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic #Master MCP55 PCI-E # chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic #Slave MCP55 PCI-E # chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end # device i2c 55 on end
# end # end
chip drivers/generic/generic #MAC EEPROM chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
end # SM end # SM
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI device pci 6.0 on end # PCI
device pci 6.1 on end # AZA device pci 6.1 on end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 1
device pci 18.0 on device pci 18.0 on
# devices on link 2, link 2 == LDT 2 # devices on link 2, link 2 == LDT 2
chip southbridge/nvidia/mcp55 chip southbridge/nvidia/mcp55
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on end # LPC device pci 1.0 on end # LPC
device pci 1.1 on end # SM 0 device pci 1.1 on end # SM 0
device pci 2.0 off end # USB 1.1 device pci 2.0 off end # USB 1.1
device pci 2.1 off end # USB 2 device pci 2.1 off end # USB 2
device pci 4.0 off end # IDE device pci 4.0 off end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 off end # PCI device pci 6.0 off end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 on end # PCI E 1 device pci e.0 on end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
@ -422,15 +422,15 @@ chip northbridge/amd/amdk8/root_complex
end # PCI domain end # PCI domain
# chip drivers/generic/debug # chip drivers/generic/debug
# device pnp 0.0 off end # chip name # device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all # device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 on end # mem # device pnp 0.2 on end # mem
# device pnp 0.3 off end # cpuid # device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr # device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size # device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc # device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io # device pnp 0.8 off end # io
# device pnp 0.9 off end # io # device pnp 0.9 off end # io
# end # end
end #root_complex end #root_complex

42
src/mainboard/nvidia/l1_2pvv/apc_auto.c
View File

@ -44,7 +44,7 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#if CONFIG_USE_INIT == 0 #if CONFIG_USE_INIT == 0
#include "lib/memcpy.c" #include "lib/memcpy.c"
#endif #endif
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
@ -52,10 +52,10 @@
#if 0 #if 0
static void post_code(uint8_t value) { static void post_code(uint8_t value) {
#if 1 #if 1
int i; int i;
for(i=0;i<0x80000;i++) { for(i=0;i<0x80000;i++) {
outb(value, 0x80); outb(value, 0x80);
} }
#endif #endif
} }
#endif #endif
@ -87,14 +87,14 @@ static void post_code(uint8_t value) {
void hardwaremain(int ret_addr) void hardwaremain(int ret_addr)
{ {
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id; struct node_core_id id;
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);
@ -102,29 +102,29 @@ void hardwaremain(int ret_addr)
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/ */
__asm__ volatile ( __asm__ volatile (
"movl %0, %%edi\n\t" "movl %0, %%edi\n\t"
"jmp *%%edi\n\t" "jmp *%%edi\n\t"
:: "a"(ret_addr) :: "a"(ret_addr)
); );
} }
struct eregs { struct eregs {
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi; uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
uint32_t vector; uint32_t vector;
uint32_t error_code; uint32_t error_code;
uint32_t eip; uint32_t eip;
uint32_t cs; uint32_t cs;
uint32_t eflags; uint32_t eflags;
}; };
void x86_exception(struct eregs *info) void x86_exception(struct eregs *info)
{ {
do { do {
hlt(); hlt();
} while(1); } while(1);
} }

214
src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
View File

@ -83,7 +83,7 @@
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0 #if CONFIG_USE_INIT == 0
#include "lib/memcpy.c" #include "lib/memcpy.c"
#endif #endif
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
@ -135,12 +135,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define MCP55_PCI_E_X_1 4 #define MCP55_PCI_E_X_1 4
#define MCP55_MB_SETUP \ #define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
@ -164,70 +164,70 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20; byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0); dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16); dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */ /* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) { if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) { if (last_boot_normal_x) {
goto normal_image; goto normal_image;
} else { } else {
goto fallback_image; goto fallback_image;
} }
} }
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
/* Setup the mcp55 */ /* Setup the mcp55 */
mcp55_enable_rom(); mcp55_enable_rom();
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) { if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image; goto normal_image;
} }
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
else if (do_normal_boot()) { else if (do_normal_boot()) {
goto normal_image; goto normal_image;
} }
else { else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
#if HAVE_FAILOVER_BOOT==1 #if HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image" __asm__ volatile ("jmp __fallback_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
) )
#endif #endif
; ;
} }
@ -263,23 +263,23 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif #endif
}; };
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0; int needs_reset = 0;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
if (bist == 0) { if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
} }
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0); pnp_write_config(SERIAL_DEV, 0x24, 0);
w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE); w83627ehg_enable_dev(SERIAL_DEV, TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV); pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map(); setup_mb_resource_map();
uart_init(); uart_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
@ -289,79 +289,79 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
mcp55_enable_usbdebug_direct(DBGP_DEFAULT); mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
early_usbdebug_direct_init(); early_usbdebug_direct_init();
#endif #endif
console_init(); console_init();
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
#if MEM_TRAIN_SEQ == 1 #if MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif #endif
setup_coherent_ht_domain(); // routing table and start other core0 setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system, * So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case) * (there may be apic id conflicts in that case)
*/ */
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if K8_SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
} }
enable_fid_change(); enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
} }
#endif #endif
needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x(); needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now; //It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); enable_smbus();
memreset_setup(); memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output //do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */ /* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID // init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
} }

4
src/mainboard/nvidia/l1_2pvv/cmos.layout
View File

@ -53,14 +53,14 @@ entries
395 1 e 1 hw_scrubber 395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects 396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock 397 2 e 8 max_mem_clock
399 1 e 2 dual_core 399 1 e 2 dual_core
400 1 e 1 power_on_after_fail 400 1 e 1 power_on_after_fail
412 4 e 6 debug_level 412 4 e 6 debug_level
416 4 e 7 boot_first 416 4 e 7 boot_first
420 4 e 7 boot_second 420 4 e 7 boot_second
424 4 e 7 boot_third 424 4 e 7 boot_third
428 4 h 0 boot_index 428 4 h 0 boot_index
432 8 h 0 boot_countdown 432 8 h 0 boot_countdown
440 4 e 9 slow_cpu 440 4 e 9 slow_cpu
444 1 e 1 nmi 444 1 e 1 nmi
445 1 e 1 iommu 445 1 e 1 iommu

95
src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
View File

@ -37,27 +37,27 @@
struct mb_sysconf_t mb_sysconf; struct mb_sysconf_t mb_sysconf;
unsigned pci1234x[] = unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0, 0x0000ff0,
0x0000ff0, 0x0000ff0,
0x0000ff0, 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0 // 0x0000ff0
}; };
unsigned hcdnx[] = unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020, 0x20202020,
0x20202020, 0x20202020,
0x20202020, 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
}; };
@ -67,27 +67,27 @@ static unsigned get_bus_conf_done = 0;
static unsigned get_hcid(unsigned i) static unsigned get_hcid(unsigned i)
{ {
unsigned id = 0; unsigned id = 0;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
device_t dev; device_t dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
switch (dev->device) { switch (dev->device) {
case 0x0369: //IO55 case 0x0369: //IO55
id = 4; id = 4;
break; break;
} }
// we may need more way to find out hcid: subsystem id? GPIO read ? // we may need more way to find out hcid: subsystem id? GPIO read ?
// we need use id for 1. bus num, 2. mptable, 3. acpi table // we need use id for 1. bus num, 2. mptable, 3. acpi table
return id; return id;
} }
void get_bus_conf(void) void get_bus_conf(void)
@ -96,27 +96,26 @@ void get_bus_conf(void)
unsigned apicid_base; unsigned apicid_base;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
device_t dev; device_t dev;
int i, j; int i, j;
if (get_bus_conf_done) if (get_bus_conf_done)
return; //do it only once return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
sysconf.mb = &mb_sysconf; sysconf.mb = &mb_sysconf;
m = sysconf.mb; m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t)); memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for (i = 0; i < sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
for (i = 0; i < sysconf.hc_possible_num; i++) { get_sblk_pci1234();
sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i];
}
get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
@ -132,22 +131,22 @@ void get_bus_conf(void)
if (!(sysconf.pci1234[i] & 0x1)) if (!(sysconf.pci1234[i] & 0x1))
continue; continue;
busn_min = (sysconf.pci1234[i] >> 16) & 0xff; busn_min = (sysconf.pci1234[i] >> 16) & 0xff;
busn_max = (sysconf.pci1234[i] >> 24) & 0xff; busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
for (j = busn_min; j <= busn_max; j++) for (j = busn_min; j <= busn_max; j++)
m->bus_type[j] = 1; m->bus_type[j] = 1;
if(m->bus_isa <= busn_max) if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1; m->bus_isa = busn_max + 1;
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa); printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa);
} }
/* MCP55b */ /* MCP55b */
for (i = 1; i < sysconf.hc_possible_num; i++) { for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x0f)) if (!(sysconf.pci1234[i] & 0x0f))
continue; continue;
// check hcid type here // check hcid type here
sysconf.hcid[i] = get_hcid(i); sysconf.hcid[i] = get_hcid(i);
if (!sysconf.hcid[i]) if (!sysconf.hcid[i])
continue; //unknown co processor continue; //unknown co processor
m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff; m->bus_mcp55b = (sysconf.pci1234[1]>>16) & 0xff;
@ -160,6 +159,6 @@ void get_bus_conf(void)
apicid_base = CONFIG_MAX_PHYSICAL_CPUS; apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif #endif
m->apicid_mcp55 = apicid_base+0; m->apicid_mcp55 = apicid_base+0;
m->apicid_mcp55b = apicid_base+1; m->apicid_mcp55b = apicid_base+1;
} }

68
src/mainboard/nvidia/l1_2pvv/irq_tables.c
View File

@ -20,10 +20,10 @@
*/ */
/* This file was generated by getpir.c, do not modify! /* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify) * (but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/ */
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
@ -38,18 +38,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
@ -62,19 +62,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
m = sysconf.mb; m = sysconf.mb;
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@ -100,25 +100,25 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, m->bus_mcp55, ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
for (i = 1; i < sysconf.hc_possible_num; i++) { for (i = 1; i < sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
} }
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk_info("done.\n"); printk_info("done.\n");

10
src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
View File

@ -23,11 +23,11 @@
#define MB_SYSCONF_H #define MB_SYSCONF_H
struct mb_sysconf_t { struct mb_sysconf_t {
unsigned char bus_isa; unsigned char bus_isa;
unsigned char bus_mcp55; unsigned char bus_mcp55;
unsigned char bus_mcp55b; unsigned char bus_mcp55b;
unsigned apicid_mcp55; unsigned apicid_mcp55;
unsigned apicid_mcp55b; unsigned apicid_mcp55b;
unsigned bus_type[256]; unsigned bus_type[256];
unsigned sbdnb; unsigned sbdnb;

100
src/mainboard/nvidia/l1_2pvv/mptable.c
View File

@ -31,34 +31,34 @@
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "NVIDIA "; static const char oem[8] = "NVIDIA ";
static const char productid[12] = "L1_2PVV "; static const char productid[12] = "L1_2PVV ";
struct mp_config_table *mc; struct mp_config_table *mc;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
int i,j; int i,j;
unsigned char apicpin[4]; unsigned char apicpin[4];
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig)); memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04; mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */ mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid)); memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0; mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0; mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR; mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0; mc->mpe_length = 0;
mc->mpe_checksum = 0; mc->mpe_checksum = 0;
mc->reserved = 0; mc->reserved = 0;
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
@ -66,20 +66,20 @@ void *smp_write_config_table(void *v)
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for (j = 0; j < 256 ; j++) { for (j = 0; j < 256 ; j++) {
if (m->bus_type[j]) if (m->bus_type[j])
smp_write_bus(mc, j, "PCI "); smp_write_bus(mc, j, "PCI ");
} }
smp_write_bus(mc, m->bus_isa, "ISA "); smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) if (res)
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
@ -93,17 +93,17 @@ void *smp_write_config_table(void *v)
dword = 0x43c6c643; dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00; dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0xd00012d2; dword = 0xd00012d2;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
if (m->bus_mcp55b) { if (m->bus_mcp55b) {
dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0)); dev = dev_find_slot(m->bus_mcp55b, PCI_DEVFN(m->sbdnb + 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) if (res)
smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base); smp_write_ioapic(mc, m->apicid_mcp55b, 0x11, res->base);
@ -111,13 +111,13 @@ void *smp_write_config_table(void *v)
dword = 0x43c60000; dword = 0x43c60000;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x81000000; dword = 0x81000000;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0xd00002d0; dword = 0xd00002d0;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
} }
@ -137,35 +137,35 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+6)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
//Slot PCIE //Slot PCIE
for (j = 2; j < 8; j++) { for (j = 2; j < 8; j++) {
device_t dev; device_t dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0)); dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 0x0a + j - 2 , 0));
if (!dev || !dev->enabled) if (!dev || !dev->enabled)
continue; continue;
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4; apicpin[i] = 0x10 + (2+j+i+4-sbdn%4)%4;
smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin); smp_write_intsrc_pci_bridge(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, dev, m->apicid_mcp55, apicpin);
} }
//Slot PCI 32 //Slot PCI 32
{ {
device_t dev; device_t dev;
dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0)); dev = dev_find_slot(m->bus_mcp55, PCI_DEVFN(sbdn + 6 , 0));
if (dev && dev->enabled) { if (dev && dev->enabled) {
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)

254
src/mainboard/tyan/s2912/Config.lb
View File

@ -40,7 +40,7 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## ##
@ -85,15 +85,15 @@ if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end end
else else
makerule ./cache_as_ram_auto.inc makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end end
end end
@ -102,11 +102,11 @@ end
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
else else
if CONFIG_AP_CODE_IN_CAR if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h" depends "$(MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end end
ldscript /arch/i386/init/ldscript_apc.lb ldscript /arch/i386/init/ldscript_apc.lb
end end
end end
@ -129,13 +129,13 @@ end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
end end
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds ldscript /cpu/amd/car/cache_as_ram.lds
end end
end end
@ -227,131 +227,131 @@ if CONFIG_CHIP_NAME
end end
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_F chip cpu/amd/socket_F
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on device pci 18.0 on
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/mcp55 chip southbridge/nvidia/mcp55
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO_GAME_MIDI device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm 0-1-0 chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm 0-1-1 chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic #dimm 1-0-0 chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic #dimm 1-0-1 chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic #dimm 1-1-0 chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic #dimm 1-1-1 chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end # SM end # SM
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1 # chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic #PCIXB Slot1 # chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic #PCIXB Slot2 # chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic #PCI Slot1 # chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic #Master MCP55 PCI-E # chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic #Slave MCP55 PCI-E # chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end # device i2c 55 on end
# end # end
chip drivers/generic/generic #MAC EEPROM chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
end # SM end # SM
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on end # PCI device pci 6.0 on end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
@ -364,15 +364,15 @@ chip northbridge/amd/amdk8/root_complex
end # PCI domain end # PCI domain
# chip drivers/generic/debug # chip drivers/generic/debug
# device pnp 0.0 off end # chip name # device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all # device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 on end # mem # device pnp 0.2 on end # mem
# device pnp 0.3 off end # cpuid # device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr # device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size # device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc # device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io # device pnp 0.8 off end # io
# device pnp 0.9 off end # io # device pnp 0.9 off end # io
# end # end
end #root_complex end #root_complex

45
src/mainboard/tyan/s2912/apc_auto.c
View File

@ -44,22 +44,11 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#if CONFIG_USE_INIT == 0 #if CONFIG_USE_INIT == 0
#include "lib/memcpy.c" #include "lib/memcpy.c"
#endif #endif
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
@ -87,14 +76,14 @@ static void post_code(uint8_t value) {
void hardwaremain(int ret_addr) void hardwaremain(int ret_addr)
{ {
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id; struct node_core_id id;
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);
@ -102,29 +91,29 @@ void hardwaremain(int ret_addr)
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/ */
__asm__ volatile ( __asm__ volatile (
"movl %0, %%edi\n\t" "movl %0, %%edi\n\t"
"jmp *%%edi\n\t" "jmp *%%edi\n\t"
:: "a"(ret_addr) :: "a"(ret_addr)
); );
} }
struct eregs { struct eregs {
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi; uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
uint32_t vector; uint32_t vector;
uint32_t error_code; uint32_t error_code;
uint32_t eip; uint32_t eip;
uint32_t cs; uint32_t cs;
uint32_t eflags; uint32_t eflags;
}; };
void x86_exception(struct eregs *info) void x86_exception(struct eregs *info)
{ {
do { do {
hlt(); hlt();
} while(1); } while(1);
} }

214
src/mainboard/tyan/s2912/cache_as_ram_auto.c
View File

@ -83,7 +83,7 @@
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0 #if CONFIG_USE_INIT == 0
#include "lib/memcpy.c" #include "lib/memcpy.c"
#endif #endif
#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/debug.c"
@ -133,12 +133,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define MCP55_PCI_E_X_0 1 #define MCP55_PCI_E_X_0 1
#define MCP55_MB_SETUP \ #define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
@ -162,71 +162,71 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20; byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
/*serial 0 */ /*serial 0 */
dword |= (1<<0); dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16); dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */ /* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) { if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) { if (last_boot_normal_x) {
goto normal_image; goto normal_image;
} else { } else {
goto fallback_image; goto fallback_image;
} }
} }
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
/* Setup the mcp55 */ /* Setup the mcp55 */
mcp55_enable_rom(); mcp55_enable_rom();
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) { if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image; goto normal_image;
} }
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
else if (do_normal_boot()) { else if (do_normal_boot()) {
goto normal_image; goto normal_image;
} }
else { else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
#if HAVE_FAILOVER_BOOT==1 #if HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image" __asm__ volatile ("jmp __fallback_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
) )
#endif #endif
; ;
} }
@ -262,20 +262,20 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif #endif
}; };
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0; int needs_reset = 0;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
if (bist == 0) { if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
} }
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
setup_mb_resource_map(); setup_mb_resource_map();
uart_init(); uart_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
@ -285,80 +285,80 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
mcp55_enable_usbdebug_direct(DBGP_DEFAULT); mcp55_enable_usbdebug_direct(DBGP_DEFAULT);
early_usbdebug_direct_init(); early_usbdebug_direct_init();
#endif #endif
console_init(); console_init();
print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n"); print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n"); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
#if MEM_TRAIN_SEQ == 1 #if MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif #endif
setup_coherent_ht_domain(); // routing table and start other core0 setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system, * So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case) * (there may be apic id conflicts in that case)
*/ */
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
/* it will set up chains and store link pair for optimization later */ /* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if K8_SET_FIDVID == 1 #if K8_SET_FIDVID == 1
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
} }
enable_fid_change(); enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid); init_fidvid_bsp(bsp_apicid);
// show final fid and vid // show final fid and vid
{ {
msr_t msr; msr_t msr;
msr=rdmsr(0xc0010042); msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n"); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
} }
#endif #endif
needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x(); needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too // fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now; //It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); enable_smbus();
memreset_setup(); memreset_setup();
//do we need apci timer, tsc...., only debug need it for better output //do we need apci timer, tsc...., only debug need it for better output
/* all ap stopped? */ /* all ap stopped? */
// init_timer(); // Need to use TMICT to synconize FID/VID // init_timer(); // Need to use TMICT to synconize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
} }

4
src/mainboard/tyan/s2912/cmos.layout
View File

@ -53,14 +53,14 @@ entries
395 1 e 1 hw_scrubber 395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects 396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock 397 2 e 8 max_mem_clock
399 1 e 2 dual_core 399 1 e 2 dual_core
400 1 e 1 power_on_after_fail 400 1 e 1 power_on_after_fail
412 4 e 6 debug_level 412 4 e 6 debug_level
416 4 e 7 boot_first 416 4 e 7 boot_first
420 4 e 7 boot_second 420 4 e 7 boot_second
424 4 e 7 boot_third 424 4 e 7 boot_third
428 4 h 0 boot_index 428 4 h 0 boot_index
432 8 h 0 boot_countdown 432 8 h 0 boot_countdown
440 4 e 9 slow_cpu 440 4 e 9 slow_cpu
444 1 e 1 nmi 444 1 e 1 nmi
445 1 e 1 iommu 445 1 e 1 iommu

114
src/mainboard/tyan/s2912/get_bus_conf.c
View File

@ -37,27 +37,27 @@
struct mb_sysconf_t mb_sysconf; struct mb_sysconf_t mb_sysconf;
unsigned pci1234x[] = unsigned pci1234x[] =
{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
//You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
0x0000ff0, 0x0000ff0,
0x0000ff0, 0x0000ff0,
0x0000ff0, 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0, // 0x0000ff0,
// 0x0000ff0 // 0x0000ff0
}; };
unsigned hcdnx[] = unsigned hcdnx[] =
{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020, 0x20202020,
0x20202020, 0x20202020,
0x20202020, 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
}; };
@ -67,27 +67,27 @@ static unsigned get_bus_conf_done = 0;
static unsigned get_hcid(unsigned i) static unsigned get_hcid(unsigned i)
{ {
unsigned id = 0; unsigned id = 0;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
device_t dev; device_t dev;
dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
switch (dev->device) { switch (dev->device) {
case 0x0369: //IO55 case 0x0369: //IO55
id = 4; id = 4;
break; break;
} }
// we may need more way to find out hcid: subsystem id? GPIO read ? // we may need more way to find out hcid: subsystem id? GPIO read ?
// we need use id for 1. bus num, 2. mptable, 3. acpi table // we need use id for 1. bus num, 2. mptable, 3. acpi table
return id; return id;
} }
void get_bus_conf(void) void get_bus_conf(void)
@ -96,25 +96,25 @@ void get_bus_conf(void)
unsigned apicid_base; unsigned apicid_base;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
device_t dev; device_t dev;
int i, j; int i, j;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
sysconf.mb = &mb_sysconf; sysconf.mb = &mb_sysconf;
m = sysconf.mb; m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t)); memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }
get_sblk_pci1234(); get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
@ -122,39 +122,37 @@ void get_bus_conf(void)
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* MCP55 */ /* MCP55 */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
if (dev) { if (dev) {
m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
} }
for(i=2; i<8;i++) { for(i=2; i<8;i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
if (dev) { if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
} }
} }
for(i=0; i< sysconf.hc_possible_num; i++) { for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff; unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
for (j = busn; j <= busn_max; j++) for (j = busn; j <= busn_max; j++)
m->bus_type[j] = 1; m->bus_type[j] = 1;
if(m->bus_isa <= busn_max) if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1; m->bus_isa = busn_max + 1;
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
} }
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1); apicid_base = get_apicid_base(1);

68
src/mainboard/tyan/s2912/irq_tables.c
View File

@ -20,10 +20,10 @@
*/ */
/* This file was generated by getpir.c, do not modify! /* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify) * (but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/ */
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
@ -38,18 +38,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
@ -62,19 +62,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
m = sysconf.mb; m = sysconf.mb;
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@ -100,25 +100,25 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i=1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
} }
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk_info("done.\n"); printk_info("done.\n");

6
src/mainboard/tyan/s2912/mb_sysconf.h
View File

@ -23,9 +23,9 @@
#define MB_SYSCONF_H #define MB_SYSCONF_H
struct mb_sysconf_t { struct mb_sysconf_t {
unsigned char bus_isa; unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1 unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55; unsigned apicid_mcp55;
unsigned bus_type[256]; unsigned bus_type[256];
}; };

96
src/mainboard/tyan/s2912/mptable.c
View File

@ -31,69 +31,69 @@
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN "; static const char oem[8] = "TYAN ";
static const char productid[12] = "S2895 "; static const char productid[12] = "S2895 ";
struct mp_config_table *mc; struct mp_config_table *mc;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
int i,j; int i,j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig)); memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04; mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */ mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid)); memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0; mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0; mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR; mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0; mc->mpe_length = 0;
mc->mpe_checksum = 0; mc->mpe_checksum = 0;
mc->reserved = 0; mc->reserved = 0;
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
m = sysconf.mb; m = sysconf.mb;
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for(j= 0; j < 256 ; j++) { for(j= 0; j < 256 ; j++) {
if(m->bus_type[j]) if(m->bus_type[j])
smp_write_bus(mc, j, "PCI "); smp_write_bus(mc, j, "PCI ");
} }
smp_write_bus(mc, m->bus_isa, "ISA "); smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
} }
dword = 0x43c6c643; dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00; dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0xd00002d2; dword = 0xd00002d2;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
} }
@ -112,30 +112,30 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) { for(j=7; j>=2; j--) {
if(!m->bus_mcp55[j]) continue; if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
} }
} }
for(j=0; j<1; j++) for(j=0; j<1; j++)
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);

256
src/mainboard/tyan/s2912_fam10/Config.lb
View File

@ -40,7 +40,7 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## ##
@ -87,14 +87,14 @@ if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./cache_as_ram_auto.o makerule ./cache_as_ram_auto.o
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end end
else else
makerule ./cache_as_ram_auto.inc makerule ./cache_as_ram_auto.inc
depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h" depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end end
end end
@ -103,11 +103,11 @@ end
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
else else
if CONFIG_AP_CODE_IN_CAR if CONFIG_AP_CODE_IN_CAR
makerule ./apc_auto.o makerule ./apc_auto.o
depends "$(MAINBOARD)/apc_auto.c option_table.h" depends "$(MAINBOARD)/apc_auto.c option_table.h"
action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@" action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
end end
ldscript /arch/i386/init/ldscript_apc.lb ldscript /arch/i386/init/ldscript_apc.lb
end end
end end
@ -130,13 +130,13 @@ end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
end end
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds ldscript /cpu/amd/car/cache_as_ram.lds
end end
end end
@ -230,136 +230,136 @@ end
dir /southbridge/nvidia/mcp55 dir /southbridge/nvidia/mcp55
chip northbridge/amd/amdfam10/root_complex chip northbridge/amd/amdfam10/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_F_1207 chip cpu/amd/socket_F_1207
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdfam10 #mc0 chip northbridge/amd/amdfam10 #mc0
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on end device pci 18.0 on end
device pci 18.0 on device pci 18.0 on
# SB on link 2.0. # SB on link 2.0.
chip southbridge/nvidia/mcp55 chip southbridge/nvidia/mcp55
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 on # Com2 device pnp 2e.3 on # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # SFI device pnp 2e.6 off # SFI
io 0x62 = 0x100 io 0x62 = 0x100
end end
device pnp 2e.7 off # GPIO_GAME_MIDI device pnp 2e.7 off # GPIO_GAME_MIDI
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # WDTO_PLED device pnp 2e.8 off end # WDTO_PLED
device pnp 2e.9 off end # GPIO_SUSLED device pnp 2e.9 off end # GPIO_SUSLED
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm 0-1-0 chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm 0-1-1 chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic #dimm 1-0-0 chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic #dimm 1-0-1 chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic #dimm 1-1-0 chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic #dimm 1-1-1 chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end # SM end # SM
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1 # chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic #PCIXB Slot1 # chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic #PCIXB Slot2 # chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic #PCI Slot1 # chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic #Master MCP55 PCI-E # chip drivers/generic/generic #Master MCP55 PCI-E
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic #Slave MCP55 PCI-E # chip drivers/generic/generic #Slave MCP55 PCI-E
# device i2c 55 on end # device i2c 55 on end
# end # end
chip drivers/generic/generic #MAC EEPROM chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
end # SM end # SM
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # IDE device pci 4.0 on end # IDE
device pci 5.0 on end # SATA 0 device pci 5.0 on end # SATA 0
device pci 5.1 on end # SATA 1 device pci 5.1 on end # SATA 1
device pci 5.2 on end # SATA 2 device pci 5.2 on end # SATA 2
device pci 6.0 on device pci 6.0 on
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 4.0 on end device pci 4.0 on end
register "rom_address" = "0xfff80000" register "rom_address" = "0xfff80000"
end end
end # PCI end # PCI
device pci 6.1 off end # AZA device pci 6.1 off end # AZA
device pci 8.0 on end # NIC device pci 8.0 on end # NIC
device pci 9.0 on end # NIC device pci 9.0 on end # NIC
device pci a.0 on end # PCI E 5 device pci a.0 on end # PCI E 5
device pci b.0 off end # PCI E 4 device pci b.0 off end # PCI E 4
device pci c.0 off end # PCI E 3 device pci c.0 off end # PCI E 3
device pci d.0 on end # PCI E 2 device pci d.0 on end # PCI E 2
device pci e.0 off end # PCI E 1 device pci e.0 off end # PCI E 1
device pci f.0 on end # PCI E 0 device pci f.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
@ -372,16 +372,16 @@ chip northbridge/amd/amdfam10/root_complex
end # PCI domain end # PCI domain
# chip drivers/generic/debug # chip drivers/generic/debug
# device pnp 0.0 off end # chip name # device pnp 0.0 off end # chip name
# device pnp 0.1 on end # pci_regs_all # device pnp 0.1 on end # pci_regs_all
# device pnp 0.2 on end # mem # device pnp 0.2 on end # mem
# device pnp 0.3 off end # cpuid # device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr # device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size # device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc # device pnp 0.7 off end # tsc
# device pnp 0.8 off end # io # device pnp 0.8 off end # io
# device pnp 0.9 off end # io # device pnp 0.9 off end # io
# end # end
end #root_complex end #root_complex

45
src/mainboard/tyan/s2912_fam10/apc_auto.c
View File

@ -44,22 +44,11 @@
#include "pc80/serial.c" #include "pc80/serial.c"
#if CONFIG_USE_INIT == 0 #if CONFIG_USE_INIT == 0
#include "lib/memcpy.c" #include "lib/memcpy.c"
#endif #endif
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c" #include "cpu/amd/model_fxx/apic_timer.c"
@ -87,14 +76,14 @@ static void post_code(uint8_t value) {
void hardwaremain(int ret_addr) void hardwaremain(int ret_addr)
{ {
struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); // in CACHE
struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE); // in RAM
struct node_core_id id; struct node_core_id id;
id = get_node_core_id_x(); id = get_node_core_id_x();
//FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP //FIXME: for USBDEBUG_DIRECT you need to make sure dbg_info get assigned in AP
print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n"); print_debug("CODE IN CACHE ON NODE:"); print_debug_hex8(id.nodeid); print_debug("\r\n");
train_ram(id.nodeid, sysinfo, sysinfox); train_ram(id.nodeid, sysinfo, sysinfox);
@ -102,29 +91,29 @@ void hardwaremain(int ret_addr)
go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp go back, but can not use stack any more, because we only keep ret_addr and can not restore esp, and ebp
*/ */
__asm__ volatile ( __asm__ volatile (
"movl %0, %%edi\n\t" "movl %0, %%edi\n\t"
"jmp *%%edi\n\t" "jmp *%%edi\n\t"
:: "a"(ret_addr) :: "a"(ret_addr)
); );
} }
struct eregs { struct eregs {
uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi; uint32_t eax, ecx, edx, ebx, esp, ebp, esi, edi;
uint32_t vector; uint32_t vector;
uint32_t error_code; uint32_t error_code;
uint32_t eip; uint32_t eip;
uint32_t cs; uint32_t cs;
uint32_t eflags; uint32_t eflags;
}; };
void x86_exception(struct eregs *info) void x86_exception(struct eregs *info)
{ {
do { do {
hlt(); hlt();
} while(1); } while(1);
} }

133
src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
View File

@ -49,7 +49,7 @@
#include "pc80/mc146818rtc_early.c" #include "pc80/mc146818rtc_early.c"
static void post_code(u8 value) { static void post_code(u8 value) {
outb(value, 0x80); outb(value, 0x80);
} }
#if USE_FAILOVER_IMAGE==0 #if USE_FAILOVER_IMAGE==0
@ -79,7 +79,7 @@ static void post_code(u8 value) {
#include "cpu/x86/bist.h" #include "cpu/x86/bist.h"
#if CONFIG_USE_INIT == 0 #if CONFIG_USE_INIT == 0
#include "lib/memcpy.c" #include "lib/memcpy.c"
#endif #endif
#include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/debug.c"
@ -128,12 +128,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define MCP55_PCI_E_X_0 1 #define MCP55_PCI_E_X_0 1
#define MCP55_MB_SETUP \ #define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+39, 0x00, 0x44,/* GPIO40 PCI_GNT2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+40, 0x00, 0x44,/* GPIO41 PCI_REQ2 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
@ -157,72 +157,72 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20; byte |= 0x20;
pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
/*serial 0 */ /*serial 0 */
dword |= (1<<0); dword |= (1<<0);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16); dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */ /* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) { if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) { if (last_boot_normal_x) {
goto normal_image; goto normal_image;
} else { } else {
goto fallback_image; goto fallback_image;
} }
} }
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn(); set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
/* Setup the mcp55 */ /* Setup the mcp55 */
mcp55_enable_rom(); mcp55_enable_rom();
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
if (bios_reset_detected() && last_boot_normal_x) { if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image; goto normal_image;
} }
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
else if (do_normal_boot()) { else if (do_normal_boot()) {
goto normal_image; goto normal_image;
} }
else { else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
#if HAVE_FAILOVER_BOOT==1 #if HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image" __asm__ volatile ("jmp __fallback_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
) )
#endif #endif
; ;
} }
@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE); struct sys_info *sysinfo = (struct sys_info *)(DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0; u32 bsp_apicid = 0;
u32 val; u32 val;
@ -261,15 +261,15 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x30); post_code(0x30);
if (bist == 0) { if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
} }
post_code(0x32); post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
printk_debug("\n"); printk_debug("\n");
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
@ -286,7 +286,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk_debug("bsp_apicid = %02x \n", bsp_apicid); printk_debug("bsp_apicid = %02x \n", bsp_apicid);
printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx); printk_debug("cpu_init_detectedx = %08x \n", cpu_init_detectedx);
/* Setup sysinfo defaults */ /* Setup sysinfo defaults */
set_sysinfo_in_ram(0); set_sysinfo_in_ram(0);
@ -308,9 +307,9 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* wait for all the APs core0 started by finalize_node_setup. */ /* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once. /* FIXME: A bunch of cores are going to start output to serial at once.
It would be nice to fixup prink spinlocks for ROM XIP mode. * It would be nice to fixup prink spinlocks for ROM XIP mode.
I think it could be done by putting the spinlock flag in the cache * I think it could be done by putting the spinlock flag in the cache
of the BSP located right after sysinfo. * of the BSP located right after sysinfo.
*/ */
wait_all_core0_started(); wait_all_core0_started();
@ -329,7 +328,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); printk_debug("\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only /* FIXME: The sb fid change may survive the warm reset and only
need to be done once.*/ * need to be done once.*/
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x39); post_code(0x39);
@ -357,7 +356,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
} }
if (wants_reset) if (wants_reset)
printk_debug("mcp55_early_setup_x wanted additional reset!\n"); printk_debug("mcp55_early_setup_x wanted additional reset!\n");
post_code(0x3B); post_code(0x3B);

4
src/mainboard/tyan/s2912_fam10/cmos.layout
View File

@ -53,14 +53,14 @@ entries
395 1 e 1 hw_scrubber 395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects 396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock 397 2 e 8 max_mem_clock
399 1 e 2 quad_core 399 1 e 2 quad_core
400 1 e 1 power_on_after_fail 400 1 e 1 power_on_after_fail
412 4 e 6 debug_level 412 4 e 6 debug_level
416 4 e 7 boot_first 416 4 e 7 boot_first
420 4 e 7 boot_second 420 4 e 7 boot_second
424 4 e 7 boot_third 424 4 e 7 boot_third
428 4 h 0 boot_index 428 4 h 0 boot_index
432 8 h 0 boot_countdown 432 8 h 0 boot_countdown
440 4 e 9 slow_cpu 440 4 e 9 slow_cpu
444 1 e 1 nmi 444 1 e 1 nmi
445 1 e 1 iommu 445 1 e 1 iommu

57
src/mainboard/tyan/s2912_fam10/get_bus_conf.c
View File

@ -72,62 +72,61 @@ void get_bus_conf(void)
unsigned apicid_base; unsigned apicid_base;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
device_t dev; device_t dev;
int i, j; int i, j;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done==1) return; //do it only once
get_bus_conf_done = 1; get_bus_conf_done = 1;
sysconf.mb = &mb_sysconf; sysconf.mb = &mb_sysconf;
m = sysconf.mb; m = sysconf.mb;
memset(m, 0, sizeof(struct mb_sysconf_t)); memset(m, 0, sizeof(struct mb_sysconf_t));
sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); sysconf.hc_possible_num = ARRAY_SIZE(pci1234x);
for(i=0;i<sysconf.hc_possible_num; i++) { for(i=0;i<sysconf.hc_possible_num; i++) {
sysconf.pci1234[i] = pci1234x[i]; sysconf.pci1234[i] = pci1234x[i];
sysconf.hcdn[i] = hcdnx[i]; sysconf.hcdn[i] = hcdnx[i];
} }
get_pci1234(); get_pci1234();
m->bus_type[0] = 1; //pci m->bus_type[0] = 1; //pci
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
/* MCP55 */ /* MCP55 */
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0));
if (dev) { if (dev) {
m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06);
} }
for(i=2; i<8;i++) { for(i=2; i<8;i++) {
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0));
if (dev) { if (dev) {
m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
} }
else { else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 );
} }
} }
for(i=0; i< sysconf.hc_possible_num; i++) { for(i=0; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff; unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
for (j = busn; j <= busn_max; j++) for (j = busn; j <= busn_max; j++)
m->bus_type[j] = 1; m->bus_type[j] = 1;
if(m->bus_isa <= busn_max) if(m->bus_isa <= busn_max)
m->bus_isa = busn_max + 1; m->bus_isa = busn_max + 1;
printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); printk_debug("i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
} }
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1); apicid_base = get_apicid_base(1);

68
src/mainboard/tyan/s2912_fam10/irq_tables.c
View File

@ -20,10 +20,10 @@
*/ */
/* This file was generated by getpir.c, do not modify! /* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify) * (but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up * Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/ */
#include <console/console.h> #include <console/console.h>
#include <device/pci.h> #include <device/pci.h>
@ -38,18 +38,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
@ -62,19 +62,19 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
m = sysconf.mb; m = sysconf.mb;
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@ -100,13 +100,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, m->bus_mcp55[0], ((sbdn+6)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
for(i=1; i< sysconf.hc_possible_num; i++) { for(i=1; i< sysconf.hc_possible_num; i++) {
if(!(sysconf.pci1234[i] & 0x1) ) continue; if(!(sysconf.pci1234[i] & 0x1) ) continue;
unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
unsigned devn = sysconf.hcdn[i] & 0xff; unsigned devn = sysconf.hcdn[i] & 0xff;
write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
} }
#if CBB #if CBB
@ -120,14 +120,14 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk_info("done.\n"); printk_info("done.\n");

6
src/mainboard/tyan/s2912_fam10/mb_sysconf.h
View File

@ -23,9 +23,9 @@
#define MB_SYSCONF_H #define MB_SYSCONF_H
struct mb_sysconf_t { struct mb_sysconf_t {
unsigned char bus_isa; unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1 unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55; unsigned apicid_mcp55;
unsigned bus_type[256]; unsigned bus_type[256];
}; };

96
src/mainboard/tyan/s2912_fam10/mptable.c
View File

@ -31,69 +31,69 @@
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN "; static const char oem[8] = "TYAN ";
static const char productid[12] = "S2895 "; static const char productid[12] = "S2895 ";
struct mp_config_table *mc; struct mp_config_table *mc;
struct mb_sysconf_t *m; struct mb_sysconf_t *m;
unsigned sbdn; unsigned sbdn;
int i,j; int i,j;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig)); memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04; mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */ mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid)); memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0; mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0; mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR; mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0; mc->mpe_length = 0;
mc->mpe_checksum = 0; mc->mpe_checksum = 0;
mc->reserved = 0; mc->reserved = 0;
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
m = sysconf.mb; m = sysconf.mb;
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for(j= 0; j < 256 ; j++) { for(j= 0; j < 256 ; j++) {
if(m->bus_type[j]) if(m->bus_type[j])
smp_write_bus(mc, j, "PCI "); smp_write_bus(mc, j, "PCI ");
} }
smp_write_bus(mc, m->bus_isa, "ISA "); smp_write_bus(mc, m->bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base); smp_write_ioapic(mc, m->apicid_mcp55, 0x11, res->base);
} }
dword = 0x43c6c643; dword = 0x43c6c643;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x81001a00; dword = 0x81001a00;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0xd00002d2; dword = 0xd00002d2;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
} }
@ -112,30 +112,30 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_mcp55, 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_mcp55, 0xf);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+2)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|0, m->apicid_mcp55, 0x14); // 20
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|1, m->apicid_mcp55, 0x17); // 23
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+5)<<2)|2, m->apicid_mcp55, 0x15); // 21
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+8)<<2)|0, m->apicid_mcp55, 0x16); // 22
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+9)<<2)|0, m->apicid_mcp55, 0x15); // 21
for(j=7; j>=2; j--) { for(j=7; j>=2; j--) {
if(!m->bus_mcp55[j]) continue; if(!m->bus_mcp55[j]) continue;
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[j], (0x00<<2)|i, m->apicid_mcp55, 0x10 + (2+j+i+4-sbdn%4)%4);
} }
} }
for(j=0; j<1; j++) for(j=0; j<1; j++)
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[1], ((0x04+j)<<2)|i, m->apicid_mcp55, 0x10 + (2+i+j)%4);
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);