mb/*,soc/intel: drop the obsolete dt option speed_shift_enable

The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-10-15 00:36:29 +02:00
parent d5a45470c8
commit a64b4f4548
51 changed files with 2 additions and 116 deletions
--- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb
@@ -13,8 +13,6 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw2" = "GPP_E"

 	# FSP configuration
-	# Enable Speed Shift Technology/HWP support
-	register "speed_shift_enable" = "1"

 	register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"		# Type-C Port1
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"		# Type-C Port2
--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb
@@ -60,9 +60,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[4]" = "4"
 	register "PcieClkSrcClkReq[5]" = "5"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPP_G5"

--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb
@@ -57,9 +57,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[4]" = "4"
 	register "PcieClkSrcClkReq[5]" = "5"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# GPIO for SD card detect
 	register "sdcard_cd_gpio" = "GPP_G5"

--- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb
@@ -43,9 +43,6 @@ chip soc/intel/cannonlake
 	register "PcieClkSrcClkReq[4]" = "4"
 	register "PcieClkSrcClkReq[5]" = "5"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Disable S0ix
 	register "s0ix_enable" = "0"

--- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
@@ -152,9 +152,6 @@ chip soc/intel/icelake
 		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"

--- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
+++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
@@ -152,9 +152,6 @@ chip soc/intel/icelake
 		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"

--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -122,9 +122,6 @@ chip soc/intel/jasperlake
 		[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
 	}"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"

--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -16,9 +16,6 @@ chip soc/intel/skylake
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen1_dec" = "0x00fc0801"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"

--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -17,9 +17,6 @@ chip soc/intel/skylake
 	register "gen1_dec" = "0x00fc0801"
 	register "gen2_dec" = "0x000c0201"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable DPTF
 	register "dptf_enable" = "1"

--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -14,9 +14,6 @@ chip soc/intel/skylake
 	register "gpe0_dw1" = "GPP_D"
 	register "gpe0_dw2" = "GPP_E"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# FSP Configuration
 	register "DspEnable" = "1"
 	register "IoBufferOwnership" = "3"
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -115,9 +115,6 @@ chip soc/intel/tigerlake
 	register "TcssXhciEn" = "1"
 	register "TcssAuxOri" = "0"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable S0ix
 	register "s0ix_enable" = "1"

--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -119,9 +119,6 @@ chip soc/intel/tigerlake
 	register "TcssXhciEn" = "1"
 	register "TcssAuxOri" = "0"

-	# Enable "Intel Speed Shift Technology"
-	register "speed_shift_enable" = "1"
-
 	# Enable S0ix
 	register "s0ix_enable" = "1"