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Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1

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that don't seem to clarify anything.  Abuild tested.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2008-09-18 15:30:42 +00:00
parent 297b91c6cd
commit a67c354cbf
25 changed files with 1409 additions and 1699 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/mainboard/tyan/s2891/Config.lb
View File

@@ -53,25 +53,21 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end end
else
else
makerule ./auto.inc makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end end
end
end
else else
## ##
## Romcc output ## Romcc output
## ##
@@ -107,7 +103,6 @@ end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
@@ -195,7 +190,6 @@ else
end end
## ##
## Include the secondary Configuration files ## Include the secondary Configuration files
## ##
@@ -203,7 +197,6 @@ if CONFIG_CHIP_NAME
config chip.h config chip.h
end end
# sample config for tyan/s2891 # sample config for tyan/s2891
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
@@ -211,7 +204,6 @@ chip northbridge/amd/amdk8/root_complex
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on # northbridge device pci 18.0 on # northbridge
@@ -351,6 +343,7 @@ chip northbridge/amd/amdk8/root_complex
end #mc0 end #mc0
end # pci_domain end # pci_domain
# chip drivers/generic/debug # chip drivers/generic/debug
# device pnp 0.0 off end # chip name # device pnp 0.0 off end # chip name
# device pnp 0.1 off end # pci_regs_all # device pnp 0.1 off end # pci_regs_all

4
src/mainboard/tyan/s2891/Options.lb
View File

@@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END uses LB_CKS_RANGE_END
uses LB_CKS_LOC uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION uses COREBOOT_EXTRA_VERSION
@@ -75,7 +75,6 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK uses CONFIG_LB_MEM_TOPK
## ROM_SIZE is the size of boot ROM that this board will use. ## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes #512K bytes
default ROM_SIZE=524288 default ROM_SIZE=524288
@@ -83,7 +82,6 @@ default ROM_SIZE=524288
#1M bytes #1M bytes
#default ROM_SIZE=1048576 #default ROM_SIZE=1048576
## ##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## ##

5
src/mainboard/tyan/s2891/auto.c
View File

@@ -69,12 +69,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
@@ -123,8 +122,6 @@ static void main(unsigned long bist)
k8_init_and_stop_secondaries(); k8_init_and_stop_secondaries();
} }
// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

18
src/mainboard/tyan/s2891/cache_as_ram_auto.c
View File

@@ -8,7 +8,6 @@
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
@@ -21,17 +20,6 @@
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -54,7 +42,6 @@ static void post_code(uint8_t value) {
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset_setup(void) static void memreset_setup(void)
{ {
} }
@@ -92,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -167,7 +153,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
// post_code(0x23); // post_code(0x23);
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx)/* inputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
@@ -239,7 +225,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
// soft_reset(); // soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);

1
src/mainboard/tyan/s2891/failover.c
View File

@@ -91,7 +91,6 @@ static unsigned long main(unsigned long bist)
: "a" (bist) /* inputs */ : "a" (bist) /* inputs */
: /* clobbers */ : /* clobbers */
); );
fallback_image: fallback_image:
return bist; return bist;
} }

39
src/mainboard/tyan/s2891/get_bus_conf.c
View File

@@ -62,9 +62,9 @@ void get_bus_conf(void)
{ {
unsigned apicid_base; unsigned apicid_base;
unsigned sbdn;
device_t dev; device_t dev;
unsigned sbdn;
int i; int i;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done==1) return; //do it only once
@@ -91,51 +91,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
if (dev) { if (dev) {
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if 0
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_2++;
#else
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++; bus_ck804_4++;
#endif
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_1 = 2;
#if 0
bus_ck804_2 = 3;
#else
bus_ck804_4 = 3; bus_ck804_4 = 3;
#endif
} }
#if 0
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
if (dev) {
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_3++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
if (dev) {
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3+1;
}
#endif
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
if (dev) { if (dev) {
@@ -160,7 +124,6 @@ void get_bus_conf(void)
} }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) { if (dev) {

8
src/mainboard/tyan/s2891/irq_tables.c
View File

@@ -37,9 +37,9 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned char bus_coproc_0; extern unsigned char bus_coproc_0;
extern unsigned sbdn3; extern unsigned sbdn3;
@@ -54,10 +54,10 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct irq_info *pirq_info; struct irq_info *pirq_info;
unsigned slot_num; unsigned slot_num;
uint8_t *v; uint8_t *v;
unsigned sbdn;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
unsigned sbdn;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;

6
src/mainboard/tyan/s2891/mptable.c
View File

@@ -13,9 +13,9 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned apicid_ck804; extern unsigned apicid_ck804;
extern unsigned apicid_8131_1; extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2; extern unsigned apicid_8131_2;

9
src/mainboard/tyan/s2891/resourcemap.c
View File

@@ -6,7 +6,6 @@
static void setup_s2891_resource_map(void) static void setup_s2891_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
#if 1
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers /* DRAM Limit i Registers
* F1:0x44 i = 0 * F1:0x44 i = 0
@@ -80,8 +79,6 @@ static void setup_s2891_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
#endif
#if 1
/* Memory-Mapped I/O Limit i Registers /* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0 * F1:0x84 i = 0
@@ -158,8 +155,6 @@ static void setup_s2891_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
#endif
#if 1
/* PCI I/O Limit i Registers /* PCI I/O Limit i Registers
* F1:0xC4 i = 0 * F1:0xC4 i = 0
@@ -220,7 +215,7 @@ static void setup_s2891_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
#endif
/* Config Base and Limit i Registers /* Config Base and Limit i Registers
* F1:0xE0 i = 0 * F1:0xE0 i = 0
* F1:0xE4 i = 1 * F1:0xE4 i = 1
@@ -257,12 +252,10 @@ static void setup_s2891_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
#if 1
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
}; };

82
src/mainboard/tyan/s2892/Config.lb
View File

@@ -43,10 +43,10 @@ arch i386 end
driver mainboard.o driver mainboard.o
#dir /drivers/ati/ragexl #dir /drivers/ati/ragexl
#needed by irq_tables and mptable and acpi_tables #needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o object get_bus_conf.o
if HAVE_MP_TABLE object mptable.o end if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o #object reset.o
@@ -54,46 +54,42 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o
makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end end
else else
makerule ./auto.inc
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end end
end
else else
##
## ## Romcc output
## Romcc output ##
## makerule ./failover.E
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc" depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end end
makerule ./failover.inc makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc" depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end end
makerule ./auto.E makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc" depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
makerule ./auto.inc
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc" depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
end end
@@ -130,8 +126,8 @@ end
if USE_DCACHE_RAM if USE_DCACHE_RAM
else else
### Should this be in the northbridge code? ### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/cpu_reset.inc
end end
## ##
@@ -149,10 +145,10 @@ if USE_FALLBACK_IMAGE
end end
if USE_DCACHE_RAM if USE_DCACHE_RAM
## ##
## Setup Cache-As-Ram ## Setup Cache-As-Ram
## ##
mainboardinit cpu/amd/car/cache_as_ram.inc mainboardinit cpu/amd/car/cache_as_ram.inc
end end
### ###
@@ -161,12 +157,12 @@ end
### failover to another image. ### failover to another image.
### ###
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
else else
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc mainboardinit ./failover.inc
end end
end end
### ###
@@ -178,20 +174,20 @@ end
## ##
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
initobject auto.o initobject auto.o
else else
mainboardinit ./auto.inc mainboardinit ./auto.inc
end end
else else
# ROMCC # ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc mainboardinit cpu/x86/mmx/disable_mmx.inc
end end
@@ -202,7 +198,6 @@ if CONFIG_CHIP_NAME
config chip.h config chip.h
end end
# sample config for tyan/s2892 # sample config for tyan/s2892
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
@@ -210,7 +205,6 @@ chip northbridge/amd/amdk8/root_complex
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on # northbridge device pci 18.0 on # northbridge

9
src/mainboard/tyan/s2892/Options.lb
View File

@@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END uses LB_CKS_RANGE_END
uses LB_CKS_LOC uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION uses COREBOOT_EXTRA_VERSION
@@ -76,7 +76,6 @@ default ROM_SIZE=524288
#1M bytes #1M bytes
#default ROM_SIZE=1048576 #default ROM_SIZE=1048576
## ##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## ##
@@ -131,6 +130,9 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
##HT Unit ID offset, default is 1, the typical one ##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0 default HT_CHAIN_UNITID_BASE=0x0
@@ -143,9 +145,6 @@ default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1) ##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#BTEXT Console #BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1 #default CONFIG_CONSOLE_BTEXT=1

4
src/mainboard/tyan/s2892/auto.c
View File

@@ -73,7 +73,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
@@ -91,7 +91,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup.c" #include "southbridge/nvidia/ck804/ck804_early_setup.c"
static void main(unsigned long bist) static void main(unsigned long bist)
{ {
static const struct mem_controller cpu[] = { static const struct mem_controller cpu[] = {
@@ -125,7 +124,6 @@ static void main(unsigned long bist)
k8_init_and_stop_secondaries(); k8_init_and_stop_secondaries();
} }
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();

15
src/mainboard/tyan/s2892/cache_as_ram_auto.c
View File

@@ -13,18 +13,8 @@
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
@@ -96,7 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -118,6 +107,7 @@ static void sio_setup(void)
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
@@ -180,7 +170,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
static const uint16_t spd_addr [] = { static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0,

37
src/mainboard/tyan/s2892/get_bus_conf.c
View File

@@ -88,51 +88,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
if (dev) { if (dev) {
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if 0
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_2++;
#else
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++; bus_ck804_4++;
#endif
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_1 = 2;
#if 0
bus_ck804_2 = 3;
#else
bus_ck804_4 = 3; bus_ck804_4 = 3;
#endif
} }
#if 0
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
if (dev) {
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_3++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
if (dev) {
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3+1;
}
#endif
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
if (dev) { if (dev) {
@@ -157,7 +121,6 @@ void get_bus_conf(void)
} }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) { if (dev) {

6
src/mainboard/tyan/s2892/irq_tables.c
View File

@@ -37,9 +37,9 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned sbdn3; extern unsigned sbdn3;

7
src/mainboard/tyan/s2892/mptable.c
View File

@@ -13,15 +13,16 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned apicid_ck804; extern unsigned apicid_ck804;
extern unsigned apicid_8131_1; extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2; extern unsigned apicid_8131_2;
extern unsigned sbdn3; extern unsigned sbdn3;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {

9
src/mainboard/tyan/s2892/resourcemap.c
View File

@@ -6,7 +6,6 @@
static void setup_s2892_resource_map(void) static void setup_s2892_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
#if 1
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers /* DRAM Limit i Registers
* F1:0x44 i = 0 * F1:0x44 i = 0
@@ -80,8 +79,6 @@ static void setup_s2892_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
#endif
#if 1
/* Memory-Mapped I/O Limit i Registers /* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0 * F1:0x84 i = 0
@@ -158,8 +155,6 @@ static void setup_s2892_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
#endif
#if 1
/* PCI I/O Limit i Registers /* PCI I/O Limit i Registers
* F1:0xC4 i = 0 * F1:0xC4 i = 0
@@ -220,7 +215,7 @@ static void setup_s2892_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
#endif
/* Config Base and Limit i Registers /* Config Base and Limit i Registers
* F1:0xE0 i = 0 * F1:0xE0 i = 0
* F1:0xE4 i = 1 * F1:0xE4 i = 1
@@ -257,12 +252,10 @@ static void setup_s2892_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
#if 1
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
}; };

33
src/mainboard/tyan/s2895/Config.lb
View File

@@ -59,21 +59,22 @@ object get_bus_conf.o
if HAVE_MP_TABLE object mptable.o end if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o #object reset.o
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end end
else else
makerule ./auto.inc makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@" action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end end
end end
else else
## ##
@@ -128,7 +129,6 @@ if USE_DCACHE_RAM
end end
end end
## ##
## Build our reset vector (This is where coreboot is entered) ## Build our reset vector (This is where coreboot is entered)
## ##
@@ -243,7 +243,7 @@ chip northbridge/amd/amdk8/root_complex
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 chip southbridge/nvidia/ck804
device pci 0.0 on end # HT device pci 0.0 on end # HT
@@ -313,25 +313,6 @@ chip northbridge/amd/amdk8/root_complex
end end
end # SM end # SM
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
# chip drivers/generic/generic #PCIXA Slot1
# device i2c 50 on end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master CK804 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave CK804 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end device i2c 51 on end
end end
@@ -379,7 +360,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
end # mc0 end #mc0
chip northbridge/amd/amdk8 chip northbridge/amd/amdk8
device pci 19.0 on # northbridge device pci 19.0 on # northbridge
@@ -425,4 +406,4 @@ chip northbridge/amd/amdk8/root_complex
# device pnp 0.6 off end # cache size # device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc # device pnp 0.7 off end # tsc
# end # end
end #root_complex end # root_complex

2
src/mainboard/tyan/s2895/Options.lb
View File

@@ -166,7 +166,7 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#Opteron K8 1G HT Support #Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1 default K8_HT_FREQ_1G_SUPPORT=1
#VGA #VGA Console
default CONFIG_CONSOLE_VGA=1 default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1 default CONFIG_PCI_ROM_RUN=1

19
src/mainboard/tyan/s2895/auto.c
View File

@@ -71,13 +71,9 @@ static void sio_gpio_setup(void){
unsigned value; unsigned value;
// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c // lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
#if 1
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
#endif
} }
static inline void activate_spd_rom(const struct mem_controller *ctrl) static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -91,22 +87,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0
#define ENABLE_APIC_EXT_ID 1
#define APIC_ID_OFFSET 0x10
#define LIFT_BSP_APIC_ID 0
#else
#define ENABLE_APIC_EXT_ID 0
#endif
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
#define SECOND_CPU 1 #define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -116,7 +103,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define CK804_USE_NIC 1 #define CK804_USE_NIC 1
#define CK804_USE_ACI 1 #define CK804_USE_ACI 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode //set GPIO to input mode
#define CK804_MB_SETUP \ #define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
@@ -128,7 +114,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup.c" #include "southbridge/nvidia/ck804/ck804_early_setup.c"
static void main(unsigned long bist) static void main(unsigned long bist)
{ {
static const struct mem_controller cpu[] = { static const struct mem_controller cpu[] = {
@@ -162,8 +147,6 @@ static void main(unsigned long bist)
k8_init_and_stop_secondaries(); k8_init_and_stop_secondaries();
} }
// post_code(0x32);
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
@@ -186,11 +169,9 @@ static void main(unsigned long bist)
soft_reset(); soft_reset();
} }
enable_smbus(); enable_smbus();
memreset_setup(); memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
} }

28
src/mainboard/tyan/s2895/cache_as_ram_auto.c
View File

@@ -1,18 +1,16 @@
#define ASSEMBLY 1 #define ASSEMBLY 1
#define __ROMCC__ #define __ROMCC__
#define K8_ALLOCATE_IO_RANGE 1 #define K8_ALLOCATE_IO_RANGE 1
//#define K8_SCAN_PCI_BUS 1 //#define K8_SCAN_PCI_BUS 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
@@ -27,17 +25,6 @@
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x8000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -68,7 +55,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
@@ -81,7 +67,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{ {
} }
static void sio_gpio_setup(void){ static void sio_gpio_setup(void){
unsigned value; unsigned value;
@@ -103,7 +88,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
@@ -144,7 +128,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
{ {
@@ -152,7 +135,6 @@ static void sio_setup(void)
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
@@ -213,7 +195,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
// post_code(0x23); // post_code(0x23);
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
@@ -227,6 +209,7 @@ void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
; ;
} }
#endif #endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -234,15 +217,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if HAVE_FAILOVER_BOOT==1 #if HAVE_FAILOVER_BOOT==1
#if USE_FAILOVER_IMAGE==1 #if USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx); failover_process(bist, cpu_init_detectedx);
#else
real_main(bist, cpu_init_detectedx);
#endif #endif
#else #else
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx); failover_process(bist, cpu_init_detectedx);
#endif #endif
real_main(bist, cpu_init_detectedx);
#endif #endif
real_main(bist, cpu_init_detectedx);
} }
#if USE_FAILOVER_IMAGE==0 #if USE_FAILOVER_IMAGE==0

2
src/mainboard/tyan/s2895/failover.c
View File

@@ -50,14 +50,12 @@ static void sio_setup(void)
} }
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#include "cpu/amd/dualcore/dualcore_id.c" #include "cpu/amd/dualcore/dualcore_id.c"
#else #else
#include "cpu/amd/model_fxx/node_id.c" #include "cpu/amd/model_fxx/node_id.c"
#endif #endif
static unsigned long main(unsigned long bist) static unsigned long main(unsigned long bist)
{ {
/* Is this a cpu only reset? */ /* Is this a cpu only reset? */

104
src/mainboard/tyan/s2895/get_bus_conf.c
View File

@@ -9,7 +9,6 @@
#include <cpu/amd/amdk8_sysconf.h> #include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default //busnum is default
unsigned char bus_isa; unsigned char bus_isa;
@@ -56,6 +55,7 @@ unsigned hcdnx[] =
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
}; };
unsigned sbdn3; unsigned sbdn3;
unsigned sbdnb; unsigned sbdnb;
@@ -97,63 +97,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
if (dev) { if (dev) {
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if 0
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_2++;
#else
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_5++; bus_ck804_5++;
#endif
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_1 = 2;
#if 0
bus_ck804_2 = 3;
#else
bus_ck804_5 = 3; bus_ck804_5 = 3;
#endif
} }
#if 0
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
if (dev) {
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_3++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
if (dev) {
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
if (dev) {
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_5++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
bus_ck804_5 = bus_ck804_4+1;
}
#endif
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) { if (dev) {
@@ -194,56 +146,6 @@ void get_bus_conf(void)
if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed
bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff; bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
#if 0
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
if (dev) {
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_2++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
bus_ck804b_1 = bus_ck804b_0+1;
bus_ck804b_2 = bus_ck804b_0+2;
}
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0));
if (dev) {
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_3++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
bus_ck804b_2 = bus_ck804b_0+1;
bus_ck804b_3 = bus_ck804b_0+2;
}
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0));
if (dev) {
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_4++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
bus_ck804b_4 = bus_ck804b_3+1;
}
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0));
if (dev) {
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_5++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
bus_ck804b_5 = bus_ck804b_4+1;
}
#endif
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0)); dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
if (dev) { if (dev) {
@@ -253,10 +155,7 @@ void get_bus_conf(void)
} }
else { else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e); printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
#if 1
bus_ck804b_5 = bus_ck804b_4+1; bus_ck804b_5 = bus_ck804b_4+1;
#endif
bus_isa = bus_ck804b_5+1; bus_isa = bus_ck804b_5+1;
} }
} }
@@ -272,5 +171,4 @@ void get_bus_conf(void)
apicid_8131_1 = apicid_base+1; apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2; apicid_8131_2 = apicid_base+2;
apicid_ck804b = apicid_base+3; apicid_ck804b = apicid_base+3;
} }

2
src/mainboard/tyan/s2895/irq_tables.c
View File

@@ -50,6 +50,8 @@ extern unsigned char bus_ck804b_5;//f
extern unsigned sbdn3; extern unsigned sbdn3;
extern unsigned sbdnb; extern unsigned sbdnb;
extern void get_bus_conf(void);
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {

2
src/mainboard/tyan/s2895/mptable.c
View File

@@ -30,6 +30,8 @@ extern unsigned apicid_ck804b;
extern unsigned sbdn3; extern unsigned sbdn3;
extern unsigned sbdnb; extern unsigned sbdnb;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";