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Fix whitespace in tyan s289{1,2,5} files. Also removes some #if 0 and #if 1

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that don't seem to clarify anything.  Abuild tested.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson
2008-09-18 15:30:42 +00:00
parent 297b91c6cd
commit a67c354cbf
25 changed files with 1409 additions and 1699 deletions
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321
src/mainboard/tyan/s2891/Config.lb
View File

@@ -14,9 +14,9 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1 default CONFIG_ROM_PAYLOAD = 1
## ##
## Compute where this copy of coreboot will start in the boot rom ## Compute where this copy of coreboot will start in the boot rom
@@ -53,46 +53,42 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o
makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end end
else else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else
## ##
## Romcc output ## Romcc output
## ##
makerule ./failover.E makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc" depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end end
makerule ./failover.inc makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc" depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end end
makerule ./auto.E makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc" depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
makerule ./auto.inc makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc" depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
end end
@@ -101,13 +97,12 @@ end
## Build our 16 bit and 32 bit coreboot entry code ## Build our 16 bit and 32 bit coreboot entry code
## ##
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/16bit/entry16.lds
end end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
@@ -195,155 +190,152 @@ else
end end
## ##
## Include the secondary Configuration files ## Include the secondary Configuration files
## ##
if CONFIG_CHIP_NAME if CONFIG_CHIP_NAME
config chip.h config chip.h
end end
# sample config for tyan/s2891 # sample config for tyan/s2891
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_940 chip cpu/amd/socket_940
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on # northbridge device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 chip southbridge/nvidia/ck804
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 off # Floppy device pnp 2e.0 off # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off # Com2 device pnp 2e.3 off # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # CIR device pnp 2e.6 off # CIR
io 0x60 = 0x100 io 0x60 = 0x100
end end
device pnp 2e.7 off # GAME_MIDI_GIPO1 device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # GPIO2 device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3 device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b off # HW Monitor device pnp 2e.b off # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
# chip drivers/generic/generic #dimm 0-0-0 # chip drivers/generic/generic #dimm 0-0-0
# device i2c 50 on end # device i2c 50 on end
# end # end
# chip drivers/generic/generic #dimm 0-0-1 # chip drivers/generic/generic #dimm 0-0-1
# device i2c 51 on end # device i2c 51 on end
# end # end
# chip drivers/generic/generic #dimm 0-1-0 # chip drivers/generic/generic #dimm 0-1-0
# device i2c 52 on end # device i2c 52 on end
# end # end
# chip drivers/generic/generic #dimm 0-1-1 # chip drivers/generic/generic #dimm 0-1-1
# device i2c 53 on end # device i2c 53 on end
# end # end
# chip drivers/generic/generic #dimm 1-0-0 # chip drivers/generic/generic #dimm 1-0-0
# device i2c 54 on end # device i2c 54 on end
# end # end
# chip drivers/generic/generic #dimm 1-0-1 # chip drivers/generic/generic #dimm 1-0-1
# device i2c 55 on end # device i2c 55 on end
# end # end
# chip drivers/generic/generic #dimm 1-1-0 # chip drivers/generic/generic #dimm 1-1-0
# device i2c 56 on end # device i2c 56 on end
# end # end
# chip drivers/generic/generic #dimm 1-1-1 # chip drivers/generic/generic #dimm 1-1-1
# device i2c 57 on end # device i2c 57 on end
# end # end
end # SM end # SM
# device pci 1.1 on # SM 1 # device pci 1.1 on # SM 1
# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
# device i2c 2d on end # device i2c 2d on end
# end # end
# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
# device i2c 2e on end # device i2c 2e on end
# end # end
# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
# device i2c 2a on end # device i2c 2a on end
# end # end
# chip drivers/generic/generic # Winbond HWM 0x92 # chip drivers/generic/generic # Winbond HWM 0x92
# device i2c 49 on end # device i2c 49 on end
# end # end
# chip drivers/generic/generic # Winbond HWM 0x94 # chip drivers/generic/generic # Winbond HWM 0x94
# device i2c 4a on end # device i2c 4a on end
# end # end
# end #SM # end #SM
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 off end # ACI device pci 4.0 off end # ACI
device pci 4.1 off end # MCI device pci 4.1 off end # MCI
device pci 6.0 on end # IDE device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1 device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0 device pci 8.0 on end # SATA 0
device pci 9.0 on # PCI device pci 9.0 on # PCI
# chip drivers/ati/ragexl # chip drivers/ati/ragexl
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 7.0 on end device pci 7.0 on end
#register "rom_address" = "0xfff80000" #for 512K #register "rom_address" = "0xfff80000" #for 512K
register "rom_address" = "0xfff00000" #for 1M register "rom_address" = "0xfff00000" #for 1M
end end
end end
device pci a.0 off end # NIC device pci a.0 off end # NIC
device pci b.0 off end # PCI E 3 device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2 device pci c.0 off end # PCI E 2
device pci d.0 on end # PCI E 1 device pci d.0 on end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 1
device pci 18.0 on device pci 18.0 on
# devices on link 2, link 2 == LDT 2 # devices on link 2, link 2 == LDT 2
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 9.0 on end device pci 9.0 on end
device pci 9.1 on end device pci 9.1 on end
end end
end end
device pci 1.1 on end device pci 1.1 on end
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
@@ -351,15 +343,16 @@ chip northbridge/amd/amdk8/root_complex
end #mc0 end #mc0
end # pci_domain end # pci_domain
# chip drivers/generic/debug
# device pnp 0.0 off end # chip name # chip drivers/generic/debug
# device pnp 0.1 off end # pci_regs_all # device pnp 0.0 off end # chip name
# device pnp 0.2 off end # mem # device pnp 0.1 off end # pci_regs_all
# device pnp 0.3 off end # cpuid # device pnp 0.2 off end # mem
# device pnp 0.4 off end # smbus_regs_all # device pnp 0.3 off end # cpuid
# device pnp 0.5 off end # dual core msr # device pnp 0.4 off end # smbus_regs_all
# device pnp 0.6 off end # cache size # device pnp 0.5 off end # dual core msr
# device pnp 0.7 off end # tsc # device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc
# device pnp 0.8 on end # hard_reset # device pnp 0.8 on end # hard_reset
# end # end
end # root_complex end # root_complex

4
src/mainboard/tyan/s2891/Options.lb
View File

@@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END uses LB_CKS_RANGE_END
uses LB_CKS_LOC uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION uses COREBOOT_EXTRA_VERSION
@@ -75,7 +75,6 @@ uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
uses CONFIG_LB_MEM_TOPK uses CONFIG_LB_MEM_TOPK
## ROM_SIZE is the size of boot ROM that this board will use. ## ROM_SIZE is the size of boot ROM that this board will use.
#512K bytes #512K bytes
default ROM_SIZE=524288 default ROM_SIZE=524288
@@ -83,7 +82,6 @@ default ROM_SIZE=524288
#1M bytes #1M bytes
#default ROM_SIZE=1048576 #default ROM_SIZE=1048576
## ##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## ##

49
src/mainboard/tyan/s2891/auto.c
View File

@@ -33,20 +33,20 @@
static void hard_reset(void) static void hard_reset(void)
{ {
set_bios_reset(); set_bios_reset();
/* full reset */ /* full reset */
outb(0x0a, 0x0cf9); outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9); outb(0x0e, 0x0cf9);
} }
static void soft_reset(void) static void soft_reset(void)
{ {
set_bios_reset(); set_bios_reset();
#if 1 #if 1
/* link reset */ /* link reset */
outb(0x02, 0x0cf9); outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9); outb(0x06, 0x0cf9);
#endif #endif
} }
@@ -69,15 +69,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
#define SECOND_CPU 1 #define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -112,38 +111,36 @@ static void main(unsigned long bist)
#endif #endif
}; };
int needs_reset; int needs_reset;
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
struct node_core_id id; struct node_core_id id;
#else #else
unsigned nodeid; unsigned nodeid;
#endif #endif
if (bist == 0) { if (bist == 0) {
k8_init_and_stop_secondaries(); k8_init_and_stop_secondaries();
} }
// post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); console_init();
uart_init();
console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
setup_s2891_resource_map(); setup_s2891_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
enable_smbus(); enable_smbus();

180
src/mainboard/tyan/s2891/cache_as_ram_auto.c
View File

@@ -8,7 +8,6 @@
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
@@ -21,17 +20,6 @@
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -54,7 +42,6 @@ static void post_code(uint8_t value) {
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static void memreset_setup(void) static void memreset_setup(void)
{ {
} }
@@ -92,7 +79,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -101,28 +87,28 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
/* subject decoding*/ /* subject decoding*/
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20; byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
/* LPC Positive Decode 0 */ /* LPC Positive Decode 0 */
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
/* Serial 0, Serial 1 */ /* Serial 0, Serial 1 */
dword |= (1<<0) | (1<<1); dword |= (1<<0) | (1<<1);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
#if 1 #if 1
/* s2891 has onboard LPC port 80 */ /* s2891 has onboard LPC port 80 */
/*Hope I can enable port 80 here /*Hope I can enable port 80 here
It will decode port 80 to LPC, If you are using PCI post code you can not do this */ It will decode port 80 to LPC, If you are using PCI post code you can not do this */
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16); dword |= (1<<16);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
#endif #endif
@@ -130,48 +116,48 @@ static void sio_setup(void)
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */ /* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) { if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) { if (last_boot_normal_x) {
goto normal_image; goto normal_image;
} else { } else {
goto fallback_image; goto fallback_image;
} }
} }
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
/* Setup the ck804 */ /* Setup the ck804 */
ck804_enable_rom(); ck804_enable_rom();
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
// post_code(0x22); // post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) { if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image; goto normal_image;
} }
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
else if (do_normal_boot()) { else if (do_normal_boot()) {
goto normal_image; goto normal_image;
} }
else { else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
// post_code(0x23); // post_code(0x23);
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist) , "b" (cpu_init_detectedx)/* inputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
// post_code(0x25); // post_code(0x25);
; ;
} }
#endif #endif
@@ -182,71 +168,71 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx); failover_process(bist, cpu_init_detectedx);
#endif #endif
real_main(bist, cpu_init_detectedx); real_main(bist, cpu_init_detectedx);
} }
void real_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
static const uint16_t spd_addr [] = { static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1 #if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif #endif
}; };
int needs_reset; int needs_reset;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
struct mem_controller ctrl[8]; struct mem_controller ctrl[8];
unsigned nodes; unsigned nodes;
if (bist == 0) { if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx);
} }
// post_code(0x32); // post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
setup_s2891_resource_map(); setup_s2891_resource_map();
#if 0 #if 0
dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif #endif
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
// soft_reset(); // soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(); nodes = get_nodes();
//It's the time to set ctrl now; //It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr); fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus(); enable_smbus();
#if 0 #if 0
@@ -260,7 +246,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(nodes, ctrl); sdram_initialize(nodes, ctrl);
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
#if 0 #if 0

1
src/mainboard/tyan/s2891/failover.c
View File

@@ -91,7 +91,6 @@ static unsigned long main(unsigned long bist)
: "a" (bist) /* inputs */ : "a" (bist) /* inputs */
: /* clobbers */ : /* clobbers */
); );
fallback_image: fallback_image:
return bist; return bist;
} }

39
src/mainboard/tyan/s2891/get_bus_conf.c
View File

@@ -62,9 +62,9 @@ void get_bus_conf(void)
{ {
unsigned apicid_base; unsigned apicid_base;
unsigned sbdn;
device_t dev; device_t dev;
unsigned sbdn;
int i; int i;
if(get_bus_conf_done==1) return; //do it only once if(get_bus_conf_done==1) return; //do it only once
@@ -91,51 +91,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
if (dev) { if (dev) {
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if 0
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_2++;
#else
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++; bus_ck804_4++;
#endif
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_1 = 2;
#if 0
bus_ck804_2 = 3;
#else
bus_ck804_4 = 3; bus_ck804_4 = 3;
#endif
} }
#if 0
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
if (dev) {
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_3++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
if (dev) {
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3+1;
}
#endif
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
if (dev) { if (dev) {
@@ -160,7 +124,6 @@ void get_bus_conf(void)
} }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) { if (dev) {

114
src/mainboard/tyan/s2891/irq_tables.c
View File

@@ -16,18 +16,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern unsigned char bus_isa; extern unsigned char bus_isa;
@@ -37,13 +37,13 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned char bus_coproc_0; extern unsigned char bus_coproc_0;
extern unsigned sbdn3; extern unsigned sbdn3;
extern unsigned coprocdn; extern unsigned coprocdn;
extern void get_bus_conf(void); extern void get_bus_conf(void);
@@ -54,20 +54,20 @@ unsigned long write_pirq_routing_table(unsigned long addr)
struct irq_info *pirq_info; struct irq_info *pirq_info;
unsigned slot_num; unsigned slot_num;
uint8_t *v; uint8_t *v;
uint8_t sum=0;
int i;
unsigned sbdn; unsigned sbdn;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c uint8_t sum=0;
int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@@ -93,74 +93,74 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//pcix bridge //pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//co processor //co processor
if(sysconf.pci1234[2] & 1) { if(sysconf.pci1234[2] & 1) {
write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_coproc_0, (coprocdn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
} }
#if 0 #if 0
//smbus //smbus
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//usb //usb
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//audio //audio
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//sata //sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//sata //sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//nic //nic
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot1 PCIE x16 //Slot1 PCIE x16
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//firewire //firewire
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot2 pci //Slot2 pci
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot3 PCIE x16 //Slot3 PCIE x16
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot4 PCIX //Slot4 PCIX
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot5 PCIX //Slot5 PCIX
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot6 PCIX //Slot6 PCIX
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
#endif #endif
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk_info("done.\n"); printk_info("done.\n");

130
src/mainboard/tyan/s2891/mptable.c
View File

@@ -13,9 +13,9 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned apicid_ck804; extern unsigned apicid_ck804;
extern unsigned apicid_8131_1; extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2; extern unsigned apicid_8131_2;
@@ -26,52 +26,52 @@ extern void get_bus_conf(void);
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN "; static const char oem[8] = "TYAN ";
static const char productid[12] = "S2891 "; static const char productid[12] = "S2891 ";
struct mp_config_table *mc; struct mp_config_table *mc;
unsigned sbdn; unsigned sbdn;
unsigned char bus_num; unsigned char bus_num;
int i; int i;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig)); memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04; mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */ mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid)); memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0; mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0; mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR; mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0; mc->mpe_length = 0;
mc->mpe_checksum = 0; mc->mpe_checksum = 0;
mc->reserved = 0; mc->reserved = 0;
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) { for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI "); smp_write_bus(mc, bus_num, "PCI ");
} }
smp_write_bus(mc, bus_isa, "ISA "); smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
@@ -80,30 +80,30 @@ void *smp_write_config_table(void *v)
/* Initialize interrupt mapping*/ /* Initialize interrupt mapping*/
dword = 0x0120d218; dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00; dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d; dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
} }
} }
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
} }
} }
} }
@@ -122,53 +122,53 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
// Onboard ck804 smbus // Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
// 10 // 10
// Onboard ck804 USB 1.1 // Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2 // Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0 // Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1 // Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16 //Slot PCIE x16
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
} }
//Slot PCIE x4 //Slot PCIE x4
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
} }
//Onboard ati //Onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (7<<2)|0, apicid_ck804, 0x13); // 19
//Channel B of 8131 //Channel B of 8131
//Onboard Broadcom NIC //Onboard Broadcom NIC
for(i=0;i<2;i++) { for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
} }
//Channel A of 8131 //Channel A of 8131
//Slot 4 PCIX 133/100/66 //Slot 4 PCIX 133/100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|i, apicid_8131_1, (0+i)%4); //24
} }
//Slot 3 PCIX 133/100/66 SoDIMM PCI //Slot 3 PCIX 133/100/66 SoDIMM PCI
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|i, apicid_8131_1, (2+i)%4); //26
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);

9
src/mainboard/tyan/s2891/resourcemap.c
View File

@@ -6,7 +6,6 @@
static void setup_s2891_resource_map(void) static void setup_s2891_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
#if 1
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers /* DRAM Limit i Registers
* F1:0x44 i = 0 * F1:0x44 i = 0
@@ -80,8 +79,6 @@ static void setup_s2891_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
#endif
#if 1
/* Memory-Mapped I/O Limit i Registers /* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0 * F1:0x84 i = 0
@@ -158,8 +155,6 @@ static void setup_s2891_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
#endif
#if 1
/* PCI I/O Limit i Registers /* PCI I/O Limit i Registers
* F1:0xC4 i = 0 * F1:0xC4 i = 0
@@ -220,7 +215,7 @@ static void setup_s2891_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
#endif
/* Config Base and Limit i Registers /* Config Base and Limit i Registers
* F1:0xE0 i = 0 * F1:0xE0 i = 0
* F1:0xE4 i = 1 * F1:0xE4 i = 1
@@ -257,12 +252,10 @@ static void setup_s2891_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
#if 1
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
}; };

380
src/mainboard/tyan/s2892/Config.lb
View File

@@ -14,9 +14,9 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
default CONFIG_ROM_PAYLOAD = 1 default CONFIG_ROM_PAYLOAD = 1
## ##
## Compute where this copy of coreboot will start in the boot rom ## Compute where this copy of coreboot will start in the boot rom
@@ -43,10 +43,10 @@ arch i386 end
driver mainboard.o driver mainboard.o
#dir /drivers/ati/ragexl #dir /drivers/ati/ragexl
#needed by irq_tables and mptable and acpi_tables #needed by irq_tables and mptable and acpi_tables
object get_bus_conf.o object get_bus_conf.o
if HAVE_MP_TABLE object mptable.o end if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o #object reset.o
@@ -54,46 +54,42 @@ if HAVE_PIRQ_TABLE object irq_tables.o end
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o
makerule ./auto.o depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end end
else else
##
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.inc makerule ./failover.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/failover.c ../romcc"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@" action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@" end
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end makerule ./auto.E
else depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
## end
## Romcc output
##
makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
end end
@@ -101,8 +97,8 @@ end
## Build our 16 bit and 32 bit coreboot entry code ## Build our 16 bit and 32 bit coreboot entry code
## ##
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/16bit/entry16.lds
end end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
@@ -113,7 +109,7 @@ if USE_DCACHE_RAM
end end
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds ldscript /cpu/amd/car/cache_as_ram.lds
end end
end end
@@ -130,8 +126,8 @@ end
if USE_DCACHE_RAM if USE_DCACHE_RAM
else else
### Should this be in the northbridge code? ### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc mainboardinit arch/i386/lib/cpu_reset.inc
end end
## ##
@@ -149,10 +145,10 @@ if USE_FALLBACK_IMAGE
end end
if USE_DCACHE_RAM if USE_DCACHE_RAM
## ##
## Setup Cache-As-Ram ## Setup Cache-As-Ram
## ##
mainboardinit cpu/amd/car/cache_as_ram.inc mainboardinit cpu/amd/car/cache_as_ram.inc
end end
### ###
@@ -161,12 +157,12 @@ end
### failover to another image. ### failover to another image.
### ###
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
else else
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
mainboardinit ./failover.inc mainboardinit ./failover.inc
end end
end end
### ###
@@ -178,20 +174,20 @@ end
## ##
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
initobject auto.o initobject auto.o
else else
mainboardinit ./auto.inc mainboardinit ./auto.inc
end end
else else
# ROMCC # ROMCC
mainboardinit cpu/x86/fpu/enable_fpu.inc mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc mainboardinit cpu/x86/sse/enable_sse.inc
mainboardinit ./auto.inc mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc mainboardinit cpu/x86/mmx/disable_mmx.inc
end end
@@ -199,152 +195,150 @@ end
## Include the secondary Configuration files ## Include the secondary Configuration files
## ##
if CONFIG_CHIP_NAME if CONFIG_CHIP_NAME
config chip.h config chip.h
end end
# sample config for tyan/s2892 # sample config for tyan/s2892
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_940 chip cpu/amd/socket_940
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on # northbridge device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 chip southbridge/nvidia/ck804
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/winbond/w83627hf chip superio/winbond/w83627hf
device pnp 2e.0 on # Floppy device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end end
device pnp 2e.1 off # Parallel Port device pnp 2e.1 off # Parallel Port
io 0x60 = 0x378 io 0x60 = 0x378
irq 0x70 = 7 irq 0x70 = 7
end end
device pnp 2e.2 on # Com1 device pnp 2e.2 on # Com1
io 0x60 = 0x3f8 io 0x60 = 0x3f8
irq 0x70 = 4 irq 0x70 = 4
end end
device pnp 2e.3 off # Com2 device pnp 2e.3 off # Com2
io 0x60 = 0x2f8 io 0x60 = 0x2f8
irq 0x70 = 3 irq 0x70 = 3
end end
device pnp 2e.5 on # Keyboard device pnp 2e.5 on # Keyboard
io 0x60 = 0x60 io 0x60 = 0x60
io 0x62 = 0x64 io 0x62 = 0x64
irq 0x70 = 1 irq 0x70 = 1
irq 0x72 = 12 irq 0x72 = 12
end end
device pnp 2e.6 off # CIR device pnp 2e.6 off # CIR
io 0x60 = 0x100 io 0x60 = 0x100
end end
device pnp 2e.7 off # GAME_MIDI_GIPO1 device pnp 2e.7 off # GAME_MIDI_GIPO1
io 0x60 = 0x220 io 0x60 = 0x220
io 0x62 = 0x300 io 0x62 = 0x300
irq 0x70 = 9 irq 0x70 = 9
end end
device pnp 2e.8 off end # GPIO2 device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3 device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI device pnp 2e.a off end # ACPI
device pnp 2e.b on # HW Monitor device pnp 2e.b on # HW Monitor
io 0x60 = 0x290 io 0x60 = 0x290
irq 0x70 = 5 irq 0x70 = 5
end end
end end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm 0-1-0 chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm 0-1-1 chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic #dimm 1-0-0 chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic #dimm 1-0-1 chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic #dimm 1-1-0 chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic #dimm 1-1-1 chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end # SM end # SM
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
device i2c 2d on end device i2c 2d on end
end end
chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
device i2c 2e on end device i2c 2e on end
end end
chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
device i2c 2a on end device i2c 2a on end
end end
chip drivers/generic/generic # Winbond HWM 0x92 chip drivers/generic/generic # Winbond HWM 0x92
device i2c 49 on end device i2c 49 on end
end end
chip drivers/generic/generic # Winbond HWM 0x94 chip drivers/generic/generic # Winbond HWM 0x94
device i2c 4a on end device i2c 4a on end
end end
end #SM end #SM
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 off end # ACI device pci 4.0 off end # ACI
device pci 4.1 off end # MCI device pci 4.1 off end # MCI
device pci 6.0 on end # IDE device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1 device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0 device pci 8.0 on end # SATA 0
device pci 9.0 on # PCI device pci 9.0 on # PCI
# chip drivers/ati/ragexl # chip drivers/ati/ragexl
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 6.0 on end device pci 6.0 on end
register "rom_address" = "0xfff80000" register "rom_address" = "0xfff80000"
end end
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 8.0 on end device pci 8.0 on end
end end
end end
device pci a.0 off end # NIC device pci a.0 off end # NIC
device pci b.0 off end # PCI E 3 device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2 device pci c.0 off end # PCI E 2
device pci d.0 on end # PCI E 1 device pci d.0 on end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 1
device pci 18.0 on device pci 18.0 on
# devices on link 2, link 2 == LDT 2 # devices on link 2, link 2 == LDT 2
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 9.0 on end # broadcom 5704 device pci 9.0 on end # broadcom 5704
device pci 9.1 on end device pci 9.1 on end
end end
end end
device pci 1.1 on end device pci 1.1 on end
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
@@ -353,12 +347,12 @@ chip northbridge/amd/amdk8/root_complex
end # pci_domain end # pci_domain
# chip drivers/generic/debug # chip drivers/generic/debug
# device pnp 0.0 off end # device pnp 0.0 off end
# device pnp 0.1 off end # device pnp 0.1 off end
# device pnp 0.2 off end # device pnp 0.2 off end
# device pnp 0.3 off end # device pnp 0.3 off end
# device pnp 0.4 off end # device pnp 0.4 off end
# device pnp 0.5 on end # device pnp 0.5 on end
# end # end
end # root_complex end # root_complex

9
src/mainboard/tyan/s2892/Options.lb
View File

@@ -30,9 +30,9 @@ uses USE_OPTION_TABLE
uses LB_CKS_RANGE_START uses LB_CKS_RANGE_START
uses LB_CKS_RANGE_END uses LB_CKS_RANGE_END
uses LB_CKS_LOC uses LB_CKS_LOC
uses MAINBOARD
uses MAINBOARD_PART_NUMBER uses MAINBOARD_PART_NUMBER
uses MAINBOARD_VENDOR uses MAINBOARD_VENDOR
uses MAINBOARD
uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION uses COREBOOT_EXTRA_VERSION
@@ -76,7 +76,6 @@ default ROM_SIZE=524288
#1M bytes #1M bytes
#default ROM_SIZE=1048576 #default ROM_SIZE=1048576
## ##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
## ##
@@ -131,6 +130,9 @@ default CONFIG_MAX_CPUS=4
default CONFIG_MAX_PHYSICAL_CPUS=2 default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1 default CONFIG_LOGICAL_CPUS=1
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
##HT Unit ID offset, default is 1, the typical one ##HT Unit ID offset, default is 1, the typical one
default HT_CHAIN_UNITID_BASE=0x0 default HT_CHAIN_UNITID_BASE=0x0
@@ -143,9 +145,6 @@ default SB_HT_CHAIN_ON_BUS0=2
##only offset for SB chain?, default is yes(1) ##only offset for SB chain?, default is yes(1)
default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#1G memory hole
default HW_MEM_HOLE_SIZEK=0x100000
#BTEXT Console #BTEXT Console
#default CONFIG_CONSOLE_BTEXT=1 #default CONFIG_CONSOLE_BTEXT=1

48
src/mainboard/tyan/s2892/auto.c
View File

@@ -33,20 +33,20 @@
static void hard_reset(void) static void hard_reset(void)
{ {
set_bios_reset(); set_bios_reset();
/* full reset */ /* full reset */
outb(0x0a, 0x0cf9); outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9); outb(0x0e, 0x0cf9);
} }
static void soft_reset(void) static void soft_reset(void)
{ {
set_bios_reset(); set_bios_reset();
#if 1 #if 1
/* link reset */ /* link reset */
outb(0x02, 0x0cf9); outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9); outb(0x06, 0x0cf9);
#endif #endif
} }
@@ -73,10 +73,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#define FIRST_CPU 1 #define FIRST_CPU 1
#define SECOND_CPU 1 #define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -84,14 +84,13 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode //set GPIO to input mode
#define CK804_MB_SETUP \ #define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup.c" #include "southbridge/nvidia/ck804/ck804_early_setup.c"
static void main(unsigned long bist) static void main(unsigned long bist)
{ {
static const struct mem_controller cpu[] = { static const struct mem_controller cpu[] = {
@@ -119,21 +118,20 @@ static void main(unsigned long bist)
#endif #endif
}; };
int needs_reset; int needs_reset;
if (bist == 0) {
k8_init_and_stop_secondaries();
}
if (bist == 0) {
k8_init_and_stop_secondaries();
}
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
// report_bist_failure(bist); // report_bist_failure(bist);
setup_s2892_resource_map(); setup_s2892_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
@@ -141,10 +139,10 @@ static void main(unsigned long bist)
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
enable_smbus(); enable_smbus();

197
src/mainboard/tyan/s2892/cache_as_ram_auto.c
View File

@@ -13,18 +13,8 @@
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x80000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h" #include "northbridge/amd/amdk8/raminit.h"
@@ -83,10 +73,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode //set GPIO to input mode
#define CK804_MB_SETUP \ #define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup.c" #include "southbridge/nvidia/ck804/ck804_early_setup.c"
@@ -96,7 +86,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/init_cpus.c"
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
@@ -105,63 +94,64 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20; byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
dword |= (1<<0); dword |= (1<<0);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */ /* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) { if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) { if (last_boot_normal_x) {
goto normal_image; goto normal_image;
} else { } else {
goto fallback_image; goto fallback_image;
} }
} }
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
/* Setup the ck804 */ /* Setup the ck804 */
ck804_enable_rom(); ck804_enable_rom();
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
// post_code(0x22); // post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) { if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image; goto normal_image;
} }
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
else if (do_normal_boot()) { else if (do_normal_boot()) {
goto normal_image; goto normal_image;
} }
else { else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
// post_code(0x23); // post_code(0x23);
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b"(cpu_init_detectedx) /* inputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
// post_code(0x25); // post_code(0x25);
; ;
} }
#endif #endif
@@ -172,91 +162,90 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx); failover_process(bist, cpu_init_detectedx);
#endif #endif
real_main(bist, cpu_init_detectedx); real_main(bist, cpu_init_detectedx);
} }
void real_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
static const uint16_t spd_addr [] = {
static const uint16_t spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1 #if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif #endif
}; };
int needs_reset; int needs_reset;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
struct mem_controller ctrl[8]; struct mem_controller ctrl[8];
unsigned nodes; unsigned nodes;
if (bist == 0) { if (bist == 0) {
init_cpus(cpu_init_detectedx); init_cpus(cpu_init_detectedx);
} }
// post_code(0x32); // post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
setup_s2892_resource_map(); setup_s2892_resource_map();
#if 0 #if 0
dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif #endif
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(); nodes = get_nodes();
//It's the time to set ctrl now; //It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr); fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus(); enable_smbus();
#if 0 #if 0
dump_spd_registers(&cpu[0]); dump_spd_registers(&cpu[0]);
#endif #endif
#if 0 #if 0
dump_smbus_registers(); dump_smbus_registers();
#endif #endif
memreset_setup(); memreset_setup();
sdram_initialize(nodes, ctrl); sdram_initialize(nodes, ctrl);
#if 0 #if 0
print_pci_devices(); print_pci_devices();
#endif #endif
#if 0 #if 0
dump_pci_devices(); dump_pci_devices();
#endif #endif
post_cache_as_ram(); post_cache_as_ram();
} }

37
src/mainboard/tyan/s2892/get_bus_conf.c
View File

@@ -88,51 +88,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
if (dev) { if (dev) {
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if 0
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_2++;
#else
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++; bus_ck804_4++;
#endif
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_1 = 2;
#if 0
bus_ck804_2 = 3;
#else
bus_ck804_4 = 3; bus_ck804_4 = 3;
#endif
} }
#if 0
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
if (dev) {
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_3++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
if (dev) {
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3+1;
}
#endif
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
if (dev) { if (dev) {
@@ -157,7 +121,6 @@ void get_bus_conf(void)
} }
bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff; bus_8131_0 = (sysconf.pci1234[1] >> 16) & 0xff;
/* 8131-1 */ /* 8131-1 */
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) { if (dev) {

104
src/mainboard/tyan/s2892/irq_tables.c
View File

@@ -16,18 +16,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern unsigned char bus_isa; extern unsigned char bus_isa;
@@ -37,9 +37,9 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned sbdn3; extern unsigned sbdn3;
@@ -54,18 +54,18 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t *v; uint8_t *v;
unsigned sbdn; unsigned sbdn;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@@ -91,69 +91,69 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//pcix bridge //pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
#if 0 #if 0
//smbus //smbus
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//usb //usb
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//audio //audio
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//sata //sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//sata //sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//nic //nic
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot1 PCIE x16 //Slot1 PCIE x16
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//firewire //firewire
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot2 pci //Slot2 pci
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot3 PCIE x16 //Slot3 PCIE x16
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot4 PCIX //Slot4 PCIX
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot5 PCIX //Slot5 PCIX
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot6 PCIX //Slot6 PCIX
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
#endif #endif
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk_info("done.\n"); printk_info("done.\n");

151
src/mainboard/tyan/s2892/mptable.c
View File

@@ -13,64 +13,65 @@ extern unsigned char bus_ck804_2; //3
extern unsigned char bus_ck804_3; //4 extern unsigned char bus_ck804_3; //4
extern unsigned char bus_ck804_4; //5 extern unsigned char bus_ck804_4; //5
extern unsigned char bus_ck804_5; //6 extern unsigned char bus_ck804_5; //6
extern unsigned char bus_8131_0;//7 extern unsigned char bus_8131_0; //7
extern unsigned char bus_8131_1;//8 extern unsigned char bus_8131_1; //8
extern unsigned char bus_8131_2;//9 extern unsigned char bus_8131_2; //9
extern unsigned apicid_ck804; extern unsigned apicid_ck804;
extern unsigned apicid_8131_1; extern unsigned apicid_8131_1;
extern unsigned apicid_8131_2; extern unsigned apicid_8131_2;
extern unsigned sbdn3; extern unsigned sbdn3;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN "; static const char oem[8] = "TYAN ";
static const char productid[12] = "S2892 "; static const char productid[12] = "S2892 ";
struct mp_config_table *mc; struct mp_config_table *mc;
unsigned sbdn; unsigned sbdn;
unsigned char bus_num; unsigned char bus_num;
int i; int i;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig)); memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04; mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */ mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid)); memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0; mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0; mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR; mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0; mc->mpe_length = 0;
mc->mpe_checksum = 0; mc->mpe_checksum = 0;
mc->reserved = 0; mc->reserved = 0;
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) { for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI "); smp_write_bus(mc, bus_num, "PCI ");
} }
smp_write_bus(mc, bus_isa, "ISA "); smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
@@ -79,30 +80,30 @@ void *smp_write_config_table(void *v)
/* Initialize interrupt mapping*/ /* Initialize interrupt mapping*/
dword = 0x0120d218; dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00; dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0x0000007d; dword = 0x0000007d;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
} }
} }
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
} }
} }
} }
@@ -121,74 +122,74 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
// Onboard ck804 smbus // Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
// 10 // 10
// Onboard ck804 USB 1.1 // Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2 // Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0 // Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1 // Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
//Slot PCIE x16 //Slot PCIE x16
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
} }
//Slot PCIE x4 //Slot PCIE x4
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
} }
//Slot 2 PCI 32 //Slot 2 PCI 32
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (4<<2)|i, apicid_ck804, 0x10+(0+i)%4); //16
} }
//Onboard ati //Onboard ati
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18
//Onboard intel 10/100 //Onboard intel 10/100
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18
//Channel B of 8131 //Channel B of 8131
//Onboard Broadcom NIC //Onboard Broadcom NIC
for(i=0;i<2;i++) { for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
} }
//SO DIMM PCI-X //SO DIMM PCI-X
for(i=0;i<2;i++) { for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28
} }
//Slot 4 PCIX 133/100/66 //Slot 4 PCIX 133/100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30
} }
//Channel A of 8131 //Channel A of 8131
//Slot 5 PCIX 133/100/66 //Slot 5 PCIX 133/100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27
} }
//Slot 6 PCIX 133/100/66 //Slot 6 PCIX 133/100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);

9
src/mainboard/tyan/s2892/resourcemap.c
View File

@@ -6,7 +6,6 @@
static void setup_s2892_resource_map(void) static void setup_s2892_resource_map(void)
{ {
static const unsigned int register_values[] = { static const unsigned int register_values[] = {
#if 1
/* Careful set limit registers before base registers which contain the enables */ /* Careful set limit registers before base registers which contain the enables */
/* DRAM Limit i Registers /* DRAM Limit i Registers
* F1:0x44 i = 0 * F1:0x44 i = 0
@@ -80,8 +79,6 @@ static void setup_s2892_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
#endif
#if 1
/* Memory-Mapped I/O Limit i Registers /* Memory-Mapped I/O Limit i Registers
* F1:0x84 i = 0 * F1:0x84 i = 0
@@ -158,8 +155,6 @@ static void setup_s2892_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
#endif
#if 1
/* PCI I/O Limit i Registers /* PCI I/O Limit i Registers
* F1:0xC4 i = 0 * F1:0xC4 i = 0
@@ -220,7 +215,7 @@ static void setup_s2892_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
#endif
/* Config Base and Limit i Registers /* Config Base and Limit i Registers
* F1:0xE0 i = 0 * F1:0xE0 i = 0
* F1:0xE4 i = 1 * F1:0xE4 i = 1
@@ -257,12 +252,10 @@ static void setup_s2892_resource_map(void)
* [31:24] Bus Number Limit i * [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i * This field defines the highest bus number in configuration region i
*/ */
#if 1
// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */ // PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
// PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */ // PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
#endif
}; };

407
src/mainboard/tyan/s2895/Config.lb
View File

@@ -19,7 +19,7 @@ end
## Compute the start location and size size of ## Compute the start location and size size of
## The coreboot bootloader. ## The coreboot bootloader.
## ##
default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
## ##
@@ -39,11 +39,11 @@ default XIP_ROM_SIZE=65536
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
else else
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE) default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
else else
default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE) default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
end end
end end
arch i386 end arch i386 end
@@ -59,44 +59,45 @@ object get_bus_conf.o
if HAVE_MP_TABLE object mptable.o end if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end if HAVE_PIRQ_TABLE object irq_tables.o end
#object reset.o #object reset.o
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
makerule ./auto.o makerule ./auto.o
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h" depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o" action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end end
else
makerule ./auto.inc
depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
action "perl -e 's/.rodata/.rom.data/g' -pi $@"
action "perl -e 's/.text/.section .rom.text/g' -pi $@"
end
end
else else
## ##
## Romcc output ## Romcc output
## ##
makerule ./failover.E makerule ./failover.E
depends "$(MAINBOARD)/failover.c ../romcc" depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end end
makerule ./failover.inc makerule ./failover.inc
depends "$(MAINBOARD)/failover.c ../romcc" depends "$(MAINBOARD)/failover.c ../romcc"
action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
end end
makerule ./auto.E makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ../romcc" depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
makerule ./auto.inc makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ../romcc" depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end end
end end
@@ -105,30 +106,29 @@ end
## Build our 16 bit and 32 bit coreboot entry code ## Build our 16 bit and 32 bit coreboot entry code
## ##
if HAVE_FAILOVER_BOOT if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/16bit/entry16.lds
end end
else else
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/16bit/entry16.lds
end end
end end
mainboardinit cpu/x86/32bit/entry32.inc mainboardinit cpu/x86/32bit/entry32.inc
if USE_DCACHE_RAM if USE_DCACHE_RAM
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds ldscript /cpu/x86/32bit/entry32.lds
end end
if CONFIG_USE_INIT if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds ldscript /cpu/amd/car/cache_as_ram.lds
end end
end end
## ##
## Build our reset vector (This is where coreboot is entered) ## Build our reset vector (This is where coreboot is entered)
## ##
@@ -166,15 +166,15 @@ ldscript /southbridge/nvidia/ck804/id.lds
## ROMSTRAP table for CK804 ## ROMSTRAP table for CK804
## ##
if HAVE_FAILOVER_BOOT if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds ldscript /southbridge/nvidia/ck804/romstrap.lds
end end
else else
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
mainboardinit southbridge/nvidia/ck804/romstrap.inc mainboardinit southbridge/nvidia/ck804/romstrap.inc
ldscript /southbridge/nvidia/ck804/romstrap.lds ldscript /southbridge/nvidia/ck804/romstrap.lds
end end
end end
if USE_DCACHE_RAM if USE_DCACHE_RAM
@@ -190,19 +190,19 @@ end
### failover to another image. ### failover to another image.
### ###
if HAVE_FAILOVER_BOOT if HAVE_FAILOVER_BOOT
if USE_FAILOVER_IMAGE if USE_FAILOVER_IMAGE
if USE_DCACHE_RAM if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover_failover.lds ldscript /arch/i386/lib/failover_failover.lds
end
end end
end
else else
if USE_FALLBACK_IMAGE if USE_FALLBACK_IMAGE
if USE_DCACHE_RAM if USE_DCACHE_RAM
ldscript /arch/i386/lib/failover.lds ldscript /arch/i386/lib/failover.lds
else else
mainboardinit ./failover.inc mainboardinit ./failover.inc
end
end end
end
end end
## ##
@@ -236,124 +236,105 @@ end
# sample config for tyan/s2895 # sample config for tyan/s2895
chip northbridge/amd/amdk8/root_complex chip northbridge/amd/amdk8/root_complex
device apic_cluster 0 on device apic_cluster 0 on
chip cpu/amd/socket_940 chip cpu/amd/socket_940
device apic 0 on end device apic 0 on end
end end
end end
device pci_domain 0 on device pci_domain 0 on
chip northbridge/amd/amdk8 #mc0 chip northbridge/amd/amdk8 #mc0
device pci 18.0 on device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 chip southbridge/nvidia/ck804
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on # LPC device pci 1.0 on # LPC
chip superio/smsc/lpc47b397 chip superio/smsc/lpc47b397
device pnp 2e.0 on # Floppy device pnp 2e.0 on # Floppy
io 0x60 = 0x3f0 io 0x60 = 0x3f0
irq 0x70 = 6 irq 0x70 = 6
drq 0x74 = 2 drq 0x74 = 2
end
device pnp 2e.3 off # Parallel Port
io 0x60 = 0x378
irq 0x70 = 7
end
device pnp 2e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.8 on # HW Monitor
io 0x60 = 0x290
chip drivers/generic/generic # LM95221 CPU temp
device i2c 2b on end
end
chip drivers/generic/generic # EMCT03
device i2c 54 on end
end
end end
device pnp 2e.a on # RT device pnp 2e.3 off # Parallel Port
io 0x60 = 0x400 io 0x60 = 0x378
irq 0x70 = 7
end end
end device pnp 2e.4 on # Com1
io 0x60 = 0x3f8
irq 0x70 = 4
end
device pnp 2e.5 off # Com2
io 0x60 = 0x2f8
irq 0x70 = 3
end
device pnp 2e.7 on # Keyboard
io 0x60 = 0x60
io 0x62 = 0x64
irq 0x70 = 1
irq 0x72 = 12
end
device pnp 2e.8 on # HW Monitor
io 0x60 = 0x290
chip drivers/generic/generic # LM95221 CPU temp
device i2c 2b on end
end
chip drivers/generic/generic # EMCT03
device i2c 54 on end
end
end
device pnp 2e.a on # RT
io 0x60 = 0x400
end
end
end end
device pci 1.1 on # SM 0 device pci 1.1 on # SM 0
chip drivers/generic/generic #dimm 0-0-0 chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end device i2c 50 on end
end end
chip drivers/generic/generic #dimm 0-0-1 chip drivers/generic/generic #dimm 0-0-1
device i2c 51 on end device i2c 51 on end
end end
chip drivers/generic/generic #dimm 0-1-0 chip drivers/generic/generic #dimm 0-1-0
device i2c 52 on end device i2c 52 on end
end end
chip drivers/generic/generic #dimm 0-1-1 chip drivers/generic/generic #dimm 0-1-1
device i2c 53 on end device i2c 53 on end
end end
chip drivers/generic/generic #dimm 1-0-0 chip drivers/generic/generic #dimm 1-0-0
device i2c 54 on end device i2c 54 on end
end end
chip drivers/generic/generic #dimm 1-0-1 chip drivers/generic/generic #dimm 1-0-1
device i2c 55 on end device i2c 55 on end
end end
chip drivers/generic/generic #dimm 1-1-0 chip drivers/generic/generic #dimm 1-1-0
device i2c 56 on end device i2c 56 on end
end end
chip drivers/generic/generic #dimm 1-1-1 chip drivers/generic/generic #dimm 1-1-1
device i2c 57 on end device i2c 57 on end
end end
end # SM end # SM
device pci 1.1 on # SM 1 device pci 1.1 on # SM 1
#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? chip drivers/generic/generic #MAC EEPROM
# chip drivers/generic/generic #PCIXA Slot1 device i2c 51 on end
# device i2c 50 on end end
# end
# chip drivers/generic/generic #PCIXB Slot1
# device i2c 51 on end
# end
# chip drivers/generic/generic #PCIXB Slot2
# device i2c 52 on end
# end
# chip drivers/generic/generic #PCI Slot1
# device i2c 53 on end
# end
# chip drivers/generic/generic #Master CK804 PCI-E
# device i2c 54 on end
# end
# chip drivers/generic/generic #Slave CK804 PCI-E
# device i2c 55 on end
# end
chip drivers/generic/generic #MAC EEPROM
device i2c 51 on end
end
end # SM end # SM
device pci 2.0 on end # USB 1.1 device pci 2.0 on end # USB 1.1
device pci 2.1 on end # USB 2 device pci 2.1 on end # USB 2
device pci 4.0 on end # ACI device pci 4.0 on end # ACI
device pci 4.1 off end # MCI device pci 4.1 off end # MCI
device pci 6.0 on end # IDE device pci 6.0 on end # IDE
device pci 7.0 on end # SATA 1 device pci 7.0 on end # SATA 1
device pci 8.0 on end # SATA 0 device pci 8.0 on end # SATA 0
device pci 9.0 on end # PCI device pci 9.0 on end # PCI
device pci a.0 on end # NIC device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3 device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2 device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1 device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
register "ide0_enable" = "1" register "ide0_enable" = "1"
register "ide1_enable" = "1" register "ide1_enable" = "1"
register "sata0_enable" = "1" register "sata0_enable" = "1"
register "sata1_enable" = "1" register "sata1_enable" = "1"
# register "nic_rom_address" = "0xfff80000" # 64k # register "nic_rom_address" = "0xfff80000" # 64k
# register "raid_rom_address" = "0xfff90000" # register "raid_rom_address" = "0xfff90000"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
@@ -362,50 +343,50 @@ chip northbridge/amd/amdk8/root_complex
end # device pci 18.0 end # device pci 18.0
device pci 18.0 on end # Link 1 device pci 18.0 on end # Link 1
device pci 18.0 on device pci 18.0 on
# devices on link 2, link 2 == LDT 2 # devices on link 2, link 2 == LDT 2
chip southbridge/amd/amd8131 chip southbridge/amd/amd8131
# the on/off keyword is mandatory # the on/off keyword is mandatory
device pci 0.0 on end device pci 0.0 on end
device pci 0.1 on end device pci 0.1 on end
device pci 1.0 on device pci 1.0 on
chip drivers/pci/onboard chip drivers/pci/onboard
device pci 6.0 on end # lsi scsi device pci 6.0 on end # lsi scsi
device pci 6.1 on end device pci 6.1 on end
end end
end end
device pci 1.1 on end device pci 1.1 on end
end end
end # device pci 18.0 end # device pci 18.0
device pci 18.1 on end device pci 18.1 on end
device pci 18.2 on end device pci 18.2 on end
device pci 18.3 on end device pci 18.3 on end
end # mc0 end #mc0
chip northbridge/amd/amdk8 chip northbridge/amd/amdk8
device pci 19.0 on # northbridge device pci 19.0 on # northbridge
# devices on link 0, link 0 == LDT 0 # devices on link 0, link 0 == LDT 0
chip southbridge/nvidia/ck804 chip southbridge/nvidia/ck804
device pci 0.0 on end # HT device pci 0.0 on end # HT
device pci 1.0 on end # LPC device pci 1.0 on end # LPC
device pci 1.1 off end # SM device pci 1.1 off end # SM
device pci 2.0 off end # USB 1.1 device pci 2.0 off end # USB 1.1
device pci 2.1 off end # USB 2 device pci 2.1 off end # USB 2
device pci 4.0 off end # ACI device pci 4.0 off end # ACI
device pci 4.1 off end # MCI device pci 4.1 off end # MCI
device pci 6.0 off end # IDE device pci 6.0 off end # IDE
device pci 7.0 off end # SATA 1 device pci 7.0 off end # SATA 1
device pci 8.0 off end # SATA 0 device pci 8.0 off end # SATA 0
device pci 9.0 off end # PCI device pci 9.0 off end # PCI
device pci a.0 on end # NIC device pci a.0 on end # NIC
device pci b.0 off end # PCI E 3 device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2 device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1 device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0 device pci e.0 on end # PCI E 0
# register "nic_rom_address" = "0xfff80000" # 64k # register "nic_rom_address" = "0xfff80000" # 64k
register "mac_eeprom_smbus" = "3" register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51" register "mac_eeprom_addr" = "0x51"
end end
end # device pci 19.0 end # device pci 19.0
device pci 19.0 on end device pci 19.0 on end
device pci 19.0 on end device pci 19.0 on end
@@ -415,14 +396,14 @@ chip northbridge/amd/amdk8/root_complex
end end
end # PCI domain end # PCI domain
# chip drivers/generic/debug # chip drivers/generic/debug
# device pnp 0.0 off end # chip name # device pnp 0.0 off end # chip name
# device pnp 0.1 off end # pci_regs_all # device pnp 0.1 off end # pci_regs_all
# device pnp 0.2 off end # mem # device pnp 0.2 off end # mem
# device pnp 0.3 off end # cpuid # device pnp 0.3 off end # cpuid
# device pnp 0.4 on end # smbus_regs_all # device pnp 0.4 on end # smbus_regs_all
# device pnp 0.5 off end # dual core msr # device pnp 0.5 off end # dual core msr
# device pnp 0.6 off end # cache size # device pnp 0.6 off end # cache size
# device pnp 0.7 off end # tsc # device pnp 0.7 off end # tsc
# end # end
end #root_complex end # root_complex

2
src/mainboard/tyan/s2895/Options.lb
View File

@@ -166,7 +166,7 @@ default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#Opteron K8 1G HT Support #Opteron K8 1G HT Support
default K8_HT_FREQ_1G_SUPPORT=1 default K8_HT_FREQ_1G_SUPPORT=1
#VGA #VGA Console
default CONFIG_CONSOLE_VGA=1 default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1 default CONFIG_PCI_ROM_RUN=1

71
src/mainboard/tyan/s2895/auto.c
View File

@@ -37,20 +37,20 @@
static void hard_reset(void) static void hard_reset(void)
{ {
set_bios_reset(); set_bios_reset();
/* full reset */ /* full reset */
outb(0x0a, 0x0cf9); outb(0x0a, 0x0cf9);
outb(0x0e, 0x0cf9); outb(0x0e, 0x0cf9);
} }
static void soft_reset(void) static void soft_reset(void)
{ {
set_bios_reset(); set_bios_reset();
#if 1 #if 1
/* link reset */ /* link reset */
outb(0x02, 0x0cf9); outb(0x02, 0x0cf9);
outb(0x06, 0x0cf9); outb(0x06, 0x0cf9);
#endif #endif
} }
@@ -71,13 +71,9 @@ static void sio_gpio_setup(void){
unsigned value; unsigned value;
// lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c // lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
#if 1
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
#endif
} }
static inline void activate_spd_rom(const struct mem_controller *ctrl) static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -91,23 +87,14 @@ static inline int spd_read_byte(unsigned device, unsigned address)
} }
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#if 0
#define ENABLE_APIC_EXT_ID 1
#define APIC_ID_OFFSET 0x10
#define LIFT_BSP_APIC_ID 0
#else
#define ENABLE_APIC_EXT_ID 0
#endif
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
/* tyan does not want the default */ /* tyan does not want the default */
#include "resourcemap.c" #include "resourcemap.c"
#define FIRST_CPU 1
#define FIRST_CPU 1
#define SECOND_CPU 1 #define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -116,19 +103,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#define CK804_USE_NIC 1 #define CK804_USE_NIC 1
#define CK804_USE_ACI 1 #define CK804_USE_ACI 1
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode //set GPIO to input mode
#define CK804_MB_SETUP \ #define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup.c" #include "southbridge/nvidia/ck804/ck804_early_setup.c"
static void main(unsigned long bist) static void main(unsigned long bist)
{ {
static const struct mem_controller cpu[] = { static const struct mem_controller cpu[] = {
@@ -156,41 +141,37 @@ static void main(unsigned long bist)
#endif #endif
}; };
int needs_reset; int needs_reset;
if (bist == 0) { if (bist == 0) {
k8_init_and_stop_secondaries(); k8_init_and_stop_secondaries();
} }
// post_code(0x32); lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); console_init();
uart_init();
console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
sio_gpio_setup(); sio_gpio_setup();
setup_s2895_resource_map(); setup_s2895_resource_map();
needs_reset = setup_coherent_ht_domain(); needs_reset = setup_coherent_ht_domain();
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
soft_reset(); soft_reset();
} }
enable_smbus(); enable_smbus();
memreset_setup(); memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
} }

218
src/mainboard/tyan/s2895/cache_as_ram_auto.c
View File

@@ -1,18 +1,16 @@
#define ASSEMBLY 1 #define ASSEMBLY 1
#define __ROMCC__ #define __ROMCC__
#define K8_ALLOCATE_IO_RANGE 1 #define K8_ALLOCATE_IO_RANGE 1
//#define K8_SCAN_PCI_BUS 1 //#define K8_SCAN_PCI_BUS 1
//used by raminit
#define QRANK_DIMM_SUPPORT 1 #define QRANK_DIMM_SUPPORT 1
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#define SET_NB_CFG_54 1 #define SET_NB_CFG_54 1
#endif #endif
#include <stdint.h> #include <stdint.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <arch/io.h> #include <arch/io.h>
@@ -27,17 +25,6 @@
#include "arch/i386/lib/console.c" #include "arch/i386/lib/console.c"
#include "ram/ramtest.c" #include "ram/ramtest.c"
#if 0
static void post_code(uint8_t value) {
#if 1
int i;
for(i=0;i<0x8000;i++) {
outb(value, 0x80);
}
#endif
}
#endif
#include <cpu/amd/model_fxx_rev.h> #include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -68,7 +55,6 @@ static void post_code(uint8_t value) {
#include "cpu/amd/mtrr/amd_earlymtrr.c" #include "cpu/amd/mtrr/amd_earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
@@ -81,15 +67,14 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
{ {
} }
static void sio_gpio_setup(void){ static void sio_gpio_setup(void){
unsigned value; unsigned value;
/*Enable onboard scsi*/ /*Enable onboard scsi*/
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
} }
@@ -103,7 +88,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address); return smbus_read_byte(device, address);
} }
#include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c" #include "sdram/generic_sdram.c"
@@ -122,12 +106,12 @@ static inline int spd_read_byte(unsigned device, unsigned address)
//set GPIO to input mode //set GPIO to input mode
#define CK804_MB_SETUP \ #define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c" #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
@@ -144,105 +128,103 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "southbridge/nvidia/ck804/ck804_enable_rom.c" #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c" #include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void) static void sio_setup(void)
{ {
unsigned value; unsigned value;
uint32_t dword; uint32_t dword;
uint8_t byte; uint8_t byte;
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
byte |= 0x20;
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
byte |= 0x20; dword |= (1<<29)|(1<<0);
pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
dword |= (1<<29)|(1<<0); dword |= (1<<16);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4); lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
dword |= (1<<16); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
value &= 0xbf;
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
} }
void failover_process(unsigned long bist, unsigned long cpu_init_detectedx) void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
unsigned last_boot_normal_x = last_boot_normal(); unsigned last_boot_normal_x = last_boot_normal();
/* Is this a cpu only reset? or Is this a secondary cpu? */ /* Is this a cpu only reset? or Is this a secondary cpu? */
if ((cpu_init_detectedx) || (!boot_cpu())) { if ((cpu_init_detectedx) || (!boot_cpu())) {
if (last_boot_normal_x) { if (last_boot_normal_x) {
goto normal_image; goto normal_image;
} else { } else {
goto fallback_image; goto fallback_image;
} }
} }
/* Nothing special needs to be done to find bus 0 */ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */ /* Allow the HT devices to be found */
enumerate_ht_chain(); enumerate_ht_chain();
sio_setup(); sio_setup();
/* Setup the ck804 */ /* Setup the ck804 */
ck804_enable_rom(); ck804_enable_rom();
/* Is this a deliberate reset by the bios */ /* Is this a deliberate reset by the bios */
// post_code(0x22); // post_code(0x22);
if (bios_reset_detected() && last_boot_normal_x) { if (bios_reset_detected() && last_boot_normal_x) {
goto normal_image; goto normal_image;
} }
/* This is the primary cpu how should I boot? */ /* This is the primary cpu how should I boot? */
else if (do_normal_boot()) { else if (do_normal_boot()) {
goto normal_image; goto normal_image;
} }
else { else {
goto fallback_image; goto fallback_image;
} }
normal_image: normal_image:
// post_code(0x23); // post_code(0x23);
__asm__ volatile ("jmp __normal_image" __asm__ volatile ("jmp __normal_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
); );
fallback_image: fallback_image:
// post_code(0x25); // post_code(0x25);
#if HAVE_FAILOVER_BOOT==1 #if HAVE_FAILOVER_BOOT==1
__asm__ volatile ("jmp __fallback_image" __asm__ volatile ("jmp __fallback_image"
: /* outputs */ : /* outputs */
: "a" (bist), "b" (cpu_init_detectedx) /* inputs */ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
) )
#endif #endif
; ;
} }
#endif #endif
void real_main(unsigned long bist, unsigned long cpu_init_detectedx); void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
#if HAVE_FAILOVER_BOOT==1 #if HAVE_FAILOVER_BOOT==1
#if USE_FAILOVER_IMAGE==1 #if USE_FAILOVER_IMAGE==1
failover_process(bist, cpu_init_detectedx); failover_process(bist, cpu_init_detectedx);
#else #endif
real_main(bist, cpu_init_detectedx);
#endif
#else #else
#if USE_FALLBACK_IMAGE == 1 #if USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx); failover_process(bist, cpu_init_detectedx);
#endif #endif
real_main(bist, cpu_init_detectedx);
#endif #endif
real_main(bist, cpu_init_detectedx);
} }
#if USE_FAILOVER_IMAGE==0 #if USE_FAILOVER_IMAGE==0
@@ -250,38 +232,38 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
void real_main(unsigned long bist, unsigned long cpu_init_detectedx) void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
{ {
static const uint16_t spd_addr [] = { static const uint16_t spd_addr [] = {
(0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1 #if CONFIG_MAX_PHYSICAL_CPUS > 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0,
#endif #endif
}; };
int needs_reset; int needs_reset;
unsigned bsp_apicid = 0; unsigned bsp_apicid = 0;
struct mem_controller ctrl[8]; struct mem_controller ctrl[8];
unsigned nodes; unsigned nodes;
if (bist == 0) { if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx); bsp_apicid = init_cpus(cpu_init_detectedx);
} }
// post_code(0x32); // post_code(0x32);
lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE); lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init(); uart_init();
console_init(); console_init();
/* Halt if there was a built in self test failure */ /* Halt if there was a built in self test failure */
report_bist_failure(bist); report_bist_failure(bist);
sio_gpio_setup(); sio_gpio_setup();
setup_mb_resource_map(); setup_mb_resource_map();
#if 0 #if 0
dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif #endif
@@ -289,25 +271,25 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
wait_all_core0_started(); wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched // It is said that we should start core1 after all core0 launched
start_other_cores(); start_other_cores();
wait_all_other_cores_started(bsp_apicid); wait_all_other_cores_started(bsp_apicid);
#endif #endif
needs_reset |= ht_setup_chains_x(); needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x(); needs_reset |= ck804_early_setup_x();
if (needs_reset) { if (needs_reset) {
print_info("ht reset -\r\n"); print_info("ht reset -\r\n");
// soft_reset(); // soft_reset();
} }
allow_all_aps_stop(bsp_apicid); allow_all_aps_stop(bsp_apicid);
nodes = get_nodes(); nodes = get_nodes();
//It's the time to set ctrl now; //It's the time to set ctrl now;
fill_mem_ctrl(nodes, ctrl, spd_addr); fill_mem_ctrl(nodes, ctrl, spd_addr);
enable_smbus(); enable_smbus();
#if 0 #if 0

2
src/mainboard/tyan/s2895/failover.c
View File

@@ -50,14 +50,12 @@ static void sio_setup(void)
} }
#if CONFIG_LOGICAL_CPUS==1 #if CONFIG_LOGICAL_CPUS==1
#include "cpu/amd/dualcore/dualcore_id.c" #include "cpu/amd/dualcore/dualcore_id.c"
#else #else
#include "cpu/amd/model_fxx/node_id.c" #include "cpu/amd/model_fxx/node_id.c"
#endif #endif
static unsigned long main(unsigned long bist) static unsigned long main(unsigned long bist)
{ {
/* Is this a cpu only reset? */ /* Is this a cpu only reset? */

104
src/mainboard/tyan/s2895/get_bus_conf.c
View File

@@ -9,7 +9,6 @@
#include <cpu/amd/amdk8_sysconf.h> #include <cpu/amd/amdk8_sysconf.h>
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default //busnum is default
unsigned char bus_isa; unsigned char bus_isa;
@@ -56,6 +55,7 @@ unsigned hcdnx[] =
// 0x20202020, // 0x20202020,
// 0x20202020, // 0x20202020,
}; };
unsigned sbdn3; unsigned sbdn3;
unsigned sbdnb; unsigned sbdnb;
@@ -97,63 +97,15 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x09,0));
if (dev) { if (dev) {
bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
#if 0
bus_ck804_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_2++;
#else
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_5++; bus_ck804_5++;
#endif
} }
else { else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09); printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x09);
bus_ck804_1 = 2; bus_ck804_1 = 2;
#if 0
bus_ck804_2 = 3;
#else
bus_ck804_5 = 3; bus_ck804_5 = 3;
#endif
} }
#if 0
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0b,0));
if (dev) {
bus_ck804_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_3++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0b);
bus_ck804_3 = bus_ck804_2+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0c,0));
if (dev) {
bus_ck804_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_4++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x0c);
bus_ck804_4 = bus_ck804_3+1;
}
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn + 0x0d,0));
if (dev) {
bus_ck804_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804_5++;
}
else {
printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",sbdn + 0x0d);
bus_ck804_5 = bus_ck804_4+1;
}
#endif
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) { if (dev) {
@@ -194,56 +146,6 @@ void get_bus_conf(void)
if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed if(sysconf.pci1234[2] & 0x0f) { //if the second cpu is installed
bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff; bus_ck804b_0 = (sysconf.pci1234[2]>>16) & 0xff;
#if 0
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x09,0));
if (dev) {
bus_ck804b_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_2++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x09);
bus_ck804b_1 = bus_ck804b_0+1;
bus_ck804b_2 = bus_ck804b_0+2;
}
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0b,0));
if (dev) {
bus_ck804b_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_3 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_3++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0b);
bus_ck804b_2 = bus_ck804b_0+1;
bus_ck804b_3 = bus_ck804b_0+2;
}
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0c,0));
if (dev) {
bus_ck804b_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_4 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_4++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0c);
bus_ck804b_4 = bus_ck804b_3+1;
}
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0d,0));
if (dev) {
bus_ck804b_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_ck804b_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_ck804b_5++;
}
else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0d);
bus_ck804b_5 = bus_ck804b_4+1;
}
#endif
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0)); dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
if (dev) { if (dev) {
@@ -253,10 +155,7 @@ void get_bus_conf(void)
} }
else { else {
printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e); printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
#if 1
bus_ck804b_5 = bus_ck804b_4+1; bus_ck804b_5 = bus_ck804b_4+1;
#endif
bus_isa = bus_ck804b_5+1; bus_isa = bus_ck804b_5+1;
} }
} }
@@ -272,5 +171,4 @@ void get_bus_conf(void)
apicid_8131_1 = apicid_base+1; apicid_8131_1 = apicid_base+1;
apicid_8131_2 = apicid_base+2; apicid_8131_2 = apicid_base+2;
apicid_ck804b = apicid_base+3; apicid_ck804b = apicid_base+3;
} }

112
src/mainboard/tyan/s2895/irq_tables.c
View File

@@ -16,18 +16,18 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t dev
uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
uint8_t slot, uint8_t rfu) uint8_t slot, uint8_t rfu)
{ {
pirq_info->bus = bus; pirq_info->bus = bus;
pirq_info->devfn = devfn; pirq_info->devfn = devfn;
pirq_info->irq[0].link = link0; pirq_info->irq[0].link = link0;
pirq_info->irq[0].bitmap = bitmap0; pirq_info->irq[0].bitmap = bitmap0;
pirq_info->irq[1].link = link1; pirq_info->irq[1].link = link1;
pirq_info->irq[1].bitmap = bitmap1; pirq_info->irq[1].bitmap = bitmap1;
pirq_info->irq[2].link = link2; pirq_info->irq[2].link = link2;
pirq_info->irq[2].bitmap = bitmap2; pirq_info->irq[2].bitmap = bitmap2;
pirq_info->irq[3].link = link3; pirq_info->irq[3].link = link3;
pirq_info->irq[3].bitmap = bitmap3; pirq_info->irq[3].bitmap = bitmap3;
pirq_info->slot = slot; pirq_info->slot = slot;
pirq_info->rfu = rfu; pirq_info->rfu = rfu;
} }
extern unsigned char bus_ck804_0; //1 extern unsigned char bus_ck804_0; //1
@@ -50,6 +50,8 @@ extern unsigned char bus_ck804b_5;//f
extern unsigned sbdn3; extern unsigned sbdn3;
extern unsigned sbdnb; extern unsigned sbdnb;
extern void get_bus_conf(void);
unsigned long write_pirq_routing_table(unsigned long addr) unsigned long write_pirq_routing_table(unsigned long addr)
{ {
@@ -59,18 +61,18 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t *v; uint8_t *v;
unsigned sbdn; unsigned sbdn;
uint8_t sum=0; uint8_t sum=0;
int i; int i;
get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */ /* Align the table to be 16 byte aligned. */
addr += 15; addr += 15;
addr &= ~15; addr &= ~15;
/* This table must be betweeen 0xf0000 & 0x100000 */ /* This table must be betweeen 0xf0000 & 0x100000 */
printk_info("Writing IRQ routing tables to 0x%x...", addr); printk_info("Writing IRQ routing tables to 0x%x...", addr);
pirq = (void *)(addr); pirq = (void *)(addr);
v = (uint8_t *)(addr); v = (uint8_t *)(addr);
@@ -96,81 +98,81 @@ unsigned long write_pirq_routing_table(unsigned long addr)
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//pcix bridge //pcix bridge
write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); write_pirq_info(pirq_info, bus_8131_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
if(sysconf.pci1234[2] & 0xf) { if(sysconf.pci1234[2] & 0xf) {
//second pci beidge //second pci beidge
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0); write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+9)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
} }
#if 0 #if 0
//smbus //smbus
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+1)<<3)|0, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//usb //usb
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+2)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//audio //audio
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+4)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//sata //sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+7)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//sata //sata
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+8)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//nic //nic
write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_0, ((sbdn+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot1 PCIE x16 //Slot1 PCIE x16
write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0); write_pirq_info(pirq_info, bus_ck804_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 1, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//firewire //firewire
write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804_1, (0x5<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot2 pci //Slot2 pci
write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0); write_pirq_info(pirq_info, bus_ck804_1, (0x4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 2, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//nic //nic
write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_ck804b_0, ((sbdnb+0xa)<<3)|0, 0x1, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot3 PCIE x16 //Slot3 PCIE x16
write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0); write_pirq_info(pirq_info, bus_ck804b_5, (0<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 3, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot4 PCIX //Slot4 PCIX
write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0); write_pirq_info(pirq_info, bus_8131_2, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 4, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot5 PCIX //Slot5 PCIX
write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0); write_pirq_info(pirq_info, bus_8131_2, (9<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 5, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//onboard scsi //onboard scsi
write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0); write_pirq_info(pirq_info, bus_8131_2, (6<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
//Slot6 PCIX //Slot6 PCIX
write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0); write_pirq_info(pirq_info, bus_8131_1, (4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 6, 0);
pirq_info++; slot_num++; pirq_info++; slot_num++;
#endif #endif
pirq->size = 32 + 16 * slot_num; pirq->size = 32 + 16 * slot_num;
for (i = 0; i < pirq->size; i++) for (i = 0; i < pirq->size; i++)
sum += v[i]; sum += v[i];
sum = pirq->checksum - sum; sum = pirq->checksum - sum;
if (sum != pirq->checksum) { if (sum != pirq->checksum) {
pirq->checksum = sum; pirq->checksum = sum;
} }
printk_info("done.\n"); printk_info("done.\n");

160
src/mainboard/tyan/s2895/mptable.c
View File

@@ -30,54 +30,56 @@ extern unsigned apicid_ck804b;
extern unsigned sbdn3; extern unsigned sbdn3;
extern unsigned sbdnb; extern unsigned sbdnb;
extern void get_bus_conf(void);
void *smp_write_config_table(void *v) void *smp_write_config_table(void *v)
{ {
static const char sig[4] = "PCMP"; static const char sig[4] = "PCMP";
static const char oem[8] = "TYAN "; static const char oem[8] = "TYAN ";
static const char productid[12] = "S2895 "; static const char productid[12] = "S2895 ";
struct mp_config_table *mc; struct mp_config_table *mc;
unsigned sbdn; unsigned sbdn;
unsigned char bus_num; unsigned char bus_num;
int i; int i;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc)); memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig)); memcpy(mc->mpc_signature, sig, sizeof(sig));
mc->mpc_length = sizeof(*mc); /* initially just the header */ mc->mpc_length = sizeof(*mc); /* initially just the header */
mc->mpc_spec = 0x04; mc->mpc_spec = 0x04;
mc->mpc_checksum = 0; /* not yet computed */ mc->mpc_checksum = 0; /* not yet computed */
memcpy(mc->mpc_oem, oem, sizeof(oem)); memcpy(mc->mpc_oem, oem, sizeof(oem));
memcpy(mc->mpc_productid, productid, sizeof(productid)); memcpy(mc->mpc_productid, productid, sizeof(productid));
mc->mpc_oemptr = 0; mc->mpc_oemptr = 0;
mc->mpc_oemsize = 0; mc->mpc_oemsize = 0;
mc->mpc_entry_count = 0; /* No entries yet... */ mc->mpc_entry_count = 0; /* No entries yet... */
mc->mpc_lapic = LAPIC_ADDR; mc->mpc_lapic = LAPIC_ADDR;
mc->mpe_length = 0; mc->mpe_length = 0;
mc->mpe_checksum = 0; mc->mpe_checksum = 0;
mc->reserved = 0; mc->reserved = 0;
smp_write_processors(mc); smp_write_processors(mc);
get_bus_conf(); get_bus_conf();
sbdn = sysconf.sbdn; sbdn = sysconf.sbdn;
/*Bus: Bus ID Type*/ /*Bus: Bus ID Type*/
/* define bus and isa numbers */ /* define bus and isa numbers */
for(bus_num = 0; bus_num < bus_isa; bus_num++) { for(bus_num = 0; bus_num < bus_isa; bus_num++) {
smp_write_bus(mc, bus_num, "PCI "); smp_write_bus(mc, bus_num, "PCI ");
} }
smp_write_bus(mc, bus_isa, "ISA "); smp_write_bus(mc, bus_isa, "ISA ");
/*I/O APICs: APIC ID Version State Address*/ /*I/O APICs: APIC ID Version State Address*/
{ {
device_t dev; device_t dev;
struct resource *res; struct resource *res;
uint32_t dword; uint32_t dword;
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0)); dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_ck804, 0x11, res->base); smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
@@ -86,49 +88,49 @@ void *smp_write_config_table(void *v)
/* Initialize interrupt mapping*/ /* Initialize interrupt mapping*/
dword = 0x0120d218; dword = 0x0120d218;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x12008a00; dword = 0x12008a00;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0x00080d7d; dword = 0x00080d7d;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
} }
} }
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1)); dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base); smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
} }
} }
if(sysconf.pci1234[2] & 0xf) { if(sysconf.pci1234[2] & 0xf) {
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0)); dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
if (dev) { if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_1); res = find_resource(dev, PCI_BASE_ADDRESS_1);
if (res) { if (res) {
smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base); smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
} }
dword = 0x0000d218; dword = 0x0000d218;
pci_write_config32(dev, 0x7c, dword); pci_write_config32(dev, 0x7c, dword);
dword = 0x00000000; dword = 0x00000000;
pci_write_config32(dev, 0x80, dword); pci_write_config32(dev, 0x80, dword);
dword = 0x00000d00; dword = 0x00000d00;
pci_write_config32(dev, 0x84, dword); pci_write_config32(dev, 0x84, dword);
} }
} }
} }
@@ -148,73 +150,73 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_ck804, 0xf);
// Onboard ck804 smbus // Onboard ck804 smbus
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
// 10 // 10
// Onboard ck804 USB 1.1 // Onboard ck804 USB 1.1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
// Onboard ck804 USB 2 // Onboard ck804 USB 2
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
// Onboard ck804 Audio // Onboard ck804 Audio
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
// Onboard ck804 SATA 0 // Onboard ck804 SATA 0
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
// Onboard ck804 SATA 1 // Onboard ck804 SATA 1
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
// Onboard ck804 NIC // Onboard ck804 NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
//Slot 1 PCIE x16 //Slot 1 PCIE x16
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
} }
//Onboard Firewire //Onboard Firewire
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
//Slot 2 PCI 32 //Slot 2 PCI 32
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4);
} }
if(sysconf.pci1234[2] & 0xf) { if(sysconf.pci1234[2] & 0xf) {
//Onboard ck804b NIC //Onboard ck804b NIC
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
//Slot 3 PCIE x16 //Slot 3 PCIE x16
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
} }
} }
//Channel B of 8131 //Channel B of 8131
//Slot 4 PCI-X 100/66 //Slot 4 PCI-X 100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
} }
//Slot 5 PCIX 100/66 //Slot 5 PCIX 100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
} }
//OnBoard LSI SCSI //OnBoard LSI SCSI
for(i=0;i<2;i++) { for(i=0;i<2;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
} }
//Channel A of 8131 //Channel A of 8131
//Slot 6 PCIX 133/100/66 //Slot 6 PCIX 133/100/66
for(i=0;i<4;i++) { for(i=0;i<4;i++) {
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
} }
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);