soc/qualcomm/ipq40xx: Initial commit for IPQ40xx SoC support
Copy 'ipq806x' files as a template BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: dc6a5937953fe61cd4b5a99ca49f9371c4b712d4 Original-Change-Id: If171fcdd3b0561cb6b7dab5f8434de7ef711ea41 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/333178 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> squashed: soc/qualcomm/ipq40xx: Update ipq806x/storm references Since the files were taken from ipq806x/storm as template. Update those references to reflect ipq40xx/gale. BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Original-Commit-Id: c6c76d184cc92c09e6826fbdc7d7fac59b2cb69b Original-Change-Id: Ieae1bce25291243b4a6034d37a6949978f318997 Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/333293 Original-Commit-Ready: David Hendricks <dhendrix@chromium.org> Original-Tested-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ie5794c48131ae562861074b406106734541880d9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/14644 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Varadarajan Narayanan
committed by
Patrick Georgi
Patrick Georgi
parent
c84e2fe893
commit
a6935c2508
406
src/soc/qualcomm/ipq40xx/uart.c
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406
src/soc/qualcomm/ipq40xx/uart.c
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@@ -0,0 +1,406 @@
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/*
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* Copyright (c) 2012 The Linux Foundation. All rights reserved.
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* Source : APQ8064 LK boot
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of The Linux Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <console/console.h>
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#include <console/uart.h>
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#include <delay.h>
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#include <gpio.h>
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#include <soc/clock.h>
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#include <soc/gsbi.h>
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#include <soc/ipq_uart.h>
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#include <stdint.h>
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#include <stdlib.h>
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#define FIFO_DATA_SIZE 4
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typedef struct {
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void *uart_dm_base;
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void *uart_gsbi_base;
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unsigned uart_gsbi;
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uart_clk_mnd_t mnd_value;
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gpio_func_data_t dbg_uart_gpio[NO_OF_DBG_UART_GPIOS];
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} uart_params_t;
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/*
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* All constants lifted from u-boot's
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* board/qcom/ipq40xx_cdp/ipq40xx_board_param.h
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*/
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static const uart_params_t uart_board_param = {
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.uart_dm_base = (void *)UART4_DM_BASE,
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.uart_gsbi_base = (void *)UART_GSBI4_BASE,
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.uart_gsbi = GSBI_4,
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.mnd_value = { 12, 625, 313 },
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.dbg_uart_gpio = {
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{
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.gpio = 10,
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.func = 1,
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.dir = GPIO_OUTPUT,
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.pull = GPIO_NO_PULL,
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.drvstr = GPIO_12MA,
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.enable = GPIO_DISABLE
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},
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{
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.gpio = 11,
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.func = 1,
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.dir = GPIO_INPUT,
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.pull = GPIO_NO_PULL,
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.drvstr = GPIO_12MA,
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.enable = GPIO_DISABLE
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},
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}
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};
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/**
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* msm_boot_uart_dm_init_rx_transfer - Init Rx transfer
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base)
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{
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/* Reset receiver */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CMD_RESET_RX);
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/* Enable receiver */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CR_RX_ENABLE);
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write32(MSM_BOOT_UART_DM_DMRX(uart_dm_base),
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MSM_BOOT_UART_DM_DMRX_DEF_VALUE);
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/* Clear stale event */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
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/* Enable stale event */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_GCMD_ENA_STALE_EVT);
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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#if IS_ENABLED(CONFIG_DRIVERS_UART)
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static unsigned int msm_boot_uart_dm_init(void *uart_dm_base);
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/* Received data is valid or not */
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static int valid_data = 0;
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/* Received data */
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static unsigned int word = 0;
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/**
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* msm_boot_uart_dm_read - reads a word from the RX FIFO.
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* @data: location where the read data is stored
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* @count: no of valid data in the FIFO
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* @wait: indicates blocking call or not blocking call
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*
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* Reads a word from the RX FIFO. If no data is available blocks if
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* @wait is true, else returns %MSM_BOOT_UART_DM_E_RX_NOT_READY.
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*/
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#if 0 /* Not used yet */
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static unsigned int
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msm_boot_uart_dm_read(unsigned int *data, int *count, int wait)
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{
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static int total_rx_data = 0;
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static int rx_data_read = 0;
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void *base;
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uint32_t status_reg;
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base = uart_board_param.uart_dm_base;
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if (data == NULL)
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return MSM_BOOT_UART_DM_E_INVAL;
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status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
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/* Check for DM_RXSTALE for RX transfer to finish */
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while (!(status_reg & MSM_BOOT_UART_DM_RXSTALE)) {
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status_reg = readl(MSM_BOOT_UART_DM_MISR(base));
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if (!wait)
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* Check for Overrun error. We'll just reset Error Status */
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if (readl(MSM_BOOT_UART_DM_SR(base)) &
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MSM_BOOT_UART_DM_SR_UART_OVERRUN) {
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writel(MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT,
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MSM_BOOT_UART_DM_CR(base));
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total_rx_data = rx_data_read = 0;
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msm_boot_uart_dm_init(base);
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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}
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/* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */
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if (total_rx_data == 0)
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total_rx_data = readl(MSM_BOOT_UART_DM_RX_TOTAL_SNAP(base));
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/* Data available in FIFO; read a word. */
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*data = readl(MSM_BOOT_UART_DM_RF(base, 0));
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/* WAR for http://prism/CR/548280 */
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if (*data == 0)
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return MSM_BOOT_UART_DM_E_RX_NOT_READY;
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/* increment the total count of chars we've read so far */
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rx_data_read += FIFO_DATA_SIZE;
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/* actual count of valid data in word */
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*count = ((total_rx_data < rx_data_read) ?
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(FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) :
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FIFO_DATA_SIZE);
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/* If there are still data left in FIFO we'll read them before
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* initializing RX Transfer again
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*/
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if (rx_data_read < total_rx_data)
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return MSM_BOOT_UART_DM_E_SUCCESS;
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msm_boot_uart_dm_init_rx_transfer(base);
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total_rx_data = rx_data_read = 0;
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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#endif
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void uart_tx_byte(int idx, unsigned char data)
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{
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int num_of_chars = 1;
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unsigned tx_data = 0;
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void *base = uart_board_param.uart_dm_base;
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/* Wait until transmit FIFO is empty. */
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while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
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MSM_BOOT_UART_DM_SR_TXEMT))
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udelay(1);
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/*
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* TX FIFO is ready to accept new character(s). First write number of
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* characters to be transmitted.
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*/
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write32(MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base), num_of_chars);
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/* And now write the character(s) */
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write32(MSM_BOOT_UART_DM_TF(base, 0), tx_data);
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}
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#endif /* CONFIG_SERIAL_UART */
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/*
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* msm_boot_uart_dm_reset - resets UART controller
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* @base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_reset(void *base)
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{
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write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_RX);
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write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RESET_TX);
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write32(MSM_BOOT_UART_DM_CR(base),
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MSM_BOOT_UART_DM_CMD_RESET_ERR_STAT);
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write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_TX_ERR);
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write32(MSM_BOOT_UART_DM_CR(base), MSM_BOOT_UART_DM_CMD_RES_STALE_INT);
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return MSM_BOOT_UART_DM_E_SUCCESS;
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}
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/*
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* msm_boot_uart_dm_init - initilaizes UART controller
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* @uart_dm_base: UART controller base address
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*/
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static unsigned int msm_boot_uart_dm_init(void *uart_dm_base)
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{
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/* Configure UART mode registers MR1 and MR2 */
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/* Hardware flow control isn't supported */
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write32(MSM_BOOT_UART_DM_MR1(uart_dm_base), 0x0);
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/* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */
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write32(MSM_BOOT_UART_DM_MR2(uart_dm_base),
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MSM_BOOT_UART_DM_8_N_1_MODE);
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/* Configure Interrupt Mask register IMR */
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write32(MSM_BOOT_UART_DM_IMR(uart_dm_base),
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MSM_BOOT_UART_DM_IMR_ENABLED);
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/*
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* Configure Tx and Rx watermarks configuration registers
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* TX watermark value is set to 0 - interrupt is generated when
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* FIFO level is less than or equal to 0
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*/
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write32(MSM_BOOT_UART_DM_TFWR(uart_dm_base),
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MSM_BOOT_UART_DM_TFW_VALUE);
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/* RX watermark value */
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write32(MSM_BOOT_UART_DM_RFWR(uart_dm_base),
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MSM_BOOT_UART_DM_RFW_VALUE);
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/* Configure Interrupt Programming Register */
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/* Set initial Stale timeout value */
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write32(MSM_BOOT_UART_DM_IPR(uart_dm_base),
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MSM_BOOT_UART_DM_STALE_TIMEOUT_LSB);
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/* Configure IRDA if required */
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/* Disabling IRDA mode */
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write32(MSM_BOOT_UART_DM_IRDA(uart_dm_base), 0x0);
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/* Configure hunt character value in HCR register */
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/* Keep it in reset state */
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write32(MSM_BOOT_UART_DM_HCR(uart_dm_base), 0x0);
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/*
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* Configure Rx FIFO base address
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* Both TX/RX shares same SRAM and default is half-n-half.
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* Sticking with default value now.
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* As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries).
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* We have found RAM_ADDR_WIDTH = 0x7f
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*/
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/* Issue soft reset command */
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msm_boot_uart_dm_reset(uart_dm_base);
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/* Enable/Disable Rx/Tx DM interfaces */
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/* Data Mover not currently utilized. */
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write32(MSM_BOOT_UART_DM_DMEN(uart_dm_base), 0x0);
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/* Enable transmitter */
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write32(MSM_BOOT_UART_DM_CR(uart_dm_base),
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MSM_BOOT_UART_DM_CR_TX_ENABLE);
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/* Initialize Receive Path */
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msm_boot_uart_dm_init_rx_transfer(uart_dm_base);
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return 0;
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}
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/**
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* ipq40xx_uart_init - initializes UART
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*
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* Initializes clocks, GPIO and UART controller.
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*/
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void uart_init(int idx)
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{
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/* Note int idx isn't used in this driver. */
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void *dm_base;
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void *gsbi_base;
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dm_base = uart_board_param.uart_dm_base;
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if (read32(MSM_BOOT_UART_DM_CSR(dm_base)) == UART_DM_CLK_RX_TX_BIT_RATE)
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return; /* UART must have been already initialized. */
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gsbi_base = uart_board_param.uart_gsbi_base;
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ipq_configure_gpio(uart_board_param.dbg_uart_gpio,
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NO_OF_DBG_UART_GPIOS);
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/* Configure the uart clock */
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uart_clock_config(uart_board_param.uart_gsbi,
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uart_board_param.mnd_value.m_value,
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uart_board_param.mnd_value.n_value,
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uart_board_param.mnd_value.d_value,
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0);
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write32(GSBI_CTRL_REG(gsbi_base),
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GSBI_PROTOCOL_CODE_I2C_UART << GSBI_CTRL_REG_PROTOCOL_CODE_S);
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write32(MSM_BOOT_UART_DM_CSR(dm_base), UART_DM_CLK_RX_TX_BIT_RATE);
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/* Initialize UART_DM */
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msm_boot_uart_dm_init(dm_base);
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}
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/* for the benefit of non-console uart init */
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void ipq40xx_uart_init(void)
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{
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uart_init(0);
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}
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#if 0 /* Not used yet */
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uint32_t uartmem_getbaseaddr(void)
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{
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return (uint32_t)uart_board_param.uart_dm_base;
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}
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#endif
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/**
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* uart_tx_flush - transmits a string of data
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* @s: string to transmit
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*/
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void uart_tx_flush(int idx)
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{
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void *base = uart_board_param.uart_dm_base;
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while (!(read32(MSM_BOOT_UART_DM_SR(base)) &
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MSM_BOOT_UART_DM_SR_TXEMT))
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;
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}
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/**
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* uart_can_rx_byte - checks if data available for reading
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*
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* Returns 1 if data available, 0 otherwise
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*/
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#if 0 /* Not used yet */
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int uart_can_rx_byte(void)
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{
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/* Return if data is already read */
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if (valid_data)
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return 1;
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/* Read data from the FIFO */
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if (msm_boot_uart_dm_read(&word, &valid_data, 0) !=
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MSM_BOOT_UART_DM_E_SUCCESS)
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return 0;
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return 1;
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}
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#endif
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#if IS_ENABLED(CONFIG_DRIVERS_UART)
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/**
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* ipq40xx_serial_getc - reads a character
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*
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* Returns the character read from serial port.
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*/
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uint8_t uart_rx_byte(int idx)
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{
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uint8_t byte;
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#if 0 /* Not used yet */
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while (!uart_can_rx_byte())
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; /* wait for incoming data */
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#endif
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byte = (uint8_t)(word & 0xff);
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word = word >> 8;
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valid_data--;
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return byte;
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}
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#endif
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#ifndef __PRE_RAM__
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/* TODO: Implement function */
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void uart_fill_lb(void *data)
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{
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}
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#endif
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