cpu/intel: Move is_tme_supported() from soc/intel to cpu/intel

It makes the detection of this feature accessible without the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU dependency.

BUG=288978352
TEST=compilation

Change-Id: I005c4953648ac9a90af23818b251efbfd2c04043
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77697
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/common/Makefile.inc

@@ -1,5 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
+romstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c
 ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c

src/cpu/intel/common/common.h

@@ -66,4 +66,12 @@ void set_energy_perf_pref(u8 pref);
  */
 void enable_energy_perf_pref(void);
 
+/*
+ * Check if Total Memory Encryption (TME) is supported by the CPU
+ *
+ * coreboot shall detect the existence of TME feature by running CPUID instruction:
+ * CPUID leaf 7/sub-leaf 0: Return Value in ECX [bit 13] = 1
+ */
+bool is_tme_supported(void);
+
 #endif

src/cpu/intel/common/common_init.c

@@ -14,6 +14,9 @@
 #define  CPUID_6_ENGERY_PERF_PREF	(1 << 10)
 #define  CPUID_6_HWP			(1 << 7)
 
+/* Structured Extended Feature Flags */
+#define CPUID_EXT_FEATURE_TME_SUPPORTED (1 << 13)
+
 void set_vmx_and_lock(void)
 {
 	set_feature_ctrl_vmx();
@@ -227,3 +230,11 @@ void set_energy_perf_pref(u8 pref)
 	msr_unset_and_set(IA32_HWP_REQUEST, IA32_HWP_REQUEST_EPP_MASK,
 		(uint64_t)pref << IA32_HWP_REQUEST_EPP_SHIFT);
 }
+
+bool is_tme_supported(void)
+{
+	struct cpuid_result cpuid_regs;
+
+	cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0);
+	return (cpuid_regs.ecx & CPUID_EXT_FEATURE_TME_SUPPORTED);
+}