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intel/haswell: Drop MONOTONIC_TIMER_MSR

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The variable was set on all haswell boards, so we can do it like on
broadwell where the MSR based timer is assumed to be around, too.

Change-Id: Id48ad7454d4cf83c3b1616b64687cdcfee4baa10
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/10256
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Patrick Georgi
2015-05-19 21:30:20 +02:00
committed by Patrick Georgi
parent e2b0affd6c
commit a6b4798ac0
8 changed files with 3 additions and 15 deletions
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4
src/cpu/intel/haswell/Makefile.inc
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@@ -6,7 +6,7 @@ romstage-y += tsc_freq.c
ramstage-y += acpi.c
ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c
ramstage-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
ramstage-y += monotonic_timer.c
romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
@@ -14,7 +14,7 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
smm-$(CONFIG_MONOTONIC_TIMER_MSR) += monotonic_timer.c
smm-y += monotonic_timer.c
cpu_incs += $(src)/cpu/intel/haswell/cache_as_ram.inc