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AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS

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Following boards use cimx/sb700:
  amd/dinar
  supermicro/h8qgi
  supermicro/h8scm
  tyan/s8226

Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).

Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.

I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.

Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5539
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Kyösti Mälkki
2014-04-16 09:43:40 +03:00
parent 35546deba6
commit a6c525a7d5
13 changed files with 41 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
src/southbridge/amd/cimx/sb700/late.c
View File

@@ -218,22 +218,15 @@ static void sb700_enable(device_t dev)
case (0x14 << 3) | 0: /* 0:14:0 SMBUS */
{
#if 1
u32 ioapic_base;
printk(BIOS_DEBUG, "sm_init().\n");
ioapic_base = IO_APIC_ADDR;
clear_ioapic(ioapic_base);
/* I/O APIC IDs are normally limited to 4-bits. Enforce this limit. */
#if (CONFIG_APIC_ID_OFFSET == 0 && CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS >= 1)
/* Assign the ioapic ID the next available number after the processor core local APIC IDs */
setup_ioapic(ioapic_base, (UINT8) (CONFIG_MAX_CPUS * CONFIG_MAX_PHYSICAL_CPUS));
#elif (CONFIG_APIC_ID_OFFSET > 0)
/* Assign the ioapic ID the value 0. Processor APIC IDs follow. */
setup_ioapic(ioapic_base, 0);
#else
#error "The processor APIC IDs must be lifted to make room for the I/O APIC ID"
#endif
#endif
if (CONFIG_MAX_CPUS >= 16)
setup_ioapic(ioapic_base, 0);
else
setup_ioapic(ioapic_base, CONFIG_MAX_CPUS + 1);
}
break;