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soc/intel/skylake: Implement GPIO ACPI AML generating functions

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Implement GPIO ACPI AML generating functions that can be called by
coreboot drivers to generate GPIO manipulation code in AML. Following
API functions are implemented:

1. acpigen_soc_read_rx_gpio
2. acpigen_soc_get_tx_gpio
3. acpigen_soc_set_tx_gpio
4. acpigen_soc_clear_tx_gpio

In addition to the API functions above, helper functions are added to
gpio.asl to set/clear/get Tx value of GPIO.

BUG=b:62028489

Change-Id: I77e5d0decd8929a922d06b02312378f092551667
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19828
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh
2017-05-23 11:53:47 -07:00
committed by Martin Roth
parent d635506fa7
commit a6f0b2754b
2 changed files with 82 additions and 1 deletions
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46
src/soc/intel/skylake/acpi/gpio.asl
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@@ -120,7 +120,7 @@ Method (GADD, 1, NotSerialized)
}
/*
* Get GPIO Value
* Get GPIO Rx Value
* Arg0 - GPIO Number
*/
Method (GRXS, 1, Serialized)
@@ -134,3 +134,47 @@ Method (GRXS, 1, Serialized)
Return (Local0)
}
/*
* Get GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (GTXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (GPIOTXSTATE_MASK, ShiftRight (VAL0, GPIOTXSTATE_SHIFT), Local0)
Return (Local0)
}
/*
* Set GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (STXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
Or (GPIOTXSTATE_MASK, VAL0, VAL0)
}
/*
* Clear GPIO Tx Value
* Arg0 - GPIO Number
*/
Method (CTXS, 1, Serialized)
{
OperationRegion (PREG, SystemMemory, GADD (Arg0), 4)
Field (PREG, AnyAcc, NoLock, Preserve)
{
VAL0, 32
}
And (Not (GPIOTXSTATE_MASK), VAL0, VAL0)
}