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Add support for Google Parrot Chromebook

Browse Source 
AKA Acer C7 Chromebook

See http://www.google.com/intl/en/chrome/devices/acer-c7-chromebook.html
for more information. Thank you to Sage Electronic Engineering, LLC for
making this possible! http://www.se-eng.com/

Change-Id: Ic4e4d50045a82cbb82e1dea3cd5a04525a648612
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2026
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Stefan Reinauer
2012-12-11 16:00:47 -08:00
committed by Ronald G. Minnich
parent 0e81b62638
commit a7198b34cc
27 changed files with 3012 additions and 0 deletions
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105
src/mainboard/google/parrot/devicetree.cb Normal file
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chip northbridge/intel/sandybridge
# Enable DisplayPort B Hotplug with 6ms pulse
register "gpu_dp_b_hotplug" = "0x06"
# Enable Panel as eDP and configure power delays
register "gpu_panel_port_select" = "0" # LVDS
register "gpu_panel_power_cycle_delay" = "5" # 400ms
register "gpu_panel_power_up_delay" = "500" # 50ms
register "gpu_panel_power_down_delay" = "150" # 15ms
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
# Set backlight PWM values
register "gpu_cpu_backlight" = "0x000001d4"
register "gpu_pch_backlight" = "0x03aa0000"
device lapic_cluster 0 on
chip cpu/intel/socket_rPGA989
device lapic 0 on end
end
chip cpu/intel/model_206ax
# Magic APIC ID to locate this chip
device lapic 0xACAC off end
# Coordinate with HW_ALL
register "pstate_coord_type" = "0xfe"
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
end
end
device pci_domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "pirqa_routing" = "0x8b"
register "pirqb_routing" = "0x8a"
register "pirqc_routing" = "0x8b"
register "pirqd_routing" = "0x8b"
register "pirqe_routing" = "0x8b"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# GPI routing
# 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
# 2 SCI (if corresponding GPIO_EN bit is also set)
# Set Lid Switch to SMI to capture in recovery mode. It gets reset to
# SCI mode when we go to ACPI mode.
register "alt_gp_smi_en" = "0x8100"
register "gpi7_routing" = "2"
register "gpi8_routing" = "1"
register "gpi15_routing" = "1" #lid switch gpe
register "ide_legacy_combined" = "0x0"
register "sata_ahci" = "0x1"
register "sata_port_map" = "0x1"
# EC range is 0xFD60 (EC_IO) and 0x68/0x6C
register "gen1_dec" = "0x0004fd61"
register "gen2_dec" = "0x00040069"
# Enable zero-based linear PCIe root port functions
register "pcie_port_coalesce" = "1"
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 19.0 off end # Intel Gigabit Ethernet
device pci 1a.0 on end # USB2 EHCI #2
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.1 on end # PCIe Port #2 (WLAN)
device pci 1c.2 on end # PCIe Port #3 (ETH0)
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1c.6 off end # PCIe Port #7
device pci 1c.7 off end # PCIe Port #8
device pci 1d.0 on end # USB2 EHCI #1
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip ec/compal/ene932
# 60/64 KBC
device pnp ff.1 on # dummy address
end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller 1
device pci 1f.3 on end # SMBus
device pci 1f.5 off end # SATA Controller 2
device pci 1f.6 on end # Thermal
end
end
end