soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary: * Don't relocate the FSP binary image * Copy the FSP binary into ESRAM * Specify Kconfig values to easily debug ESRAM and TempRamInit code * Specify the FSP binary file location * Specify the FSP binary image ID * Specify where in the flash image the FSP image must reside * Specify the FSP data file location * Specify where to place the FSP data file in the flash image * Specify where in the ESRAM the FSP image must reside Test 1 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Add "select ENABLE_DEBUG_LED_FINDFSP" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Test 2 on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Remove "select ENABLE_DEBUG_LED_FINDFSP" * Add "select ENABLE_DEBUG_LED_TEMPRAMINIT" * Testing is successful if the SD LED is on indicating that the FSP.bin file was properly located, The test fails if the SD LED is flashing. Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13443 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Lee Leahy
Leroy P Leahy
parent
9fd0895cb4
commit
a7ba56e3ce
@ -28,6 +28,42 @@ config CPU_SPECIFIC_OPTIONS
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select ARCH_VERSTAGE_X86_32
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select ARCH_VERSTAGE_X86_32
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select USE_MARCH_586
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select USE_MARCH_586
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#####
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# Debug support
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# The following options provide debug support for the Quark coreboot
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# code. The SD LED is used as a binary marker to determine if a
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# specific point in the execution flow has been reached.
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#####
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config ENABLE_DEBUG_LED
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bool
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default n
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help
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Enable the use of the SD LED for early debugging before serial output
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is available. Setting this LED indicates that control has reached the
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desired check point.
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config ENABLE_DEBUG_LED_ESRAM
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bool "SD LED indicates ESRAM initialized"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that ESRAM has been successfully initialized.
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config ENABLE_DEBUG_LED_FINDFSP
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bool "SD LED indicates fsp.bin file was found"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that fsp.bin was found.
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config ENABLE_DEBUG_LED_TEMPRAMINIT
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bool "SD LED indicates TempRamInit was successful"
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default n
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select ENABLE_DEBUG_LED
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help
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Indicate that TempRamInit was successful.
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#####
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#####
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# Flash layout
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# Flash layout
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# Specify the size of the coreboot file system in the read-only
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# Specify the size of the coreboot file system in the read-only
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@ -44,6 +80,88 @@ config CBFS_SIZE
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- The chipset microcode (RMU) binary file located at 0xFFF00000
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- The chipset microcode (RMU) binary file located at 0xFFF00000
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- Intel Trusted Execution Engine firmware
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- Intel Trusted Execution Engine firmware
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#####
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# FSP binary
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# The following options control the FSP binary file placement in
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# the flash image and ESRAM. This file is required by the Quark
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# SoC code to boot coreboot and its payload.
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#####
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config ADD_FSP_RAW_BIN
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bool "Add the Intel FSP binary to the flash image without relocation"
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default n
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depends on PLATFORM_USES_FSP1_1
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help
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Select this option to add an Intel FSP binary to
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the resulting coreboot image.
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Note: Without this binary, coreboot builds relying on the FSP
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will not boot
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config FSP_FILE
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string "Intel FSP binary path and filename"
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default "3rdparty/blobs/soc/intel/quark/fsp.bin"
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depends on PLATFORM_USES_FSP1_1
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depends on ADD_FSP_RAW_BIN
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help
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The path and filename of the Intel FSP binary for this platform.
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config FSP_IMAGE_ID_STRING
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string "8 byte platform string identifying the FSP platform"
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default "QUK-FSP0"
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depends on PLATFORM_USES_FSP1_1
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help
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8 ASCII character byte signature string that will help match the FSP
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binary to a supported hardware configuration.
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config FSP_LOC
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hex
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default 0xfff80000
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depends on PLATFORM_USES_FSP1_1
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help
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The location in CBFS that the FSP is located. This must match the
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value that is set in the FSP binary. If the FSP needs to be moved,
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rebase the FSP with Intel's BCT (tool).
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config FSP_ESRAM_LOC
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hex
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default 0x80000000
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depends on PLATFORM_USES_FSP1_1
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help
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The location in ESRAM where a copy of the FSP binary is placed.
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#####
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# FSP PDAT binary
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# The following options control the FSP platform data binary
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# file placement in the flash image.
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#####
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config ADD_FSP_PDAT_FILE
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bool "Should the PDAT binary be added to the flash image?"
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default n
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depends on PLATFORM_USES_FSP1_1
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help
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The PDAT file is required for the FSP 1.1 binary
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config FSP_PDAT_FILE
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string
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default "3rdparty/blobs/soc/intel/quark/pdat.bin"
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depends on PLATFORM_USES_FSP1_1
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depends on ADD_FSP_PDAT_FILE
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help
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The path and filename of the Intel Galileo platform-data-patch (PDAT)
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binary. This binary file is generated by the platform-data-patch.py
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script released with the Quark BSP and contains the Ethernet address.
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config FSP_PDAT_LOC
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hex
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default 0xfff10000
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depends on PLATFORM_USES_FSP1_1
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depends on ADD_FSP_PDAT_FILE
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help
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The location in CBFS that the PDAT is located. It must match the
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PCD PcdPlatformDataBaseAddress of Quark SoC FSP.
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#####
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#####
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# RMU binary
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# RMU binary
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# The following options control the Quark chipset microcode file
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# The following options control the Quark chipset microcode file
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@ -27,6 +27,18 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include
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# Chipset microcode path
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# Chipset microcode path
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
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# Add the FSP binary to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
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fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
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fsp.bin-position := $(CONFIG_FSP_LOC)
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fsp.bin-type := raw
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# Add the platform data file to the CBFS image
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cbfs-files-$(CONFIG_ADD_FSP_PDAT_FILE) += pdat.bin
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pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE))
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pdat.bin-position := $(CONFIG_FSP_PDAT_LOC)
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pdat.bin-type := raw
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# Add the chipset microcode file to the CBFS image
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# Add the chipset microcode file to the CBFS image
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE))
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@ -14,3 +14,4 @@
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#
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#
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cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
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cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
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cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
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206
src/soc/intel/quark/romstage/cache_as_ram.inc
Normal file
206
src/soc/intel/quark/romstage/cache_as_ram.inc
Normal file
@ -0,0 +1,206 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
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* Copyright (C) 2015-2016 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Replacement for cache_as_ram.inc when using the FSP binary. This code
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* locates the FSP binary, initializes the cache as RAM and performs the
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* first stage of initialization. Next this code switches the stack from
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* the cache to RAM and then disables the cache as RAM. Finally this code
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* performs the final stage of initialization.
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*/
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#include <rules.h>
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/*
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* eax: BIST value
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*/
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movl %eax, %edi
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cache_as_ram:
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post_code(0x20)
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/*
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* edi: BIST value
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*/
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/*
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* Find the FSP binary in cbfs.
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* Make a fake stack that has the return value back to this code.
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*/
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lea fake_fsp_stack, %esp
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jmp find_fsp
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find_fsp_ret:
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/* Save the FSP location */
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mov %eax, %ebp
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/*
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* Only when a valid FSP binary is found at CONFIG_FSP_LOC is
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* the returned FSP_INFO_HEADER structure address above the base
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* address of FSP binary specified by the CONFIG_FSP_LOC value.
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* All of the error values are in the 0x8xxxxxxx range which are
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* below the CONFIG_FSP_LOC value.
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*/
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cmp $CONFIG_FSP_ESRAM_LOC, %eax
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jbe halt1
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post_code(POST_FSP_TEMP_RAM_INIT)
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#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
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movl $SD_HOST_CTRL, %ebx
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movb 0(%ebx), %al
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orb $1, %al
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movb %al, 0(%ebx)
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jmp .
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#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
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/* Calculate entry into FSP */
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mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
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add 0x1c(%ebp), %eax /* add in the offset for FSP */
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/*
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* Pass early init variables on a fake stack (no memory yet)
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* as well as the return location
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*/
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lea CAR_init_stack, %esp
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/*
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* BIST value is zero
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* eax: TempRamInitApi address
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* ebp: FSP_INFO_HEADER address
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* edi: BIST value
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* esi: Not used
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*/
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/* call FSP binary to setup temporary stack */
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jmp *%eax
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CAR_init_done:
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addl $4, %esp
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/*
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* ebp: FSP_INFO_HEADER address
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* ecx: Temp RAM base
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* edx: Temp RAM top
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* edi: BIST value
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*/
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cmp $0, %eax
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jne halt2
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#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
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movl %edx, %esi
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movl $SD_HOST_CTRL, %ebx
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movb 0(%ebx), %al
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orb $1, %al
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movb %al, 0(%ebx)
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movl %esi, %edx
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jmp .
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#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
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/* Set up bootloader stack */
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clrl %eax
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jmp .Lhlt
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halt1:
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/*
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* Failures for postcode 0xBA - failed in fsp_fih_early_find()
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*
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* Values are:
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* 0x01 - FV signature, "_FVH" not present
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* 0x02 - FFS GUID not present
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* 0x03 - FSP INFO Header not found
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* 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
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* a different location, or does it need to be?
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* 0x05 - FSP INFO Header signature "FSPH" not found
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* 0x06 - FSP Image ID is not the expected ID.
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*/
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movb $0xBA, %ah
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jmp .Lhlt
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halt2:
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/*
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* Failures for postcode 0xBB - failed in the FSP:
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*
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* 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
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* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
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* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
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* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
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* 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
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* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
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*/
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movb $0xBB, %ah
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jmp .Lhlt
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#----------------------------------------------------------------------------
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#
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# Procedure: .Lhlt
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#
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# Input: ah - Upper 8-bits of POST code
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# al - Lower 8-bits of POST code
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#
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# Description:
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# Infinite loop displaying alternating POST code values
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#
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#----------------------------------------------------------------------------
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#define FLASH_DELAY 0x1000 /* I/O delay between post codes on failure */
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#define POST_DELAY 0x50
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.Lhlt:
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xchg %al, %ah
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mov $POST_DELAY, %dh
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#if IS_ENABLED(CONFIG_POST_IO)
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outb %al, $CONFIG_POST_IO_PORT
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#else
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post_code(POST_DEAD_CODE)
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#endif
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.flash_setup:
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movl $FLASH_DELAY, %ecx
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.flash_delay:
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outb %al, $0xED
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loop .flash_delay
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#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
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movl $SD_HOST_CTRL, %ebx
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movb 0(%ebx), %dl
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xorb $1, %dl
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movb %dl, 0(%ebx)
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#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
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decb %dh
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jnz .flash_setup
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jmp .Lhlt
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/*
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* esp is set to this location so that the call into and return from the FSP
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* in find_fsp will work.
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*/
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.align 4
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fake_fsp_stack:
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.long find_fsp_ret
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.long CONFIG_FSP_ESRAM_LOC /* FSP base address */
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CAR_init_params:
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.long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
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||||||
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.long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
|
||||||
|
.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
|
||||||
|
.long CONFIG_ROM_SIZE /* Total Firmware Length */
|
||||||
|
|
||||||
|
CAR_init_stack:
|
||||||
|
.long CAR_init_done
|
||||||
|
.long CAR_init_params
|
||||||
@ -452,6 +452,21 @@ stackless_PCIConfig_Read:
|
|||||||
|
|
||||||
esram_init_done:
|
esram_init_done:
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
|
||||||
|
|
||||||
|
/* Copy FSP image to eSRAM and call it. */
|
||||||
|
/* TODO: FSP location/size could be got in a routine. */
|
||||||
|
cld
|
||||||
|
movl $(0x00040000), %ecx /* 256K DWORDs = 64K */
|
||||||
|
shrl $2, %ecx
|
||||||
|
movl $CONFIG_FSP_LOC, %esi /* The source address. */
|
||||||
|
movl $CONFIG_FSP_ESRAM_LOC, %edi /* FSP destination in ESRAM */
|
||||||
|
rep movsl
|
||||||
|
#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
|
||||||
|
|
||||||
|
#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
|
||||||
|
sd_led:
|
||||||
|
|
||||||
.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */
|
.equ SD_PFA, (0x14 << 11) /* B0:D20:F0 - SDIO controller */
|
||||||
.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
|
.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) /* SD cntrl base in PCI config space */
|
||||||
.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
|
.equ SD_CFG_CMD, (SD_CFG_BASE+0x04) /* Command reg in PCI config space */
|
||||||
@ -488,6 +503,7 @@ L43:
|
|||||||
jmp stackless_PCIConfig_Read
|
jmp stackless_PCIConfig_Read
|
||||||
|
|
||||||
L44:
|
L44:
|
||||||
|
#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
|
||||||
/* Turn on SD LED to indicate ESRAM successfully initialized */
|
/* Turn on SD LED to indicate ESRAM successfully initialized */
|
||||||
movl $SD_HOST_CTRL, %ebx
|
movl $SD_HOST_CTRL, %ebx
|
||||||
movb 0(%ebx), %al
|
movb 0(%ebx), %al
|
||||||
@ -496,3 +512,5 @@ L44:
|
|||||||
|
|
||||||
/* Loop forever */
|
/* Loop forever */
|
||||||
jmp .
|
jmp .
|
||||||
|
#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
|
||||||
|
#endif /* CONFIG_ENABLE_DEBUG_LED */
|
||||||
|
|||||||
Loading…
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Reference in New Issue
Block a user