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superio/ite: Add function to disable 3VSBSW# signal

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The 3VSBSW# signal can now also be disabled again which is necessary to
power components down properly in SMM when entering S5. In such cases
the signal will be enabled only in the SMM S3 handler.

Change-Id: I8535176908ec39e9916774135e028cbc7c203474
Signed-off-by: Joel Linn <jl@conductive.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81588
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Joel Linn
2024-03-26 18:35:15 +01:00
committed by Nico Huber
parent 9905d1f8a8
commit a7c96155b9
3 changed files with 15 additions and 3 deletions
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8
src/superio/ite/common/early_serial.c
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@@ -75,6 +75,7 @@ void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
*
* LDN 7, reg 0x2a - needed for S3, or memory power will be cut off
* this was documented only in IT8712F_V0.9.2!
* Also documented in IT8728F_V0.4.2 and IT8772E_V0.4
*
* Enable 3VSBSW#. (For System Suspend-to-RAM)
* 0: 3VSBSW# will be always inactive.
@@ -85,13 +86,16 @@ void ite_enable_serial(pnp_devfn_t dev, u16 iobase)
* and pass: GPIO_DEV
*/
void ite_enable_3vsbsw(pnp_devfn_t dev)
void ite_set_3vsbsw(pnp_devfn_t dev, bool enable)
{
u8 tmp;
pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
tmp = pnp_read_config(dev, ITE_CONFIG_REG_MFC);
tmp |= 0x80;
if (enable)
tmp |= 0x80;
else
tmp &= ~0x80;
pnp_write_config(dev, ITE_CONFIG_REG_MFC, tmp);
pnp_exit_conf_state(dev);
}