sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/i945/early_init.c: Correct the PEG_LC address of DEV(0:01.0)

Browse Source 
This bug/typo was spoted by Felix Held.
As documented in the datasheet, to enable PMEGPE, HPGPE, GENGPE, we need
to write 0x7 into DEV(0:01.0) register "PCI Express-G Legacy Control"
located at 0xec.
Used address at 0x114 to enable GPEs is likely a typo.

Patch not tested.

Change-Id: Iee1c1e4b7fef21608f2678a1d4104b668a66a7e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/27307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Elyes HAOUAS
2018-11-24 09:31:10 +01:00
committed by Felix Held
parent 48fa9225ca
commit a9068aa4e0
1 changed files with 1 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/northbridge/intel/i945/early_init.c
View File

@@ -701,7 +701,7 @@ static void i945_setup_pci_express_x16(void)
/* Enable GPEs */
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xec);
reg32 |= (1 << 2) | (1 << 1) | (1 << 0); /* PMEGPE, HPGPE, GENGPE */
pci_write_config32(PCI_DEV(0, 0x01, 0), 0x114, reg32);
pci_write_config32(PCI_DEV(0, 0x01, 0), 0xec, reg32);
/* Virtual Channel Configuration: Only VC0 on PCIe x16 */
reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0x114);