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baytrail: Fix XHCI problems and re-enable

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- a few clock gating bits were set improperly and were preventing
the system from transitioning out of S0 state.
- the XHCC registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control.  This was causing memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver

Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4933
Tested-by: build bot (Jenkins)
This commit is contained in:
Duncan Laurie
2013-11-04 11:22:27 -08:00
committed by Aaron Durbin
parent 8199809079
commit a90a59f5a3
2 changed files with 9 additions and 6 deletions
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4
src/mainboard/google/rambi/devicetree.cb
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@@ -5,8 +5,8 @@ chip soc/intel/baytrail
register "sata_ahci" = "0x1"
register "ide_legacy_combined" = "0x0"
# Route USB ports to XHCI -- DISABLED UNTIL XHCI WORKS
register "usb_route_to_xhci" = "0"
# Route USB ports to XHCI
register "usb_route_to_xhci" = "1"
# USB Port Disable Mask
register "usb2_port_disable_mask" = "0x0"