src: Replace common MSR addresses with macros

Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>

src/cpu/amd/microcode/microcode.c

@@ -127,7 +127,7 @@ static void apply_microcode_patch(const struct microcode *m)
 	UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
 
 	/* read the patch_id again */
-	msr = rdmsr(0x8b);
+	msr = rdmsr(IA32_BIOS_SIGN_ID);
 	new_patch_id = msr.lo;
 
 	UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id,

src/cpu/x86/lapic/boot_cpu.c

@@ -13,13 +13,14 @@
 
 #include <smp/node.h>
 #include <cpu/x86/msr.h>
+#include <cpu/x86/lapic_def.h>
 
 #if IS_ENABLED(CONFIG_SMP)
 int boot_cpu(void)
 {
 	int bsp;
 	msr_t msr;
-	msr = rdmsr(0x1b);
+	msr = rdmsr(LAPIC_BASE_MSR);
 	bsp = !!(msr.lo & (1 << 8));
 	return bsp;
 }

src/cpu/x86/smm/smmhandler.S

@@ -21,7 +21,7 @@
  * to 64k if we can though.
  */
 
-#define LAPIC_BASE_MSR 0x1b
+#include <cpu/x86/lapic_def.h>
 
 /*
  * +--------------------------------+ 0xaffff
@@ -49,8 +49,6 @@
  *
  */
 
-#define LAPIC_ID 0xfee00020
-
 /* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
  * at which smm_handler_start lives. At the moment the handler
  * lives right at 0xa0000, so the offset is 0.
@@ -134,7 +132,7 @@ untampered_lapic:
 	movw    %ax, %gs
 
 	/* Get this CPU's LAPIC ID */
-	movl $LAPIC_ID, %esi
+	movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi
 	movl (%esi), %ecx
 	shr  $24, %ecx