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cpu/allwinner/a10: Add function for reading chip revision

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Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4596
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Alexandru Gagniuc
2014-01-02 01:57:53 -05:00
parent bd09dbe330
commit a94bed0116
2 changed files with 20 additions and 0 deletions
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11
src/cpu/allwinner/a10/timer.c
View File

@@ -11,6 +11,7 @@
#include <delay.h> #include <delay.h>
#include <timer.h> #include <timer.h>
struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE;
struct a1x_timer *const tmr0 = struct a1x_timer *const tmr0 =
&((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0]; &((struct a1x_timer_module *)A1X_TIMER_BASE)->timer[0];
@@ -53,3 +54,13 @@ void udelay(unsigned usec)
} }
} }
/*
* This function has nothing to do with timers; however, the chip revision
* register is in the timer module, so keep this function here.
*/
u8 a1x_get_cpu_chip_revision(void)
{
write32(0, &timer_module->cpu_cfg);
return (read32(&timer_module->cpu_cfg) >> 6) & 0x3;
}

9
src/cpu/allwinner/a10/timer.h
View File

@@ -24,6 +24,13 @@
#define TIMER_CTRL_RELOAD (1 << 1) #define TIMER_CTRL_RELOAD (1 << 1)
#define TIMER_CTRL_TMR_EN (1 << 0) #define TIMER_CTRL_TMR_EN (1 << 0)
/* Chip revision definitions (found in CPU_CFG register) */
#define A1X_CHIP_REV_A 0x0
#define A1X_CHIP_REV_C1 0x1
#define A1X_CHIP_REV_C2 0x2
#define A1X_CHIP_REV_B 0x3
/* General purpose timer */ /* General purpose timer */
struct a1x_timer { struct a1x_timer {
u32 ctrl; u32 ctrl;
@@ -87,4 +94,6 @@ struct a1x_timer_module {
u32 cpu_cfg; u32 cpu_cfg;
} __attribute__ ((packed)); } __attribute__ ((packed));
u8 a1x_get_cpu_chip_revision(void);
#endif /* CPU_ALLWINNER_A10_TIMER_H */ #endif /* CPU_ALLWINNER_A10_TIMER_H */