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vendorcode/mt8192: devapc: fix register offset for PCIe domain

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Correct the wrong offset for setting PCIe domain.

Change-Id: I9de2bdf5a0a4fb5b34985b11976fd50b397e97ba
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51512
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nina Wu
2021-03-16 14:29:12 +08:00
committed by Hung-Te Lin
parent 5358467638
commit a94fea1ee4
1 changed files with 1 additions and 1 deletions
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src/soc/mediatek/mt8192/devapc.c
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@@ -13,7 +13,7 @@ static void infra_master_init(uintptr_t base)
SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1); SET32_BITFIELDS(getreg(base, MAS_SEC_0), SCP_SSPM_SEC, 1, CPU_EB_SEC, 1);
/* Domain */ /* Domain */
SET32_BITFIELDS(getreg(base, MAS_SEC_0), PCIE_DOM, MAS_DOMAIN_1); SET32_BITFIELDS(getreg(base, MAS_DOM_0), PCIE_DOM, MAS_DOMAIN_1);
SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2, SET32_BITFIELDS(getreg(base, MAS_DOM_1), SCP_SSPM_DOM, MAS_DOMAIN_2,
CPU_EB_DOM, MAS_DOMAIN_2); CPU_EB_DOM, MAS_DOMAIN_2);