Move definitions of HIGH_MEMORY_SAVE

This is more of ACPI S3 resume and x86 definition than CBMEM.

Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15190
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/arch/x86/include/arch/acpi.h

@@ -24,6 +24,14 @@
 #ifndef __ASM_ACPI_H
 #define __ASM_ACPI_H
 
+#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
+	! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)
+#define HIGH_MEMORY_SAVE	(CONFIG_RAMTOP - CONFIG_RAMBASE)
+#else
+#define HIGH_MEMORY_SAVE	0
+#endif
+
+#ifndef __ASSEMBLER__
 #include <stdint.h>
 #include <rules.h>
 #include <commonlib/helpers.h>
@@ -643,4 +651,6 @@ static inline uintptr_t acpi_align_current(uintptr_t current)
 	return ALIGN(current, 16);
 }
 
+#endif  /* __ASSEMBLER__ */
+
 #endif  /* __ASM_ACPI_H */

src/cpu/amd/agesa/s3_resume.c

@@ -13,6 +13,7 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/acpi.h>
 #include <console/console.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>

src/cpu/intel/haswell/romstage.c

@@ -24,6 +24,7 @@
 #include <halt.h>
 #include <lib.h>
 #include <timestamp.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <arch/stages.h>
 #include <device/pci_def.h>

src/cpu/intel/model_206ax/cache_as_ram.inc

@@ -18,6 +18,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/post_code.h>
 #include <cbmem.h>
+#include <arch/acpi.h>
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE

src/include/cbmem.h

@@ -19,14 +19,6 @@
 
 #include <commonlib/cbmem_id.h>
 #include <rules.h>
-
-#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \
-	! IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)
-#define HIGH_MEMORY_SAVE	(CONFIG_RAMTOP - CONFIG_RAMBASE)
-#else
-#define HIGH_MEMORY_SAVE	0
-#endif
-
 /* Delegation of resume backup memory so we don't have to
  * (slowly) handle backing up OS memory in romstage.c
  */

src/mainboard/lenovo/t400/romstage.c

@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <arch/acpi.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>

src/mainboard/lenovo/x200/romstage.c

@@ -19,6 +19,7 @@
 #include <stdint.h>
 #include <string.h>
 #include <arch/io.h>
+#include <arch/acpi.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/tsc.h>

src/northbridge/intel/i945/early_init.c

@@ -16,6 +16,7 @@
 #include <stdint.h>
 #include <stdlib.h>
 #include <console/console.h>
+#include <arch/acpi.h>
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <cbmem.h>

src/northbridge/intel/sandybridge/early_init.c

@@ -18,6 +18,7 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <arch/io.h>
+#include <arch/acpi.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <cbmem.h>