soc/intel: Clean mess around UART_DEBUG

Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.

As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.

Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>

src/soc/intel/apollolake/Kconfig

@@ -169,14 +169,6 @@ config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
 	default 133
 
-config UART_DEBUG
-	bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
-	default n
-	select CONSOLE_SERIAL
-	select DRIVERS_UART
-	select DRIVERS_UART_8250MEM_32
-	select NO_UART_ON_SUPERIO
-
 # 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB.
 config C_ENV_BOOTBLOCK_SIZE
 	hex

src/soc/intel/apollolake/Makefile.inc

@@ -18,14 +18,14 @@ bootblock-y += lpc.c
 bootblock-y += mmap_boot.c
 bootblock-y += pmutil.c
 bootblock-y += spi.c
-bootblock-$(CONFIG_UART_DEBUG) += uart.c
+bootblock-y += uart.c
 
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += gspi.c
 romstage-y += heci.c
 romstage-y += i2c.c
-romstage-$(CONFIG_UART_DEBUG) += uart.c
+romstage-y += uart.c
 romstage-y += memmap.c
 romstage-y += meminit.c
 ifeq ($(CONFIG_SOC_INTEL_GLK),y)
@@ -42,7 +42,7 @@ smm-y += mmap_boot.c
 smm-y += pmutil.c
 smm-y += smihandler.c
 smm-y += spi.c
-smm-$(CONFIG_UART_DEBUG) += uart.c
+smm-y += uart.c
 smm-y += elog.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
@@ -57,7 +57,7 @@ ramstage-y += i2c.c
 ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += mmap_boot.c
-ramstage-$(CONFIG_UART_DEBUG) += uart.c
+ramstage-y += uart.c
 ramstage-y += nhlt.c
 ramstage-y += spi.c
 ramstage-y += systemagent.c
@@ -74,7 +74,7 @@ postcar-y += spi.c
 postcar-y += i2c.c
 postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
 postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
-postcar-$(CONFIG_UART_DEBUG) += uart.c
+postcar-y += uart.c
 postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
 
 verstage-y += car.c
@@ -83,7 +83,7 @@ verstage-y += gspi.c
 verstage-y += heci.c
 verstage-y += memmap.c
 verstage-y += mmap_boot.c
-verstage-$(CONFIG_UART_DEBUG) += uart.c
+verstage-y += uart.c
 verstage-y += pmutil.c
 verstage-y += reset.c
 verstage-y += spi.c

src/soc/intel/apollolake/bootblock/bootblock.c

@@ -95,7 +95,7 @@ void bootblock_soc_early_init(void)
 	pmc_global_reset_enable(0);
 
 	/* Prepare UART for serial console. */
-	if (IS_ENABLED(CONFIG_UART_DEBUG))
+	if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE))
 		uart_bootblock_init();
 
 	if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI))

src/soc/intel/apollolake/cse.c

@@ -222,7 +222,7 @@ static void dump_cse_version(void *unused)
 	 * Print ME version only if UART debugging is enabled. Else, it takes
 	 * ~0.6 second to talk to ME and get this information.
 	 */
-	if (!IS_ENABLED(CONFIG_UART_DEBUG))
+	if (!IS_ENABLED(CONFIG_CONSOLE_SERIAL))
 		return;
 
 	msg.mkhi_hdr.fields.group_id = MKHI_GROUP_ID_GEN;

src/soc/intel/apollolake/romstage.c

@@ -278,7 +278,7 @@ asmlinkage void car_stage_entry(void)
 static void fill_console_params(FSPM_UPD *mupd)
 {
 	if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) {
-		if (IS_ENABLED(CONFIG_UART_DEBUG)) {
+		if (IS_ENABLED(CONFIG_INTEL_LPSS_UART_FOR_CONSOLE)) {
 			mupd->FspmConfig.SerialDebugPortDevice =
 					CONFIG_UART_FOR_CONSOLE;
 			/* use MMIO port type */