soc/intel/alderlake: rename CONFIG_MAX_PCIE_CLOCKS to CONFIG_MAX_PCIE_CLOCK_SRC

CONFIG_MAX_PCIE_CLOCKS renamed to MAX_PCIE_CLOCK_SRC to make it clear that this config
is for the number of PCIe Clock sources available which is different from PCIe clock reqs.
This is more relevant in alderlake, as the number clock source and clock reqs differ.
However since this is a better name, renaming it throughout the soc/intel tree.

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I747c94331b68c4ec0b6b5a04149856a4bb384829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/elkhartlake/chip.h

@@ -108,10 +108,10 @@ struct soc_intel_elkhartlake_config {
 	/* PCIe output clocks type to PCIe devices.
 	 * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
 	 * 0xFF: not used */
-	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
 	/* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
 	 * clksrc. */
-	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
 
 	/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
 	uint8_t PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS];