soc/intel/alderlake: Skip FSP Notify API (post PCI enumeration)

Alder Lake SoC deselects USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM Kconfig
to skip FSP notify API (Post PCI Enumeration) and make use of native
coreboot driver to perform SoC recommended operations prior booting to
payload/OS.

BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects required configs.
[INFO ]  coreboot skipped calling FSP notify phase: 00000020.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46f6ca791fb60b417d205d0a54705f3481deebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>

src/soc/intel/alderlake/Kconfig

@@ -118,7 +118,6 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202005_BINDING
-	select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
 
 config ALDERLAKE_CONFIGURE_DESCRIPTOR
 	bool