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mb/google/brask/var/bujia: Add wireless and memory thermal sensor

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Bujia has 4 thermal sensors, so add two missing sensors settings.

BUG=b:351917517
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot.
      check ACPI SSDT table have new TSR info.
      $ cat /sys/firmware/acpi/tables/SSDT > SSDT
      $ iasl -d SSDT
      check SSDT.dsl

Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Shon Wang
2024-07-02 16:47:53 +08:00
committed by Felix Held
parent a6a5ae0eaa
commit a9997f891f
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/brya/variants/bujia/overridetree.cb
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@@ -65,6 +65,8 @@ chip soc/intel/alderlake
## sensor information
register "options.tsr[0].desc" = ""DRAM""
register "options.tsr[1].desc" = ""Charger""
register "options.tsr[2].desc" = ""Wireless""
register "options.tsr[3].desc" = ""Memory""
# TODO: below values are initial reference values only
## Active Policy
@@ -84,6 +86,8 @@ chip soc/intel/alderlake
[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000),
[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000),
[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 75, 5000),
[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 75, 5000),
}"
## Critical Policy