mb/google/hatch: Create Akemi variant
This is based on the hatch variant BUG=b:138879565 TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp chromeos-bootimage look for image-akemi.*.bin generated under the /build/hatch/firmware/ Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Peichao Wang
Furquan Shaikh
parent
8699724a07
commit
aa3c0a5fad
@ -71,6 +71,7 @@ config FMDFILE
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config GBB_HWID
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config GBB_HWID
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string
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string
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depends on CHROMEOS
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depends on CHROMEOS
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default "AKEMI TEST 4326" if BOARD_GOOGLE_AKEMI
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default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
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default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
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default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS
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default "HELIOS TEST 0878" if BOARD_GOOGLE_HELIOS
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default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED
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default "KINDRED TEST 2636" if BOARD_GOOGLE_KINDRED
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@ -86,6 +87,7 @@ config MAINBOARD_FAMILY
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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string
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string
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default "Akemi" if BOARD_GOOGLE_AKEMI
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default "Hatch" if BOARD_GOOGLE_HATCH
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default "Hatch" if BOARD_GOOGLE_HATCH
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default "Helios" if BOARD_GOOGLE_HELIOS
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default "Helios" if BOARD_GOOGLE_HELIOS
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default "Kindred" if BOARD_GOOGLE_KINDRED
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default "Kindred" if BOARD_GOOGLE_KINDRED
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@ -109,6 +111,7 @@ config TPM_TIS_ACPI_INTERRUPT
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config VARIANT_DIR
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config VARIANT_DIR
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string
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string
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default "akemi" if BOARD_GOOGLE_AKEMI
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default "hatch" if BOARD_GOOGLE_HATCH
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default "hatch" if BOARD_GOOGLE_HATCH
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default "helios" if BOARD_GOOGLE_HELIOS
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default "helios" if BOARD_GOOGLE_HELIOS
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default "kindred" if BOARD_GOOGLE_KINDRED
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default "kindred" if BOARD_GOOGLE_KINDRED
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@ -1,5 +1,11 @@
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comment "Hatch"
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comment "Hatch"
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config BOARD_GOOGLE_AKEMI
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bool "-> Akemi"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_ROMSIZE_KB_16384
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select SOC_INTEL_COMETLAKE
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config BOARD_GOOGLE_HATCH
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config BOARD_GOOGLE_HATCH
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bool "-> Hatch"
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bool "-> Hatch"
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select BOARD_GOOGLE_BASEBOARD_HATCH
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select BOARD_GOOGLE_BASEBOARD_HATCH
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23
src/mainboard/google/hatch/variants/akemi/Makefile.inc
Normal file
23
src/mainboard/google/hatch/variants/akemi/Makefile.inc
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@ -0,0 +1,23 @@
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## This file is part of the coreboot project.
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##
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## Copyright 2019 Google LLC
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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SPD_SOURCES = 4G_2400 # 0b000
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SPD_SOURCES += empty_ddr4 # 0b001
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SPD_SOURCES += 8G_2400 # 0b010
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SPD_SOURCES += 8G_2666 # 0b011
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SPD_SOURCES += 16G_2400 # 0b100
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SPD_SOURCES += 16G_2666 # 0b101
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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161
src/mainboard/google/hatch/variants/akemi/gpio.c
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161
src/mainboard/google/hatch/variants/akemi/gpio.c
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@ -0,0 +1,161 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <baseboard/gpio.h>
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#include <baseboard/variants.h>
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#include <commonlib/helpers.h>
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#include <console/console.h>
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static const struct pad_config gpio_table[] = {
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/* A0 : NC */
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PAD_NC(GPP_A0, NONE),
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/* A6 : NC */
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PAD_NC(GPP_A6, NONE),
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/* A8 : NC */
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PAD_NC(GPP_A8, NONE),
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/* A10 : NC */
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PAD_NC(GPP_A10, NONE),
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/* A11 : NC */
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PAD_NC(GPP_A11, NONE),
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/* A12 : NC */
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PAD_NC(GPP_A12, NONE),
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/* A18 : NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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/* A22 : NC */
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PAD_NC(GPP_A22, NONE),
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/* A23 : NC */
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PAD_NC(GPP_A23, NONE),
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/* B20 : NC */
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PAD_NC(GPP_B20, NONE),
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/* B21 : NC */
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PAD_NC(GPP_B21, NONE),
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/* B22 : NC */
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PAD_NC(GPP_B22, NONE),
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/* C11 : NC */
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PAD_NC(GPP_C11, NONE),
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/* C15 : NC */
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PAD_NC(GPP_C15, NONE),
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/* F1 : NC */
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PAD_NC(GPP_F1, NONE),
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/* F3 : MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
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/* F10 : MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
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/* F11 : EMMC_CMD ==> EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK ==> EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK ==> EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RESET# ==> EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* H6 : NC */
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PAD_NC(GPP_H6, NONE),
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/* H7 : NC */
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PAD_NC(GPP_H7, NONE),
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/* H19 : MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
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/* H22 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
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};
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const struct pad_config *override_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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/*
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* GPIOs configured before ramstage
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* Note: the Hatch platform's romstage will configure
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* the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins
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* as inputs before it reads them, so they are not
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* needed in this table.
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*/
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static const struct pad_config early_gpio_table[] = {
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/* A12 : NC */
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PAD_NC(GPP_A12, NONE),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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/* C14 : BT_DISABLE_L */
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PAD_CFG_GPO(GPP_C14, 0, DEEP),
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/* PCH_WP_OD */
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PAD_CFG_GPI(GPP_C20, NONE, DEEP),
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/* C21 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
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/* C23 : WLAN_PE_RST# */
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PAD_CFG_GPO(GPP_C23, 1, DEEP),
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/* E1 : M2_SSD_PEDET */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E5 : SATA_DEVSLP1 */
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
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/* F11 : EMMC_CMD ==> EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK ==> EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK ==> EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RESET# ==> EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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{
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*num = ARRAY_SIZE(early_gpio_table);
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return early_gpio_table;
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}
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@ -0,0 +1,16 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2019 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/acpi/dptf.asl>
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@ -0,0 +1,21 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_EC_H
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#define VARIANT_EC_H
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#include <baseboard/ec.h>
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#endif
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@ -0,0 +1,27 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef VARIANT_GPIO_H
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#define VARIANT_GPIO_H
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#include <baseboard/gpio.h>
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/* Memory configuration board straps */
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#define GPIO_MEM_CONFIG_0 GPP_H19
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#define GPIO_MEM_CONFIG_1 GPP_H22
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#define GPIO_MEM_CONFIG_2 GPP_F10
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#define GPIO_MEM_CONFIG_3 GPP_F3
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#endif
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181
src/mainboard/google/hatch/variants/akemi/overridetree.cb
Normal file
181
src/mainboard/google/hatch/variants/akemi/overridetree.cb
Normal file
@ -0,0 +1,181 @@
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chip soc/intel/cannonlake
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexI2C0] = PchSerialIoPci,
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[PchSerialIoIndexI2C1] = PchSerialIoPci,
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[PchSerialIoIndexI2C2] = PchSerialIoPci,
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[PchSerialIoIndexI2C3] = PchSerialIoPci,
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[PchSerialIoIndexI2C4] = PchSerialIoPci,
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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[PchSerialIoIndexSPI0] = PchSerialIoPci,
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[PchSerialIoIndexSPI1] = PchSerialIoPci,
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[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
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[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
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[PchSerialIoIndexUART1] = PchSerialIoDisabled,
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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||||||
|
#| | required to set up a BAR |
|
||||||
|
#| | for TPM communication |
|
||||||
|
#| | before memory is up |
|
||||||
|
#| GSPI1 | FP MCU |
|
||||||
|
#| I2C0 | Touchpad |
|
||||||
|
#| I2C1 | Touch screen |
|
||||||
|
#| I2C4 | Audio |
|
||||||
|
#+-------------------+---------------------------+
|
||||||
|
register "common_soc_config" = "{
|
||||||
|
.gspi[0] = {
|
||||||
|
.speed_mhz = 1,
|
||||||
|
.early_init = 1,
|
||||||
|
},
|
||||||
|
.i2c[0] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
},
|
||||||
|
.i2c[1] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 60,
|
||||||
|
.fall_time_ns = 25,
|
||||||
|
},
|
||||||
|
.i2c[3] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 150,
|
||||||
|
.fall_time_ns = 150,
|
||||||
|
},
|
||||||
|
.i2c[4] = {
|
||||||
|
.speed = I2C_SPEED_FAST,
|
||||||
|
.rise_time_ns = 120,
|
||||||
|
.fall_time_ns = 120,
|
||||||
|
},
|
||||||
|
}"
|
||||||
|
|
||||||
|
# GPIO for SD card detect
|
||||||
|
register "sdcard_cd_gpio" = "vSD3_CD_B"
|
||||||
|
|
||||||
|
# Enable eMMC HS400
|
||||||
|
register "ScsEmmcHs400Enabled" = "1"
|
||||||
|
|
||||||
|
device domain 0 on
|
||||||
|
device pci 15.0 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0000""
|
||||||
|
register "desc" = ""ELAN Touchpad""
|
||||||
|
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D21_IRQ)"
|
||||||
|
register "wake" = "GPE0_DW0_21"
|
||||||
|
register "probed" = "1"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""PNP0C50""
|
||||||
|
register "generic.desc" = ""Synaptics Touchpad""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_A21_IRQ)"
|
||||||
|
register "generic.wake" = "GPE0_DW0_21"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x20"
|
||||||
|
device i2c 0x2c on end
|
||||||
|
end
|
||||||
|
end # I2C #0
|
||||||
|
device pci 15.1 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""ELAN0001""
|
||||||
|
register "desc" = ""ELAN Touchscreen""
|
||||||
|
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "probed" = "1"
|
||||||
|
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "reset_delay_ms" = "100"
|
||||||
|
register "reset_off_delay_ms" = "5"
|
||||||
|
register "has_power_resource" = "1"
|
||||||
|
register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)"
|
||||||
|
register "stop_off_delay_ms" = "5"
|
||||||
|
device i2c 10 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""GDIX0000""
|
||||||
|
register "generic.desc" = ""Goodix Touchscreen""
|
||||||
|
register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)"
|
||||||
|
register "generic.probed" = "1"
|
||||||
|
register "generic.reset_gpio" =
|
||||||
|
"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
|
||||||
|
register "generic.reset_delay_ms" = "10"
|
||||||
|
register "generic.reset_off_delay_ms" = "1"
|
||||||
|
register "generic.has_power_resource" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 5d on end
|
||||||
|
end
|
||||||
|
chip drivers/generic/gpio_keys
|
||||||
|
register "name" = ""PENH""
|
||||||
|
register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)"
|
||||||
|
register "key.wake" = "GPE0_DW0_08"
|
||||||
|
register "key.wakeup_event_action" = "EV_ACT_DEASSERTED"
|
||||||
|
register "key.dev_name" = ""EJCT""
|
||||||
|
register "key.linux_code" = "SW_PEN_INSERTED"
|
||||||
|
register "key.linux_input_type" = "EV_SW"
|
||||||
|
register "key.label" = ""pen_eject""
|
||||||
|
device generic 0 on end
|
||||||
|
end
|
||||||
|
end # I2C #1
|
||||||
|
device pci 15.2 off end # I2C #2
|
||||||
|
device pci 15.3 on
|
||||||
|
chip drivers/i2c/sx9310
|
||||||
|
register "desc" = ""SAR Proximity Sensor""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)"
|
||||||
|
register "speed" = "I2C_SPEED_FAST"
|
||||||
|
register "uid" = "1"
|
||||||
|
register "reg_prox_ctrl0" = "0x10"
|
||||||
|
register "reg_prox_ctrl1" = "0x00"
|
||||||
|
register "reg_prox_ctrl2" = "0x84"
|
||||||
|
register "reg_prox_ctrl3" = "0x0e"
|
||||||
|
register "reg_prox_ctrl4" = "0x07"
|
||||||
|
register "reg_prox_ctrl5" = "0xc6"
|
||||||
|
register "reg_prox_ctrl6" = "0x20"
|
||||||
|
register "reg_prox_ctrl7" = "0x0d"
|
||||||
|
register "reg_prox_ctrl8" = "0x8d"
|
||||||
|
register "reg_prox_ctrl9" = "0x43"
|
||||||
|
register "reg_prox_ctrl10" = "0x1f"
|
||||||
|
register "reg_prox_ctrl11" = "0x00"
|
||||||
|
register "reg_prox_ctrl12" = "0x00"
|
||||||
|
register "reg_prox_ctrl13" = "0x00"
|
||||||
|
register "reg_prox_ctrl14" = "0x00"
|
||||||
|
register "reg_prox_ctrl15" = "0x00"
|
||||||
|
register "reg_prox_ctrl16" = "0x00"
|
||||||
|
register "reg_prox_ctrl17" = "0x00"
|
||||||
|
register "reg_prox_ctrl18" = "0x00"
|
||||||
|
register "reg_prox_ctrl19" = "0x00"
|
||||||
|
register "reg_sar_ctrl0" = "0x50"
|
||||||
|
register "reg_sar_ctrl1" = "0x8a"
|
||||||
|
register "reg_sar_ctrl2" = "0x3c"
|
||||||
|
device i2c 28 on end
|
||||||
|
end
|
||||||
|
end # I2C #3
|
||||||
|
device pci 19.0 on
|
||||||
|
chip drivers/i2c/generic
|
||||||
|
register "hid" = ""10EC5682""
|
||||||
|
register "name" = ""RT58""
|
||||||
|
register "desc" = ""Realtek RT5682""
|
||||||
|
register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
|
||||||
|
register "property_count" = "1"
|
||||||
|
# Set the jd_src to RT5668_JD1 for jack detection
|
||||||
|
register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
|
||||||
|
register "property_list[0].name" = ""realtek,jd-src""
|
||||||
|
register "property_list[0].integer" = "1"
|
||||||
|
device i2c 1a on end
|
||||||
|
end
|
||||||
|
end #I2C #4
|
||||||
|
device pci 1a.0 on end # eMMC
|
||||||
|
device pci 1e.3 on
|
||||||
|
chip drivers/spi/acpi
|
||||||
|
register "name" = ""CRFP""
|
||||||
|
register "hid" = "ACPI_DT_NAMESPACE_HID"
|
||||||
|
register "uid" = "1"
|
||||||
|
register "compat_string" = ""google,cros-ec-spi""
|
||||||
|
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)"
|
||||||
|
device spi 1 on end
|
||||||
|
end # FPMCU
|
||||||
|
end # GSPI #1
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
Loading…
x
Reference in New Issue
Block a user