exynos/snow: partial clean-up of snow bootblock using build class
This removes some duplicate code from Snow's mainboard bootblock by utilizing the bootblock build class. Change-Id: I153247370a8c5127260082dcdca3ebdc5e104fb8 Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/2270 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Ronald G. Minnich
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ad7f98cb01
commit
aa6701c090
@@ -18,7 +18,7 @@ config SATA_AHCI
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#
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# 0x0202_0000: vendor-provided BL1
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# 0x0202_3400: bootblock, assume up to 32KB in size
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# 0x0202_2600: ID section, assume 2KB in size. This will be
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# 0x0202_7000: ID section, assume 2KB in size. This will be
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# within the bootblock section.
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# 0x0203_0000: romstage, assume up to 128KB in size.
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# 0x0207_7f00: stack pointer
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@@ -38,7 +38,7 @@ config BOOTBLOCK_BASE
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config ID_SECTION_BASE
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hex
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default 0x02026000
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default 0x02027000
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config ROMSTAGE_BASE
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hex
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@@ -3,6 +3,12 @@
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# image outside of CBFS
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#INTERMEDIATE += exynos5250_add_bl1
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# Clock init is done in bootblock to support UART output for
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# debugging. We may add a Kconfig option to disable clock init
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# in the bootblock and try moving it entirely into romstage.
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bootblock-y += clock_init.c
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bootblock-y += clock.c
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romstage-y += clock.c
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romstage-y += clock_init.c
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romstage-y += exynos_cache.c
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@@ -597,6 +597,38 @@ static int autodetect_memory(void)
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#ifdef CONFIG_SPL_BUILD
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#define SIGNATURE 0xdeadbeef
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/* Parameters of early board initialization in SPL */
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static struct spl_machine_param machine_param = {
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.signature = SIGNATURE,
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.version = 1,
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.params = "vmubfasirMw",
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.size = sizeof(machine_param),
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.mem_iv_size = 0x1f,
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.mem_type = DDR_MODE_DDR3,
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/*
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* Set uboot_size to 0x100000 bytes.
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*
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* This is an overly conservative value chosen to accommodate all
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* possible U-Boot image. You are advised to set this value to a
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* smaller realistic size via scripts that modifies the .machine_param
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* section of output U-Boot image.
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*/
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.uboot_size = 0x100000,
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.boot_source = BOOT_MODE_OM,
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.frequency_mhz = 800,
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.arm_freq_mhz = 1700,
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.serial_base = 0x12c30000,
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.i2c_base = 0x12c60000,
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// .board_rev_gpios = GPIO_D00 | (GPIO_D01 << 16),
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.mem_manuf = MEM_MANUF_SAMSUNG,
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// .bad_wake_gpio = GPIO_Y10,
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};
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/**
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* Get the required memory type and speed (SPL version).
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*
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@@ -608,7 +640,7 @@ int clock_get_mem_selection(enum ddr_mode *mem_type,
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{
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struct spl_machine_param *params;
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params = spl_get_machine_params();
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params = &machine_param;
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*mem_type = params->mem_type;
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*frequency_mhz = params->frequency_mhz;
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*arm_freq = params->arm_freq_mhz;
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@@ -719,7 +751,7 @@ struct arm_clk_ratios *get_arm_ratios(void)
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return arm_ratio;
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}
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die("get_arm_ratios: Failed to find ratio\n");
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// die("get_arm_ratios: Failed to find ratio\n");
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return NULL;
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}
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@@ -1,3 +1,6 @@
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bootblock-y += pwm.c
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bootblock-y += timer.c
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romstage-y += cpu_info.c
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romstage-y += pwm.c # needed by timer.c
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romstage-y += s5p_gpio.c
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