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soc/intel/fsp_broadwell_de: Move early_mainboard_romstage_entry()

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Move early_mainboard_romstage_entry before console_init.
Allows to setup a SuperIO, if any, for serial console.

Change-Id: I370263a6197a4c0c805352f07fedddbee1b8e247
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Patrick Rudolph
2019-01-11 09:18:20 +01:00
committed by Patrick Rudolph
parent 95c021b63a
commit aa6d388597
2 changed files with 6 additions and 3 deletions
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1
src/mainboard/ocp/wedge100s/romstage.c
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@@ -40,6 +40,7 @@ void early_mainboard_romstage_entry(void)
*/ */
msr_t msr = rdmsr(IA32_FEATURE_CONTROL); msr_t msr = rdmsr(IA32_FEATURE_CONTROL);
if (msr.lo & 1) { if (msr.lo & 1) {
console_init();
printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n"); printk(BIOS_EMERG, "Detected broken platform state. Issuing full reset\n");
full_reset(); full_reset();
} }

8
src/soc/intel/fsp_broadwell_de/romstage/romstage.c
View File

@@ -68,14 +68,16 @@ void *asmlinkage main(FSP_INFO_HEADER *fsp_info_header)
pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC), pci_write_config16(PCI_DEV(0x0, LPC_DEV, LPC_FUNC),
LPC_EN, 0x340f); LPC_EN, 0x340f);
} }
console_init();
init_rtc();
setup_gpio_io_address();
/* Call into mainboard. */ /* Call into mainboard. */
post_code(0x41); post_code(0x41);
early_mainboard_romstage_entry(); early_mainboard_romstage_entry();
post_code(0x42);
console_init();
init_rtc();
setup_gpio_io_address();
/* /*
* Call early init to initialize memory and chipset. This function returns * Call early init to initialize memory and chipset. This function returns
* to the romstage_main_continue function with a pointer to the HOB * to the romstage_main_continue function with a pointer to the HOB