trying to compile...
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2062 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Greg Watson
@@ -68,6 +68,17 @@
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#define sprg6w 0x116 /* Special purpose general 6 - write only */
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#define sprg7w 0x117 /* Special purpose general 7 - write only */
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/*----------------------------------------------------------------------------+
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| Machine State Register. MSR_EE, MSR_PR, MSR_FP, MSR_ME, MSR_FE0, MSR_FE1,
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+----------------------------------------------------------------------------*/
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#define MSR_APE 0x00080000 /* wait state enable */
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#define MSR_WE 0x00040000 /* wait state enable */
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#define MSR_CE 0x00020000 /* critical interrupt enable */
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#define MSR_DWE 0x00000400 /* debug wait enable */
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#define MSR_DE 0x00000200 /* debug interrupt enable */
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#define MSR_IR 0x00000020 /* instruction relocale */
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#define MSR_DR 0x00000010 /* data relocale */
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/******************************************************************************
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* Special for PPC405GP
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******************************************************************************/
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32
src/arch/ppc/include/ppc74xx.h
Executable file
32
src/arch/ppc/include/ppc74xx.h
Executable file
@@ -0,0 +1,32 @@
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/* We are interested in the following hid0 bits:
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6 - ECLK - Enable external test clock (603 only)
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11 - DPM - Turn on dynamic power management (603 only)
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15 - NHR - Not hard reset
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16 - ICE - Instruction cache enable
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17 - DCE - Data cache enable
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18 - ILOCK - Instruction cache lock
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19 - DLOCK - Data cache lock
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20 - ICFI - Instruction cache invalidate
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21 - DCFI - Data cache invalidate
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24 - NOSER - Serial execution disable (604 only - turbo mode)
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24 - SGE - Store gathering enable (7410 only)
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29 - BHT - Branch history table (604 only)
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I made up the tags for the 604 specific bits, as they aren't
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named in the 604 book. The 603 book calls the invalidate bits
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ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
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one, and Motorola named the other. */
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#define HID0_ECLK 0x02000000
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#define HID0_DPM 0x00100000
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#define HID0_NHR 0x00010000
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#define HID0_ICE 0x00008000
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#define HID0_DCE 0x00004000
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#define HID0_ILOCK 0x00002000
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#define HID0_DLOCK 0x00001000
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#define HID0_ICFI 0x00000800
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#define HID0_DCFI 0x00000400
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#define HID0_NOSER 0x00000080
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#define HID0_SGE 0x00000080
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#define HID0_BTIC 0x00000020
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#define HID0_BHT 0x00000004
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33
src/arch/ppc/include/ppc750.h
Executable file
33
src/arch/ppc/include/ppc750.h
Executable file
@@ -0,0 +1,33 @@
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/* We are interested in the following hid0 bits:
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6 - ECLK - Enable external test clock (603 only)
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11 - DPM - Turn on dynamic power management (603 only)
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15 - NHR - Not hard reset
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16 - ICE - Instruction cache enable
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17 - DCE - Data cache enable
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18 - ILOCK - Instruction cache lock
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19 - DLOCK - Data cache lock
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20 - ICFI - Instruction cache invalidate
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21 - DCFI - Data cache invalidate
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24 - NOSER - Serial execution disable (604 only - turbo mode)
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24 - SGE - Store gathering enable (7410 only)
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29 - BHT - Branch history table (604 only)
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I made up the tags for the 604 specific bits, as they aren't
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named in the 604 book. The 603 book calls the invalidate bits
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ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
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one, and Motorola named the other. */
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#define HID0_ECLK 0x02000000
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#define HID0_DPM 0x00100000
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#define HID0_NHR 0x00010000
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#define HID0_ICE 0x00008000
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#define HID0_DCE 0x00004000
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#define HID0_ILOCK 0x00002000
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#define HID0_DLOCK 0x00001000
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#define HID0_ICFI 0x00000800
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#define HID0_DCFI 0x00000400
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#define HID0_NOSER 0x00000080
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#define HID0_SGE 0x00000080
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#define HID0_BTIC 0x00000020
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#define HID0_BHT 0x00000004
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@@ -18,16 +18,30 @@
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| 13-Oct-03 Created MPT
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+----------------------------------------------------------------------------*/
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#ifndef _sys_as_archppc970_h_
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#define _sys_as_archppc970_h_
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#ifndef _PPC970_H_
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#define _PPC970_H_
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/*----------------------------------------------------------------------------+
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| PVR value.
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| When timers are running based on CPU speed this is the timer to CPU frequency
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| ratio.
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+----------------------------------------------------------------------------*/
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#define PVR_970_DD1 0x00391100
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#define PVR_970FX_DD2 0x003C0200
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#define PVR_970FX_DD2_1 0x003C0201
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#define PVR_970FX_DD3 0x003C0300
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#define PPC970_TB_RATIO 8
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/*----------------------------------------------------------------------------+
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| Cache line size.
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+----------------------------------------------------------------------------*/
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#define CACHE_LINE_SIZE_L1 128
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#define CACHE_LINE_SIZE_L2 128
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/*----------------------------------------------------------------------------+
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| SLB size.
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+----------------------------------------------------------------------------*/
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#define SLB_SIZE 64
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/*----------------------------------------------------------------------------+
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| TLB size.
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+----------------------------------------------------------------------------*/
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#define TLB_SIZE 1024
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/*----------------------------------------------------------------------------+
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| Special Purpose Registers. Xer (64), lr (64), ctr (64), srr0 (64), srr1 (64)
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@@ -225,4 +239,4 @@
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#define SRR1_ITLB_RELOA 0x00000000000C0000
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#define SRR1_RI 0x0000000000000002
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#endif /* _sys_as_archppc970_h_ */
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#endif /* _PPC970_H_ */
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@@ -2,78 +2,25 @@
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/* This code is distributed without warranty under the GPL v2 (see COPYING) */
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/* In the MSR, not all bits are interesting to us
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13 - POW - Power management
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14 - TGPR - temporary registers for page table routines
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15 - ILE - Exception little endian
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16 - EE - External interrupts
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17 - PR - Privilege level
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18 - FP - Floating Point available
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19 - ME - Machine check exception enable
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20 - FE0 - Floating exception mode 0
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21 - SE - Single step trace mode
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22 - BE - Branch trace enable
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23 - FE1 - Floating exception mode 1
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25 - IP - Exception prefix
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26 - IR - Instruction address translation
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27 - DR - Data address translation
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30 - RI - Recoverable exception
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31 - LE - Little endian mode
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MSR_MASK is the bits we do not change.
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*/
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#define MSR_MASK 0xfff8008c
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#define MSR_POW 0x00040000
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#define MSR_TGPR 0x00020000
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#define MSR_ILE 0x00010000
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#define MSR_EE 0x00008000
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#define MSR_PR 0x00004000
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#define MSR_FP 0x00002000
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#define MSR_ME 0x00001000
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#define MSR_FE0 0x00000800
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#define MSR_SE 0x00000400
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#define MSR_BE 0x00000200
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#define MSR_FE1 0x00000100
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#define MSR_IP 0x00000040
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#define MSR_IR 0x00000020
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#define MSR_DR 0x00000010
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#define MSR_RI 0x00000002
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#define MSR_LE 0x00000001
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#define MSR_DEFAULT (MSR_FP | MSR_IR | MSR_DR)
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/* We are interested in the following hid0 bits:
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6 - ECLK - Enable external test clock (603 only)
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11 - DPM - Turn on dynamic power management (603 only)
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15 - NHR - Not hard reset
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16 - ICE - Instruction cache enable
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17 - DCE - Data cache enable
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18 - ILOCK - Instruction cache lock
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19 - DLOCK - Data cache lock
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20 - ICFI - Instruction cache invalidate
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21 - DCFI - Data cache invalidate
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24 - NOSER - Serial execution disable (604 only - turbo mode)
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24 - SGE - Store gathering enable (7410 only)
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29 - BHT - Branch history table (604 only)
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I made up the tags for the 604 specific bits, as they aren't
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named in the 604 book. The 603 book calls the invalidate bits
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ICFI and DCI, and I have no idea why it isn't DCFI. Maybe IBM named
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one, and Motorola named the other. */
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#define HID0_ECLK 0x02000000
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#define HID0_DPM 0x00100000
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#define HID0_NHR 0x00010000
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#define HID0_ICE 0x00008000
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#define HID0_DCE 0x00004000
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#define HID0_ILOCK 0x00002000
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#define HID0_DLOCK 0x00001000
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#define HID0_ICFI 0x00000800
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#define HID0_DCFI 0x00000400
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#define HID0_NOSER 0x00000080
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#define HID0_SGE 0x00000080
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#define HID0_BTIC 0x00000020
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#define HID0_BHT 0x00000004
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/*
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* BAT defines
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*/
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@@ -181,6 +128,39 @@
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#define PVR_8240 0x00810100
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#define PVR_8260 PVR_8240
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/*----------------------------------------------------------------------------+
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| Processor Version Register (PVR) values
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+----------------------------------------------------------------------------*/
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#define PVR_970 0x0039 /* 970 any revision*/
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#define PVR_970DD_1_0 0x00391100 /* 970 DD1.0 */
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#define PVR_970FX 0x003C /* 970FX any revision*/
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#define PVR_970FX_DD_2_0 0x003C0200 /* 970FX DD2.0 */
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#define PVR_970FX_DD_2_1 0x003C0201 /* 970FX DD2.1 */
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#define PVR_970FX_DD_3_0 0x003C0300 /* 970FX DD3.0 */
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#define PVR_RESERVED 0x000000F0 /* reserved nibble */
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#define SPR_SRR0 0x01a
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#define SPR_SRR1 0x01b
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#define SPR_SPRG0 0x110
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#define SPR_SPRG1 0x111
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#define SPR_SPRG2 0x112
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#define SPR_SPRG3 0x113
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#define SPR_PVR 0x11f
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#define SPR_TBLR 0x10c
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#define SPR_TBUR 0x10d
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#ifdef __PPC64__
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#define LOAD_64BIT_VAL(ra,value) addis ra,r0,value@highest; \
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ori ra,ra,value@higher; \
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sldi ra,ra,32; \
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oris ra,ra,value@h; \
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ori ra,ra,value@l
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#define TLBIEL(rb) .long 0x7C000000|\
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(rb<<11)|(274<<1)
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#define HRFID() .long 0x4C000000|\
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(274<<1)
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#endif
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#ifndef ASM
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unsigned __getmsr(void);
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void __setmsr(unsigned value);
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