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mb/google/fatcat: Add support for soldered-down memory

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This change adds support for soldered-down memory on the Fatcat board.
It introduces a new Kconfig option `MEMORY_SOLDERDOWN` and includes
the necessary Makefiles adjustments to handle SPD data in CBFS when
this option is enabled.

* A new Kconfig option `MEMORY_SOLDERDOWN` is added to control
soldered-down memory support.
* When `MEMORY_SOLDERDOWN` is enabled, it selects:
    * `CHROMEOS_DRAM_PART_NUMBER_IN_CBI` if `CHROMEOS` is enabled
    * `HAVE_SPD_IN_CBFS`
* The Makefile is updated to include the `variants/$(VARIANT_DIR)/
memory` subdirectory and conditionally include the `spd` subdirectory
based on `CONFIG_HAVE_SPD_IN_CBFS`.

BUG=b:348678071
TEST=Able to build google/fatcat with N-1 silicon.

Change-Id: I7edc1134630940812186118a29cbbd550f0e3634
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
This commit is contained in:
Subrata Banik
2024-08-08 14:46:35 +05:30
parent c84ff28ac5
commit ab1d04a0c4
3 changed files with 14 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/google/fatcat/Kconfig
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@@ -26,6 +26,7 @@ config BOARD_GOOGLE_BASEBOARD_FATCAT
select BOARD_GOOGLE_FATCAT_COMMON select BOARD_GOOGLE_FATCAT_COMMON
select HAVE_SLP_S0_GATE select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MEMORY_SOLDERDOWN
select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_METEORLAKE_U_H select SOC_INTEL_METEORLAKE_U_H
select SYSTEM_TYPE_LAPTOP select SYSTEM_TYPE_LAPTOP
@@ -85,6 +86,11 @@ config MAINBOARD_FAMILY
config MAINBOARD_PART_NUMBER config MAINBOARD_PART_NUMBER
default "Fatcat" if BOARD_GOOGLE_FATCAT default "Fatcat" if BOARD_GOOGLE_FATCAT
config MEMORY_SOLDERDOWN
def_bool n
select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS
select HAVE_SPD_IN_CBFS
# FIXME: update as per board schematics # FIXME: update as per board schematics
config TPM_TIS_ACPI_INTERRUPT config TPM_TIS_ACPI_INTERRUPT
int int

2
src/mainboard/google/fatcat/Makefile.mk
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@@ -17,6 +17,8 @@ BASEBOARD_DIR:=$(call strip_quotes,$(CONFIG_BASEBOARD_DIR))
subdirs-y += variants/baseboard/$(BASEBOARD_DIR) subdirs-y += variants/baseboard/$(BASEBOARD_DIR)
subdirs-y += variants/$(VARIANT_DIR) subdirs-y += variants/$(VARIANT_DIR)
subdirs-y += variants/$(VARIANT_DIR)/memory
subdirs-$(CONFIG_HAVE_SPD_IN_CBFS) += spd
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/$(BASEBOARD_DIR)/include

6
src/mainboard/google/fatcat/spd/Makefile.mk Normal file
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@@ -0,0 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
##
ifneq ($(SPD_SOURCES),)
LIB_SPD_DEPS := $(SPD_SOURCES)
endif