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mb/google/brya: Move GPE configuration to baseboard/devicetree.cb

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This change moves GPE configuration from brya0/overridetree.cb to
baseboard/devicetree.cb since all variants will end up using the same
configuration.

TEST=Verified using "abuild -p none -t google/brya -b brya0
--timeless" that coreboot.rom generated with and without this change
is the same.

Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Furquan Shaikh
2021-03-05 09:10:18 -08:00
committed by Tim Wawrzynczak
parent a742681628
commit ab53c3964c
2 changed files with 5 additions and 4 deletions
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5
src/mainboard/google/brya/variants/baseboard/devicetree.cb
View File

@@ -3,6 +3,11 @@ chip soc/intel/alderlake
device lapic 0 on end
end
# GPE configuration
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E"
register "pmc_gpe0_dw2" = "GPP_F"
# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x000c0201"

4
src/mainboard/google/brya/variants/brya0/overridetree.cb
View File

@@ -1,8 +1,4 @@
chip soc/intel/alderlake
register "pmc_gpe0_dw0" = "GPP_A"
register "pmc_gpe0_dw1" = "GPP_E"
register "pmc_gpe0_dw2" = "GPP_F"
register "SaGv" = "SaGv_Disabled"
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port