newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi
@@ -1,131 +0,0 @@
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## we don't use CONFIG_USE_DCACHE_RAM by default
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default CONFIG_USE_DCACHE_RAM=0
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##
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## Compute the location and size of where this firmware image
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## (coreboot plus bootloader) will live in the boot rom chip.
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##
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default CONFIG_ROM_SIZE = 256 * 1024
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default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE
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default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
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##
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## Compute where this copy of coreboot will start in the boot rom
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##
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default CONFIG_ROMBASE = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
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##
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## Compute a range of ROM that can cached to speed up coreboot,
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## execution speed.
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##
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## CONFIG_XIP_ROM_SIZE must be a power of 2.
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## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
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##
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default CONFIG_XIP_ROM_SIZE=32*1024
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default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
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## ALL dependencies for CONFIG_USE_DCACHE_RAM go here.
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## That way, later, we can simply yank them if we wish.
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## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case.
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## we do not use failover yet in this case. This is a work in progress.
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if CONFIG_USE_DCACHE_RAM
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##
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##
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mainboardinit arch/i386/init/entry.S
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mainboardinit arch/i386/init/car.S
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ldscript /arch/i386/init/ldscript.ld
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## The main code for the rom section is called rom.c
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initobject rom.o
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else
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##
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## Romcc output
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##
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makerule ./failover.E
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depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
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action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
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end
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makerule ./failover.inc
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depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
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action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
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end
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makerule ./auto.E
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depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
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action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
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end
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##
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## Build our 16 bit and 32 bit coreboot entry code
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##
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mainboardinit cpu/x86/16bit/entry16.inc
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mainboardinit cpu/x86/32bit/entry32.inc
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ldscript /cpu/x86/16bit/entry16.lds
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ldscript /cpu/x86/32bit/entry32.lds
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##
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## Build our reset vector (This is where coreboot is entered)
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##
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mainboardinit cpu/x86/16bit/reset16.inc
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ldscript /cpu/x86/16bit/reset16.lds
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### Should this be in the northbridge code?
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mainboardinit arch/i386/lib/cpu_reset.inc
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##
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## Setup RAM
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##
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mainboardinit cpu/x86/fpu_enable.inc
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mainboardinit ./auto.inc
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## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future.
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##
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## Include an id string (For safe flashing)
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##
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mainboardinit arch/i386/lib/id.inc
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ldscript /arch/i386/lib/id.lds
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##
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## end of CONFIG_USE_DCACHE_RAM bits.
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##
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end
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##
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## Include the secondary Configuration files
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##
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dir /pc80
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config chip.h
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chip cpu/emulation/qemu-x86
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device pci_domain 0 on
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device pci 0.0 on end
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chip southbridge/intel/i82371eb # southbridge
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device pci 01.0 on end
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device pci 01.1 on end
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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end
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# register "com1" = "{1}"
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# register "com1" = "{1, 0, 0x3f8, 4}"
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end
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end
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@@ -1,140 +0,0 @@
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uses CONFIG_GENERATE_MP_TABLE
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uses CONFIG_GENERATE_PIRQ_TABLE
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uses CONFIG_USE_FALLBACK_IMAGE
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uses CONFIG_HAVE_FALLBACK_BOOT
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uses CONFIG_HAVE_HARD_RESET
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uses CONFIG_HAVE_OPTION_TABLE
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uses CONFIG_USE_OPTION_TABLE
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uses CONFIG_COMPRESS
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uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
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uses CONFIG_COMPRESSED_PAYLOAD_LZMA
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uses CONFIG_PRECOMPRESSED_PAYLOAD
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uses CONFIG_ROM_PAYLOAD
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uses CONFIG_IRQ_SLOT_COUNT
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uses CONFIG_MAINBOARD
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uses CONFIG_MAINBOARD_VENDOR
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uses CONFIG_MAINBOARD_PART_NUMBER
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uses COREBOOT_EXTRA_VERSION
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uses CONFIG_ARCH
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uses CONFIG_FALLBACK_SIZE
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uses CONFIG_STACK_SIZE
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uses CONFIG_HEAP_SIZE
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uses CONFIG_ROM_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_IMAGE_SIZE
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uses CONFIG_ROM_SECTION_SIZE
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uses CONFIG_ROM_SECTION_OFFSET
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uses CONFIG_ROMBASE
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uses CONFIG_RAMBASE
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uses CONFIG_XIP_ROM_SIZE
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uses CONFIG_XIP_ROM_BASE
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uses CONFIG_GENERATE_MP_TABLE
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uses CONFIG_WRITE_HIGH_TABLES
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uses CONFIG_CROSS_COMPILE
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uses CC
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uses HOSTCC
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uses CONFIG_OBJCOPY
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
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uses CONFIG_CONSOLE_SERIAL8250
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uses CONFIG_USE_DCACHE_RAM
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uses CONFIG_DCACHE_RAM_BASE
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uses CONFIG_DCACHE_RAM_SIZE
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uses CONFIG_USE_INIT
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uses CONFIG_USE_PRINTK_IN_CAR
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uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
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uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
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uses CONFIG_UDELAY_IO
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default CONFIG_UDELAY_IO=1
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default CONFIG_CONSOLE_SERIAL8250=1
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default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
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default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
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## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
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default CONFIG_ROM_SIZE = 256*1024
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###
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### Build options
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###
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##
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## Build code for the fallback boot
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##
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default CONFIG_HAVE_FALLBACK_BOOT=1
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##
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## no MP table
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##
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default CONFIG_GENERATE_MP_TABLE=0
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##
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## Build code to reset the motherboard from coreboot
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##
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default CONFIG_HAVE_HARD_RESET=0
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##
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## Build code to export a programmable irq routing table
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##
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default CONFIG_GENERATE_PIRQ_TABLE=1
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default CONFIG_IRQ_SLOT_COUNT=6
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default CONFIG_WRITE_HIGH_TABLES=1
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##
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## Build code to export a CMOS option table
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##
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default CONFIG_HAVE_OPTION_TABLE=1
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##
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## Option ROM init
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##
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default CONFIG_PCI_ROM_RUN=1
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default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
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###
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### coreboot layout values
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###
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## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
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default CONFIG_ROM_IMAGE_SIZE = 65536
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default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
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##
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## Use a small 8K stack
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##
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default CONFIG_STACK_SIZE=0x2000
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##
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## Use a small 16K heap
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##
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default CONFIG_HEAP_SIZE=0x4000
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##
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## Only use the option table in a normal image
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##
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#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
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default CONFIG_USE_OPTION_TABLE = 0
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default CONFIG_RAMBASE = 0x00004000
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default CONFIG_ROM_PAYLOAD = 1
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##
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## The default compiler
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##
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default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
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default HOSTCC="gcc"
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##
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## known-good settings for qemu
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default CONFIG_DCACHE_RAM_BASE=0x8f000
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default CONFIG_DCACHE_RAM_SIZE=0x1000
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end
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