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nb/intel/gm45/gm45.h: Clean up cosmetics

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Align groups of definitions, reflow long lines and adjust whitespace.

Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.

Change-Id: I2969274c6b50f56994e45ada5d016504addfc13e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This commit is contained in:
Angel Pons 2020-09-16 01:13:00 +02:00
parent 9c2d15ff7f
commit ac4e4b423f
1 changed files with 63 additions and 62 deletions
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19
src/northbridge/intel/gm45/gm45.h
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@ -132,6 +132,7 @@ typedef struct {
int gs45_low_power_mode; /* low power mode of GMCH_GS45 */
int sff; /* small form factor option (soldered down DIMM) */
} sysinfo_t;
#define TOTAL_CHANNELS 2
#define CHANNEL_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0)
#define CHANNEL_IS_CARDF(dimms, idx) (dimms[idx].card_type == 0xf)
@ -167,8 +168,7 @@ enum {
/* Offsets of read/write training results in CMOS.
They will be restored upon S3 resumes. */
#define CMOS_READ_TRAINING 0x80 /* 16 bytes */
#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes
(could be reduced to 10 bytes) */
#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes (could be reduced to 10 bytes) */
#define DEFAULT_MCHBAR 0xfed14000
#define DEFAULT_DMIBAR 0xfed18000
@ -193,7 +193,7 @@ enum {
#define D0F0_DMIBAR_LO 0x68
#define D0F0_DMIBAR_HI 0x6c
#define D0F0_PMBASE 0x78
#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/
#define D0F0_PAM(x) (0x90 + (x)) /* 0-6 */
#define D0F0_REMAPBASE 0x98
#define D0F0_REMAPLIMIT 0x9a
#define D0F0_SMRAM 0x9d
@ -286,7 +286,7 @@ enum {
* Every two ranks share one register and must be programmed at the same time.
* All registers (4 ranks per channel) have to be set.
*/
#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r/2) * 4))
#define CxDRBy_MCHBAR(x, r) (0x1200 + (x * 0x0100) + ((r / 2) * 4))
#define CxDRBy_BOUND_SHIFT(r) ((r % 2) * 16)
#define CxDRBy_BOUND_MASK(r) (0x1fc << CxDRBy_BOUND_SHIFT(r))
#define CxDRBy_BOUND_MB(r, b) /* for boundary in MB b */ \
@ -344,11 +344,11 @@ enum {
/* Write Training registers. */
#define CxWRTy_MCHBAR(ch, s) (0x1470 + (ch * 0x0100) + ((3 - s) * 4))
#define CxGTEW(x) (0x1270+(x*0x100))
#define CxGTC(x) (0x1274+(x*0x100))
#define CxDTPEW(x) (0x1278+(x*0x100))
#define CxDTAEW(x) (0x1280+(x*0x100))
#define CxDTC(x) (0x1288+(x*0x100))
#define CxGTEW(x) (0x1270 + (x * 0x100))
#define CxGTC(x) (0x1274 + (x * 0x100))
#define CxDTPEW(x) (0x1278 + (x * 0x100))
#define CxDTAEW(x) (0x1280 + (x * 0x100))
#define CxDTC(x) (0x1288 + (x * 0x100))
/*
@ -382,6 +382,7 @@ enum {
#define EPLE2D 0x60
#ifndef __ACPI__
void gm45_early_init(void);
void gm45_early_reset(void);