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mb/google/volteer: add CNVi ASL entry for dynamic SSDT generation

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This change uses drivers/intel/wifi chip for CNVi device and
adds dynamic SSDT entires for CNVi also export wake gpio for CNVi.

BUG=none
BRANCH=none
TEST=Build and boot volteer

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ia8baf1c7b770db23f31383bda46ae8d090468560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Srinidhi N Kaushik
2020-03-05 17:19:51 -08:00
committed by Patrick Georgi
parent 3d676f147e
commit ac7d6b409e
1 changed files with 4 additions and 1 deletions
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5
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@@ -226,7 +226,10 @@ chip soc/intel/tigerlake
device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.0 on end # USB3.1 xHCI 0xA0ED
device pci 14.1 off end # USB3.1 xDCI 0xA0EE device pci 14.1 off end # USB3.1 xDCI 0xA0EE
device pci 14.2 on end # Shared RAM 0xA0EF device pci 14.2 on end # Shared RAM 0xA0EF
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 chip drivers/intel/wifi
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3
end
device pci 15.0 on device pci 15.0 on
chip drivers/i2c/generic chip drivers/i2c/generic