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soc/intel/skylake: Drop duplicate PmConfigPciClockRun configuration

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coreboot already unconditionally enables CLKRUN_EN in SoC common code.

Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.

Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Benjamin Doron
2020-12-12 22:42:41 +00:00
committed by Nico Huber
parent a04400d1aa
commit ac857ca3b1
4 changed files with 0 additions and 9 deletions
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1
src/soc/intel/skylake/chip.c
View File

@@ -338,7 +338,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PchPmSlpS4MinAssert = config->PmConfigSlpS4MinAssert;
params->PchPmSlpSusMinAssert = config->PmConfigSlpSusMinAssert;
params->PchPmSlpAMinAssert = config->PmConfigSlpAMinAssert;
params->PchPmLpcClockRun = config->PmConfigPciClockRun;
params->PchPmSlpStrchSusUp = config->PmConfigSlpStrchSusUp;
params->PchPmPwrBtnOverridePeriod =
config->PmConfigPwrBtnOverridePeriod;

5
src/soc/intel/skylake/chip.h
View File

@@ -376,11 +376,6 @@ struct soc_intel_skylake_config {
SLP_A_MIN_ASSERT_2S = 3,
} PmConfigSlpAMinAssert;
/*
* This member describes whether or not the PCI ClockRun feature of PCH
* should be enabled. Values 0: Disabled, 1: Enabled
*/
u8 PmConfigPciClockRun;
/*
* SLP_X Stretching After SUS Well Power Up. Values 0: Disabled,
* 1: Enabled