AMD Kabini: Split DSDT into common sections

Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.

Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)

src/cpu/amd/agesa/family16kb/acpi/cpu.asl

@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Processor Object
+ *
+ */
+Scope (\_PR) {		/* define processor scope */
+	Processor(
+		P000,		/* name space name */
+		0,			/* Unique number for this processor */
+		0x810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+
+	Processor(
+		P001,		/* name space name */
+		1,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+	Processor(
+		P002,		/* name space name */
+		2,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+	Processor(
+		P003,		/* name space name */
+		3,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+	Processor(
+		P004,		/* name space name */
+		4,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+	Processor(
+		P005,		/* name space name */
+		5,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+	Processor(
+		P006,		/* name space name */
+		6,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+	Processor(
+		P007,		/* name space name */
+		7,			/* Unique number for this processor */
+		0x0810,		/* PBLK system I/O address !hardcoded! */
+		0x06		/* PBLKLEN for boot processor */
+		) {
+	}
+} /* End _PR scope */

src/mainboard/amd/olivehill/acpi/gpe.asl

@@ -0,0 +1,78 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_GPE) {	/* Start Scope GPE */
+
+	/*  General event 3  */
+	Method(_L03) {
+		/* DBGO("\\_GPE\\_L00\n") */
+		Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Legacy PM event  */
+	Method(_L08) {
+		/* DBGO("\\_GPE\\_L08\n") */
+	}
+
+	/*  Temp warning (TWarn) event  */
+	Method(_L09) {
+		/* DBGO("\\_GPE\\_L09\n") */
+		/* Notify (\_TZ.TZ00, 0x80) */
+	}
+
+	/*  USB controller PME#  */
+	Method(_L0B) {
+		/* DBGO("\\_GPE\\_L0B\n") */
+		Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  ExtEvent0 SCI event  */
+	Method(_L10) {
+		/* DBGO("\\_GPE\\_L10\n") */
+	}
+
+	/*  ExtEvent1 SCI event  */
+	Method(_L11) {
+		/* DBGO("\\_GPE\\_L11\n") */
+	}
+
+	/*  GPIO0 or GEvent8 event  */
+	Method(_L18) {
+		/* DBGO("\\_GPE\\_L18\n") */
+		Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+
+	/*  Azalia SCI event  */
+	Method(_L1B) {
+		/* DBGO("\\_GPE\\_L1B\n") */
+		Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */
+		Notify(\_SB.PCI0.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */
+	}
+} 	/* End Scope GPE */

src/mainboard/amd/olivehill/acpi/ide.asl

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,6 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+/* No IDE functionality */
+
+#if 0
 /*
 Scope (_SB) {
 	Device(PCI0) {
@@ -244,3 +247,4 @@ Device(PRID)
 		}
 	}                                   /* End Device(SLAV) */
 }
+#endif

src/mainboard/amd/olivehill/acpi/mainboard.asl

@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Memory related values */
+Name(LOMH, 0x0)	/* Start of unused memory in C0000-E0000 range */
+Name(PBAD, 0x0)	/* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
+Name(PBLN, 0x0)	/* Length of BIOS area */
+
+Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)	/* Base address of PCIe config space */
+Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
+Name(HPBA, 0xFED00000)	/* Base address of HPET table */
+
+Name(SSFG, 0x0D)		/* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */
+
+/* Some global data */
+Name(OSTP, 3)	/* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */
+Name(OSV, Ones)	/* Assume nothing */
+Name(PMOD, One)	/* Assume APIC */

src/mainboard/amd/olivehill/acpi/routing.asl

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2013 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -26,8 +27,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
 */
 
 /* Routing is in System Bus scope */
-Scope(\_SB) {
+Name(PR0, Package(){
-	Name(PR0, Package(){
 	/* NB devices */
 	/* Bus 0, Dev 0 - F16 Host Controller */
 
@@ -68,9 +68,9 @@ Scope(\_SB) {
 	/* Bus 0, Dev 17 - SATA controller */
 	Package(){0x0011FFFF, 0, INTD, 0 },
 
-	})
+})
 
-	Name(APR0, Package(){
+Name(APR0, Package(){
 	/* NB devices in APIC mode */
 	/* Bus 0, Dev 0 - F15 Host Controller */
 
@@ -110,91 +110,89 @@ Scope(\_SB) {
 	/* Bus 0, Dev 17 - SATA controller */
 	Package(){0x0011FFFF, 0, 0, 19 },
 
-	})
+})
 
-	Name(PS2, Package(){
+Name(PS2, Package(){
 	Package(){0x0000FFFF, 0, INTC, 0 },
 	Package(){0x0000FFFF, 1, INTD, 0 },
 	Package(){0x0000FFFF, 2, INTA, 0 },
 	Package(){0x0000FFFF, 3, INTB, 0 },
-	})
+})
-	Name(APS2, Package(){
+Name(APS2, Package(){
 	Package(){0x0000FFFF, 0, 0, 18 },
 	Package(){0x0000FFFF, 1, 0, 19 },
 	Package(){0x0000FFFF, 2, 0, 16 },
 	Package(){0x0000FFFF, 3, 0, 17 },
-	})
+})
 
-	/* GFX */
+/* GFX */
-	Name(PS4, Package(){
+Name(PS4, Package(){
 	Package(){0x0000FFFF, 0, INTA, 0 },
 	Package(){0x0000FFFF, 1, INTB, 0 },
 	Package(){0x0000FFFF, 2, INTC, 0 },
 	Package(){0x0000FFFF, 3, INTD, 0 },
-	})
+})
-	Name(APS4, Package(){
+Name(APS4, Package(){
 	/* PCIe slot - Hooked to PCIe slot 4 */
 	Package(){0x0000FFFF, 0, 0, 16 },
 	Package(){0x0000FFFF, 1, 0, 17 },
 	Package(){0x0000FFFF, 2, 0, 18 },
 	Package(){0x0000FFFF, 3, 0, 19 },
-	})
+})
 
-	/* GPP 0 */
+/* GPP 0 */
-	Name(PS5, Package(){
+Name(PS5, Package(){
 	Package(){0x0000FFFF, 0, INTB, 0 },
 	Package(){0x0000FFFF, 1, INTC, 0 },
 	Package(){0x0000FFFF, 2, INTD, 0 },
 	Package(){0x0000FFFF, 3, INTA, 0 },
-	})
+})
-	Name(APS5, Package(){
+Name(APS5, Package(){
 	Package(){0x0000FFFF, 0, 0, 17 },
 	Package(){0x0000FFFF, 1, 0, 18 },
 	Package(){0x0000FFFF, 2, 0, 19 },
 	Package(){0x0000FFFF, 3, 0, 16 },
-	})
+})
 
-	/* GPP 1 */
+/* GPP 1 */
-	Name(PS6, Package(){
+Name(PS6, Package(){
 	Package(){0x0000FFFF, 0, INTC, 0 },
 	Package(){0x0000FFFF, 1, INTD, 0 },
 	Package(){0x0000FFFF, 2, INTA, 0 },
 	Package(){0x0000FFFF, 3, INTB, 0 },
-	})
+})
-	Name(APS6, Package(){
+Name(APS6, Package(){
 	Package(){0x0000FFFF, 0, 0, 18 },
 	Package(){0x0000FFFF, 1, 0, 19 },
 	Package(){0x0000FFFF, 2, 0, 16 },
 	Package(){0x0000FFFF, 3, 0, 17 },
-	})
+})
 
-	/* GPP 2 */
+/* GPP 2 */
-	Name(PS7, Package(){
+Name(PS7, Package(){
 	Package(){0x0000FFFF, 0, INTD, 0 },
 	Package(){0x0000FFFF, 1, INTA, 0 },
 	Package(){0x0000FFFF, 2, INTB, 0 },
 	Package(){0x0000FFFF, 3, INTC, 0 },
-	})
+})
-	Name(APS7, Package(){
+Name(APS7, Package(){
 	Package(){0x0000FFFF, 0, 0, 19 },
 	Package(){0x0000FFFF, 1, 0, 16 },
 	Package(){0x0000FFFF, 2, 0, 17 },
 	Package(){0x0000FFFF, 3, 0, 18 },
-	})
+})
 
-	/* GPP 3 */
+/* GPP 3 */
-	Name(PS8, Package(){
+Name(PS8, Package(){
 	Package(){0x0000FFFF, 0, INTA, 0 },
 	Package(){0x0000FFFF, 1, INTB, 0 },
 	Package(){0x0000FFFF, 2, INTC, 0 },
 	Package(){0x0000FFFF, 3, INTD, 0 },
-	})
+})
-	Name(APS8, Package(){
+Name(APS8, Package(){
 	Package(){0x0000FFFF, 0, 0, 16 },
 	Package(){0x0000FFFF, 1, 0, 17 },
 	Package(){0x0000FFFF, 2, 0, 18 },
-		Package(){0x0000FFFF, 3, 0, 19 },
+	Package(){0x0000FFFF, 3, 0, 18 },
-	})
+})
 
-
-}

src/mainboard/amd/olivehill/acpi/sata.asl

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012-2013 Advanced Micro Devices, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-/* simple name description */
+/* No SATA functionality */
 
+#if 0
 /*
 Scope (_SB) {
 	Device(PCI0) {
@@ -146,3 +147,4 @@ Scope(\_GPE) {
 		}
 	}
 }
+#endif

src/mainboard/amd/olivehill/acpi/si.asl

@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Scope(\_SI) {
+	Method(_SST, 1) {
+		/* DBGO("\\_SI\\_SST\n") */
+		/* DBGO("   New Indicator state: ") */
+		/* DBGO(Arg0) */
+		/* DBGO("\n") */
+	}
+} /* End Scope SI */

src/mainboard/amd/olivehill/acpi/sleep.asl

@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Wake status package */
+Name(WKST,Package(){Zero, Zero})
+
+/*
+* \_PTS - Prepare to Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2, etc
+*
+* Exit:
+*		-none-
+*
+* The _PTS control method is executed at the beginning of the sleep process
+* for S1-S5. The sleeping value is passed to the _PTS control method.	This
+* control method may be executed a relatively long time before entering the
+* sleep state and the OS may abort	the operation without notification to
+* the ACPI driver.  This method cannot modify the configuration or power
+* state of any device in the system.
+*/
+Method(_PTS, 1) {
+	/* DBGO("\\_PTS\n") */
+	/* DBGO("From S0 to S") */
+	/* DBGO(Arg0) */
+	/* DBGO("\n") */
+
+	/* Clear wake status structure. */
+	Store(0, Index(WKST,0))
+	Store(0, Index(WKST,1))
+	Store(7, UPWS)
+} /* End Method(\_PTS) */
+
+/*
+*	\_BFS OEM Back From Sleep method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		-none-
+*/
+Method(\_BFS, 1) {
+	/* DBGO("\\_BFS\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+}
+
+/*
+*  \_WAK System Wake method
+*
+*	Entry:
+*		Arg0=The value of the sleeping state S1=1, S2=2
+*
+*	Exit:
+*		Return package of 2 DWords
+*		Dword 1 - Status
+*			0x00000000	wake succeeded
+*			0x00000001	Wake was signaled but failed due to lack of power
+*			0x00000002	Wake was signaled but failed due to thermal condition
+*		Dword 2 - Power Supply state
+*			if non-zero the effective S-state the power supply entered
+*/
+Method(\_WAK, 1) {
+	/* DBGO("\\_WAK\n") */
+	/* DBGO("From S") */
+	/* DBGO(Arg0) */
+	/* DBGO(" to S0\n") */
+
+	Return(WKST)
+} /* End Method(\_WAK) */

src/mainboard/amd/olivehill/acpi/superio.asl

@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No Super I/O device or functionality yet */

src/mainboard/amd/olivehill/acpi/thermal.asl

@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* No thermal zone functionality */

src/mainboard/amd/olivehill/acpi/usb_oc.asl

@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -25,6 +26,22 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001
 		#include "usb.asl"
 	}
 */
+
+/* USB overcurrent mapping pins.   */
+Name(UOM0, 0)
+Name(UOM1, 2)
+Name(UOM2, 0)
+Name(UOM3, 7)
+Name(UOM4, 2)
+Name(UOM5, 2)
+Name(UOM6, 6)
+Name(UOM7, 2)
+Name(UOM8, 6)
+Name(UOM9, 6)
+
+/* USB Overcurrent GPEs */
+
+#if 0 /* TODO: Update for Olivehill */
 Method(UCOC, 0) {
 	Sleep(20)
 	Store(0x13,CMTI)
@@ -112,3 +129,4 @@ If (LLessEqual(UOM9,9)) {
 		}
 	}
 }
+#endif

src/northbridge/amd/agesa/family16kb/acpi/northbridge.asl

@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
+Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
+Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method(_BBN, 0, NotSerialized)	/* Bus number = 0 */
+{
+	Return(Zero)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+	Return(0x0B)	/* Status is visible */
+}
+
+Method(_PRT,0, NotSerialized)
+{
+	If(PMOD)
+	{
+		Return(APR0)	/* APIC mode */
+	}
+	Return (PR0)		/* PIC Mode */
+}
+
+Device(AMRT) {
+	Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Gpp 0 */
+Device(PBR4) {
+	Name(_ADR, 0x00020001)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS4) }	/* APIC mode */
+		Return (PS4)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR4 */
+
+/* Gpp 1 */
+Device(PBR5) {
+	Name(_ADR, 0x00020002)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS5) }	/* APIC mode */
+		Return (PS5)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR5 */
+
+/* Gpp 2 */
+Device(PBR6) {
+	Name(_ADR, 0x00020003)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS6) }	/* APIC mode */
+		Return (PS6)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR6 */
+
+/* Gpp 3 */
+Device(PBR7) {
+	Name(_ADR, 0x00020004)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS7) }	/* APIC mode */
+		Return (PS7)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR7 */
+
+/* Gpp 4 */
+Device(PBR8) {
+	Name(_ADR, 0x00020005)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS8) }	/* APIC mode */
+		Return (PS8)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR8 */

src/southbridge/amd/agesa/hudson/acpi/audio.asl

@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-Device(AZHD) {
+Device(AZHD) {	/* 0:14.2 - HD Audio */
 	Name(_ADR, 0x00140002)
 	OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
 		Field(AZPD, AnyAcc, NoLock, Preserve) {
@@ -44,6 +44,7 @@ Device(AZHD) {
 		offset (0x6C),
 		MMDT, 16,
 	}
+
 	Method (_INI, 0, NotSerialized)
 	{
 		If (LEqual (OSTP, 0x03))

src/southbridge/amd/agesa/hudson/acpi/fch.asl

@@ -23,7 +23,38 @@
 
 /* Describe the Southbridge devices */
 
-/* PCI slot 1, 2, 3 */
+/* 0:11.0 - SATA */
+Device(STCR) {
+	Name(_ADR, 0x00110000)
+	#include "acpi/sata.asl"
+} /* end STCR */
+
+/* 0:14.0 - SMBUS */
+Device(SBUS) {
+	Name(_ADR, 0x00140000)
+} /* end SBUS */
+
+#include "usb.asl"
+
+/* 0:14.2 - HD Audio */
+#include "audio.asl"
+
+/* 0:14.3 - LPC */
+#include "lpc.asl"
+
+/* 0:14.7 - SD Controller */
+Device(SDCN) {
+	Name(_ADR, 0x00140007)
+} /* end SDCN */
+
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+/* 0:14.1 - Primary (and only) IDE channel */
+Device(IDEC) {
+	Name(_ADR, 0x00140001)
+	#include "acpi/ide.asl"
+} /* end IDEC */
+
+/* 0:14.4 - PCI slot 1, 2, 3 */
 Device(PIBR) {
 	Name(_ADR, 0x00140004)
 	Name(_PRW, Package() {0x18, 4})
@@ -33,57 +64,13 @@ Device(PIBR) {
 	}
 }
 
-Device(SBUS) {
+/* 0:14.6 - GEC Controller */
-	Name(_ADR, 0x00140000)
-} /* end SBUS */
-
-/* Primary (and only) IDE channel */
-Device(IDEC) {
-	Name(_ADR, 0x00140001)
-	#include "acpi/ide.asl"
-} /* end IDEC */
-
-Device(STCR) {
-	Name(_ADR, 0x00110000)
-	#include "acpi/sata.asl"
-} /* end STCR */
-
-#include "usb.asl"
-
-#include "audio.asl"
-
-#include "lpc.asl"
-
-Device(HPBR) {
-	Name(_ADR, 0x00140004)
-} /* end HostPciBr */
-
-Device(ACAD) {
-	Name(_ADR, 0x00140005)
-} /* end Ac97audio */
-
 Device(ACMD) {
 	Name(_ADR, 0x00140006)
 } /* end Ac97modem */
+#endif
 
 Name(CRES, ResourceTemplate() {
-	/* Set the Bus number and Secondary Bus number for the PCI0 device
-	 * The Secondary bus range for PCI0 lets the system
-	 * know what bus values are allowed on the downstream
-	 * side of this PCI bus if there is a PCI-PCI bridge.
-	 * PCI busses can have 256 secondary busses which
-	 * range from [0-0xFF] but they do not need to be
-	 * sequential.
-	 */
-
-	WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
-		0x0000,		/* address granularity */
-		0x0000,		/* range minimum */
-		0x00FF,		/* range maximum */
-		0x0000,		/* translation */
-		0x0100,		/* length */
-		,, PSB0)	/* ResourceSourceIndex, ResourceSource, DescriptorName */
-
 	IO(Decode16, 0x0CF8, 0x0CF8, 1,	8)
 
 	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
@@ -100,6 +87,7 @@ Name(CRES, ResourceTemplate() {
 		0x0000,		/* translation */
 		0x0030		/* length */
 	)
+
 	WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
 		0x0000,		/* address granularity */
 		0x0D00,		/* range minimum */
@@ -137,13 +125,13 @@ Method(_CRS, 0) {
 } /* end of Method(_SB.PCI0._CRS) */
 
 /*
-*
+ *
-*               FIRST METHOD CALLED UPON BOOT
+ *               FIRST METHOD CALLED UPON BOOT
-*
+ *
-*  1. If debugging, print current OS and ACPI interpreter.
+ *  1. If debugging, print current OS and ACPI interpreter.
-*  2. Get PCI Interrupt routing from ACPI VSM, this
+ *  2. Get PCI Interrupt routing from ACPI VSM, this
-*     value is based on user choice in BIOS setup.
+ *     value is based on user choice in BIOS setup.
-*/
+ */
 Method(_INI, 0) {
 	/* DBGO("\\_SB\\_INI\n") */
 	/* DBGO("   DSDT.ASL code from ") */
@@ -161,11 +149,9 @@ Method(_INI, 0) {
 	/* Determine the OS we're running on */
 	CkOT()
 
-	/* On older chips, clear PciExpWakeDisEn */
+	/* TODO: It is unstable. */
-	/*if (LLessEqual(\SBRI, 0x13)) {
+	//#include "acpi/AmdImc.asl" /* Hudson IMC function */
-	*    	Store(0,\PWDE)
+	//ITZE() /* enable IMC Fan Control*/
-	* }
-	*/
 } /* End Method(_SB._INI) */
 
 Method(CkOT, 0){

src/southbridge/amd/agesa/hudson/acpi/lpc.asl

@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+/* 0:14.3 - LPC */
 Device(LIBR) {
 	Name(_ADR, 0x00140003)
 	/* Method(_INI) {

src/southbridge/amd/agesa/hudson/acpi/pci_int.asl

@@ -17,16 +17,16 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/* PCIe Configuration Space for 16 busses */
+	/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
 	OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
 		Field(PCFG, ByteAcc, NoLock, Preserve) {
 		/* Byte offsets are computed using the following technique:
 		 * ((bus number + 1) * ((device number * 8) * 4096)) + register offset
 		 * The 8 comes from 8 functions per device, and 4096 bytes per function config space
 		*/
-		Offset(0x00088024),	/* SATA reg 24h Bus 0, Device 17, Function 0 */
+		Offset(0x00088024),	/* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */
 		STB5, 32,
-		Offset(0x00098042),	/* OHCI0 reg 42h - Bus 0, Device 19, Function 0 */
+		Offset(0x00098042),	/* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */
 		PT0D, 1,
 		PT1D, 1,
 		PT2D, 1,
@@ -37,14 +37,14 @@
 		PT7D, 1,
 		PT8D, 1,
 		PT9D, 1,
-		Offset(0x000A0004),	/* SMBUS reg 4h - Bus 0, Device 20, Function 0 */
+		Offset(0x000A0004),	/* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */
 		SBIE, 1,
 		SBME, 1,
-		Offset(0x000A0008),	/* SMBUS reg 8h - Bus 0, Device 20, Function 0 */
+		Offset(0x000A0008),	/* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */
 		SBRI, 8,
-		Offset(0x000A0014),	/* SMBUS reg 14h - Bus 0, Device 20, Function 0 */
+		Offset(0x000A0014),	/* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */
 		SBB1, 32,
-		Offset(0x000A0078),	/* SMBUS reg 78h - Bus 0, Device 20, Function 0 */
+		Offset(0x000A0078),	/* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */
 		,14,
 		P92E, 1,		/* Port92 decode enable */
 	}
@@ -181,6 +181,7 @@
 			if (Local0) {
 				Decrement(Local0)
 			}
+			Store(Local0, PIRA)
 		} /* End Method(_SB.INTA._SRS) */
 	} /* End Device(INTA) */
 
@@ -467,5 +468,6 @@
 			if (Local0) {
 				Decrement(Local0)
 			}
+			Store(Local0, PIRH)
 		} /* End Method(_SB.INTH._SRS)  */
 	} /* End Device(INTH)   */

src/southbridge/amd/agesa/hudson/acpi/sleepstates.asl

@@ -24,8 +24,8 @@ Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} )	/* (S0) - working state */
 If (LAnd(SSFG, 0x01)) {
 	Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} )	/* (S1) - sleeping w/CPU context */
 }
-If (LAnd (SSFG, 0x02)) {
+If (LAnd(SSFG, 0x02)) {
-	Name (_S2, Package () {0x02, 0x02, Zero, Zero} )	/* (S2) - "light" Suspend to RAM */
+	Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} )	/* (S2) - "light" Suspend to RAM */
 }
 If (LAnd(SSFG, 0x04)) {
 	Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} )	/* (S3) - Suspend to RAM */

src/southbridge/amd/agesa/hudson/acpi/usb.asl

@@ -19,46 +19,60 @@
  * MA 02110-1301 USA
  */
 
+/* 0:12.0 - OHCI */
 Device(UOH1) {
 	Name(_ADR, 0x00120000)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UOH1 */
 
+/* 0:12.2 - EHCI */
 Device(UOH2) {
 	Name(_ADR, 0x00120002)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UOH2 */
 
+/* 0:13.0 - OHCI */
 Device(UOH3) {
 	Name(_ADR, 0x00130000)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UOH3 */
 
+/* 0:13.2 - EHCI */
 Device(UOH4) {
 	Name(_ADR, 0x00130002)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UOH4 */
 
+/* 0:16.0 - OHCI */
 Device(UOH5) {
 	Name(_ADR, 0x00160000)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UOH5 */
 
+/* 0:16.2 - EHCI */
 Device(UOH6) {
 	Name(_ADR, 0x00160002)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UOH5 */
 
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+/* 0:14.5 - OHCI */
 Device(UEH1) {
 	Name(_ADR, 0x00140005)
 	Name(_PRW, Package() {0x0B, 3})
 } /* end UEH1 */
+#endif
 
+/* 0:10.0 - XHCI 0*/
 Device(XHC0) {
 	Name(_ADR, 0x00100000)
 	Name(_PRW, Package() {0x0B, 4})
 } /* end XHC0 */
+
+#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
+/* 0:10.1 - XHCI 1*/
 Device(XHC1) {
 	Name(_ADR, 0x00100001)
 	Name(_PRW, Package() {0x0B, 4})
 } /* end XHC1 */
+#endif