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soc/intel/skylake: Add Kabylake PCH H device ID's

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Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H.

Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23382
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
V Sowmya
2018-01-23 15:27:23 +05:30
committed by Subrata Banik
parent 742a0e911c
commit acc2a4819c
10 changed files with 29 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/include/device/pci_ids.h
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@@ -2668,6 +2668,7 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_C236 0xa150
#define PCI_DEVICE_ID_INTEL_SPT_H_PREMIUM 0xa14e
#define PCI_DEVICE_ID_INTEL_SPT_H_QM170 0xa14d
#define PCI_DEVICE_ID_INTEL_KBP_H_Q270 0xa2c6
#define PCI_DEVICE_ID_INTEL_SPT_LP_Y_PREMIUM_HDCP22 0x9d4b
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22 0x9d4e
#define PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22 0x9d50
@@ -2771,6 +2772,7 @@
/* Intel PMC device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21
#define PCI_DEVICE_ID_INTEL_SPT_H_PMC 0xa121
#define PCI_DEVICE_ID_INTEL_KBP_H_PMC 0xa2a1
#define PCI_DEVICE_ID_INTEL_APL_PMC 0x5a94
#define PCI_DEVICE_ID_INTEL_GLK_PMC 0x3194
#define PCI_DEVICE_ID_INTEL_CNL_PMC 0x9da1
@@ -2782,6 +2784,10 @@
#define PCI_DEVICE_ID_INTEL_SPT_I2C3 0x9d63
#define PCI_DEVICE_ID_INTEL_SPT_I2C4 0x9d64
#define PCI_DEVICE_ID_INTEL_SPT_I2C5 0x9d65
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C0 0xa2e0
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C1 0xa2e1
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C2 0xa2e2
#define PCI_DEVICE_ID_INTEL_KBP_H_I2C3 0xa2e3
#define PCI_DEVICE_ID_INTEL_APL_I2C0 0x5aac
#define PCI_DEVICE_ID_INTEL_APL_I2C1 0x5aae
#define PCI_DEVICE_ID_INTEL_APL_I2C2 0x5ab0
@@ -2812,6 +2818,9 @@
#define PCI_DEVICE_ID_INTEL_SPT_H_UART0 0xa127
#define PCI_DEVICE_ID_INTEL_SPT_H_UART1 0xa128
#define PCI_DEVICE_ID_INTEL_SPT_H_UART2 0xa166
#define PCI_DEVICE_ID_INTEL_KBP_H_UART0 0xa2a7
#define PCI_DEVICE_ID_INTEL_KBP_H_UART1 0xa2a8
#define PCI_DEVICE_ID_INTEL_KBP_H_UART2 0xa2e6
#define PCI_DEVICE_ID_INTEL_APL_UART0 0x5abc
#define PCI_DEVICE_ID_INTEL_APL_UART1 0x5abe
#define PCI_DEVICE_ID_INTEL_APL_UART2 0x5ac0
@@ -2848,6 +2857,7 @@
#define PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM 0x191D
#define PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM 0x193D
#define PCI_DEVICE_ID_INTEL_KBL_GT1_SULTM 0x5906
#define PCI_DEVICE_ID_INTEL_KBL_GT2_DT2P2 0x5912
#define PCI_DEVICE_ID_INTEL_KBL_GT2_SULXM 0x591E
#define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTM 0x5916
#define PCI_DEVICE_ID_INTEL_KBL_GT2_SULTMR 0x5917
@@ -2877,12 +2887,14 @@
#define PCI_DEVICE_ID_INTEL_KBL_ID_Y 0x590c
#define PCI_DEVICE_ID_INTEL_KBL_ID_H 0x5910
#define PCI_DEVICE_ID_INTEL_KBL_U_R 0x5914
#define PCI_DEVICE_ID_INTEL_KBL_ID_DT 0x591f
#define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04
#define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02
/* Intel SMBUS device Ids */
#define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23
#define PCI_DEVICE_ID_INTEL_SPT_H_SMBUS 0xa123
#define PCI_DEVICE_ID_INTEL_KBP_H_SMBUS 0xa1a3
#define PCI_DEVICE_ID_INTEL_CNL_SMBUS 0x9da3
/* Intel XHCI device Ids */
@@ -2890,6 +2902,7 @@
#define PCI_DEVICE_ID_INTEL_GLK_XHCI 0x31a8
#define PCI_DEVICE_ID_INTEL_SPT_LP_XHCI 0x9d2f
#define PCI_DEVICE_ID_INTEL_SPT_H_XHCI 0xa12f
#define PCI_DEVICE_ID_INTEL_KBP_H_XHCI 0xa2af
#define PCI_DEVICE_ID_INTEL_CNL_LP_XHCI 0x9ded
/* Intel P2SB device Ids */