From acd98d87722adbf8cc94c770881cf3105b02786f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 18 Oct 2022 19:28:50 +0200 Subject: [PATCH] soc/amd/stoneyridge/uart: add and use uart_info array Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge with the other AMD SoCs in order to allow commonization of the AMD SoC UART code. Since the current Stoneyridge code doesn't provide or use UART MMIO device operations, only the base addresses of the UART controllers from this array are used for now. Signed-off-by: Felix Held Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger --- src/soc/amd/stoneyridge/uart.c | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 573ae96716..969146dc07 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -1,13 +1,28 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include -#include +#include +#include +#include #include +static const struct soc_uart_ctrlr_info uart_info[] = { + [0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", { + PAD_NF(GPIO_138, UART0_TXD, PULL_NONE), + PAD_NF(GPIO_136, UART0_RXD, PULL_NONE), + } }, + [1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", { + PAD_NF(GPIO_143, UART1_TXD, PULL_NONE), + PAD_NF(GPIO_141, UART1_RXD, PULL_NONE), + } }, +}; + uintptr_t get_uart_base(unsigned int idx) { - if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + if (idx >= ARRAY_SIZE(uart_info)) return 0; - return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); + return uart_info[idx].base; }