Enable more PCIe devices
Change-Id: I1113ae7f601b8c9db05ea8ec794d6e4b149af6b5
This commit is contained in:
@@ -249,7 +249,7 @@ chip soc/intel/tigerlake
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device pci 15.1 on end # I2C1 0xA0E9
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device pci 15.1 on end # I2C1 0xA0E9
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device pci 15.2 on end # I2C2 0xA0EA
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device pci 15.2 on end # I2C2 0xA0EA
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device pci 15.3 off end # I2C3 0xA0EB
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device pci 15.3 off end # I2C3 0xA0EB
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device pci 16.0 off end # HECI1 0xA0E0
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device pci 16.0 on end # HECI1 0xA0E0
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device pci 16.1 off end # HECI2 0xA0E1
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device pci 16.1 off end # HECI2 0xA0E1
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device pci 16.2 off end # CSME 0xA0E2
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device pci 16.2 off end # CSME 0xA0E2
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device pci 16.3 off end # CSME 0xA0E3
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device pci 16.3 off end # CSME 0xA0E3
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@@ -260,45 +260,49 @@ chip soc/intel/tigerlake
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device pci 19.1 off end # I2C5 0xA0C6
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device pci 19.1 off end # I2C5 0xA0C6
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device pci 19.2 on end # UART2 0xA0C7
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device pci 19.2 on end # UART2 0xA0C7
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device pci 1c.0 on end # RP1 0xA0B8
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device pci 1c.0 on end # RP1 0xA0B8
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device pci 1c.1 off end # RP2 0xA0B9
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device pci 1c.1 on end # RP2 0xA0B9
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device pci 1c.2 on end # RP3 0xA0BA
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device pci 1c.2 on end # RP3 0xA0BA
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device pci 1c.3 on end # RP4 0xA0BB
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device pci 1c.3 on end # RP4 0xA0BB
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device pci 1c.4 off end # RP5 0xA0BC
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device pci 1c.4 on end # RP5 0xA0BC
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device pci 1c.5 off end # RP6 0xA0BD
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device pci 1c.5 on end # RP6 0xA0BD
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device pci 1c.6 off end # RP7 0xA0BE
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device pci 1c.6 on end # RP7 0xA0BE
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device pci 1c.7 off end # RP8 0xA0BF
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device pci 1c.7 on end # RP8 0xA0BF
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device pci 1d.0 on end # RP9 0xA0B0
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device pci 1d.0 on end # RP9 0xA0B0
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device pci 1d.1 off end # RP10 0xA0B1
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device pci 1d.1 on end # RP10 0xA0B1
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device pci 1d.2 on end # RP11 0xA0B2
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device pci 1d.2 on end # RP11 0xA0B2
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device pci 1d.3 off end # RP12 0xA0B3
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device pci 1d.3 on end # RP12 0xA0B3
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device pci 1e.0 off end # UART0 0xA0A8
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device pci 1e.0 off end # UART0 0xA0A8
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device pci 1e.1 off end # UART1 0xA0A9
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device pci 1e.1 off end # UART1 0xA0A9
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device pci 1e.2 off end # GSPI0 0xA0AA
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device pci 1e.2 off end # GSPI0 0xA0AA
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device pci 1e.3 off end # GSPI1 0xA0AB
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device pci 1e.3 off end # GSPI1 0xA0AB
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device pci 1f.0 on end # eSPI 0xA080 - A09F
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device pci 1f.0 on # eSPI 0xA080 - A09F
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 on end # P2SB 0xA0A0
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device pci 1f.1 on end # P2SB 0xA0A0
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device pci 1f.2 hidden # PMC 0xA0A1
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device pci 1f.2 hidden # PMC 0xA0A1
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# TODO: verify
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# TODO: verify
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# The pmc_mux chip driver is a placeholder for the
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# The pmc_mux chip driver is a placeholder for the
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# PMC.MUX device in the ACPI hierarchy.
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# PMC.MUX device in the ACPI hierarchy.
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chip drivers/intel/pmc_mux
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# chip drivers/intel/pmc_mux
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device generic 0 on
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# device generic 0 on
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chip drivers/intel/pmc_mux/conn
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# chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "2"
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# register "usb2_port_number" = "2"
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register "usb3_port_number" = "2"
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# register "usb3_port_number" = "2"
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# SBU is fixed, HSL follows CC
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# # SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 0 on end
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# device generic 0 on end
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end
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# end
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chip drivers/intel/pmc_mux/conn
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# chip drivers/intel/pmc_mux/conn
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register "usb2_port_number" = "6"
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# register "usb2_port_number" = "6"
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register "usb3_port_number" = "4"
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# register "usb3_port_number" = "4"
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# SBU is fixed, HSL follows CC
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# # SBU is fixed, HSL follows CC
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register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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# register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
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device generic 1 on end
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# device generic 1 on end
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end
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# end
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end
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# end
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end
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# end
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end # PMC
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end # PMC
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device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
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device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
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device pci 1f.4 on end # SMBus 0xA0A3
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device pci 1f.4 on end # SMBus 0xA0A3
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