Enable more PCIe devices

Change-Id: I1113ae7f601b8c9db05ea8ec794d6e4b149af6b5
This commit is contained in:
Jeremy Soller
2020-10-15 20:54:01 -06:00
parent 0a7afd5b4c
commit ace9fe645a

View File

@@ -249,7 +249,7 @@ chip soc/intel/tigerlake
device pci 15.1 on end # I2C1 0xA0E9 device pci 15.1 on end # I2C1 0xA0E9
device pci 15.2 on end # I2C2 0xA0EA device pci 15.2 on end # I2C2 0xA0EA
device pci 15.3 off end # I2C3 0xA0EB device pci 15.3 off end # I2C3 0xA0EB
device pci 16.0 off end # HECI1 0xA0E0 device pci 16.0 on end # HECI1 0xA0E0
device pci 16.1 off end # HECI2 0xA0E1 device pci 16.1 off end # HECI2 0xA0E1
device pci 16.2 off end # CSME 0xA0E2 device pci 16.2 off end # CSME 0xA0E2
device pci 16.3 off end # CSME 0xA0E3 device pci 16.3 off end # CSME 0xA0E3
@@ -260,45 +260,49 @@ chip soc/intel/tigerlake
device pci 19.1 off end # I2C5 0xA0C6 device pci 19.1 off end # I2C5 0xA0C6
device pci 19.2 on end # UART2 0xA0C7 device pci 19.2 on end # UART2 0xA0C7
device pci 1c.0 on end # RP1 0xA0B8 device pci 1c.0 on end # RP1 0xA0B8
device pci 1c.1 off end # RP2 0xA0B9 device pci 1c.1 on end # RP2 0xA0B9
device pci 1c.2 on end # RP3 0xA0BA device pci 1c.2 on end # RP3 0xA0BA
device pci 1c.3 on end # RP4 0xA0BB device pci 1c.3 on end # RP4 0xA0BB
device pci 1c.4 off end # RP5 0xA0BC device pci 1c.4 on end # RP5 0xA0BC
device pci 1c.5 off end # RP6 0xA0BD device pci 1c.5 on end # RP6 0xA0BD
device pci 1c.6 off end # RP7 0xA0BE device pci 1c.6 on end # RP7 0xA0BE
device pci 1c.7 off end # RP8 0xA0BF device pci 1c.7 on end # RP8 0xA0BF
device pci 1d.0 on end # RP9 0xA0B0 device pci 1d.0 on end # RP9 0xA0B0
device pci 1d.1 off end # RP10 0xA0B1 device pci 1d.1 on end # RP10 0xA0B1
device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.2 on end # RP11 0xA0B2
device pci 1d.3 off end # RP12 0xA0B3 device pci 1d.3 on end # RP12 0xA0B3
device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.0 off end # UART0 0xA0A8
device pci 1e.1 off end # UART1 0xA0A9 device pci 1e.1 off end # UART1 0xA0A9
device pci 1e.2 off end # GSPI0 0xA0AA device pci 1e.2 off end # GSPI0 0xA0AA
device pci 1e.3 off end # GSPI1 0xA0AB device pci 1e.3 off end # GSPI1 0xA0AB
device pci 1f.0 on end # eSPI 0xA080 - A09F device pci 1f.0 on # eSPI 0xA080 - A09F
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
end
device pci 1f.1 on end # P2SB 0xA0A0 device pci 1f.1 on end # P2SB 0xA0A0
device pci 1f.2 hidden # PMC 0xA0A1 device pci 1f.2 hidden # PMC 0xA0A1
# TODO: verify # TODO: verify
# The pmc_mux chip driver is a placeholder for the # The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy. # PMC.MUX device in the ACPI hierarchy.
chip drivers/intel/pmc_mux # chip drivers/intel/pmc_mux
device generic 0 on # device generic 0 on
chip drivers/intel/pmc_mux/conn # chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "2" # register "usb2_port_number" = "2"
register "usb3_port_number" = "2" # register "usb3_port_number" = "2"
# SBU is fixed, HSL follows CC # # SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" # register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 0 on end # device generic 0 on end
end # end
chip drivers/intel/pmc_mux/conn # chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "6" # register "usb2_port_number" = "6"
register "usb3_port_number" = "4" # register "usb3_port_number" = "4"
# SBU is fixed, HSL follows CC # # SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" # register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 1 on end # device generic 1 on end
end # end
end # end
end # end
end # PMC end # PMC
device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF device pci 1f.3 on end # Intel HD audio 0xA0C8-A0CF
device pci 1f.4 on end # SMBus 0xA0A3 device pci 1f.4 on end # SMBus 0xA0A3