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soc/amd/mendocino: Hook up UPD dxio_tx_vboost_enable for PCIe optimization

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Add the UPD dxio_tx_vboost_enable for PCIe optimization.
It will impact the PCIe signal integrity, need to double-confirm
the SI result after enabling this setting.

BUG=b:259622787
BRANCH=none
TEST=confirm the setting has been set correspondingly with checking
     the FSP log.

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I05ae5b3091219e0cb1fe469c929fad6a725db678
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71562
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris.Wang
2022-12-28 17:07:48 +08:00
committed by Martin L Roth
parent e66fcb87fe
commit ad12b4f440
3 changed files with 7 additions and 1 deletions
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3
src/vendorcode/amd/fsp/mendocino/FspmUpd.h
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@ -96,7 +96,8 @@ typedef struct __packed {
/** Offset 0x04D7**/ uint8_t UnusedUpdSpace1;
/* usb_phy_ptr is actually struct usb_phy_config *, but that won't work for 64bit coreboot */
/** Offset 0x04D8**/ uint32_t usb_phy_ptr;
/** Offset 0x04DC**/ uint8_t UnusedUpdSpace2[292];
/** Offset 0x04DC**/ uint8_t dxio_tx_vboost_enable;
/** Offset 0x04DD**/ uint8_t UnusedUpdSpace2[291];
/** Offset 0x0600**/ uint16_t UpdTerminator;
} FSP_M_CONFIG;