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sb/intel/common: Fix style issue in spi.c

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Change-Id: I6b9e0e0c643f9b47cfe8bdfffbe247f477ace685
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS
2018-11-26 15:57:30 +01:00
committed by Patrick Georgi
parent e143243c1c
commit ad19c2f58b
1 changed files with 54 additions and 52 deletions
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18
src/southbridge/intel/common/spi.c
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@@ -196,6 +196,7 @@ enum {
static u8 readb_(const void *addr)
{
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -204,6 +205,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -212,6 +214,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -439,7 +442,8 @@ static int spi_setup_opcode(spi_transaction *trans)
optypes = (optypes & 0xfffc) | (trans->type & 0x3);
writew_(optypes, cntlr->optype);
return 0;
} else {
}
/* The lock is on. See if what we need is on the menu. */
uint8_t optype;
uint16_t opcode_index;
@@ -476,7 +480,6 @@ static int spi_setup_opcode(spi_transaction *trans)
}
return opcode_index;
}
}
static int spi_setup_offset(spi_transaction *trans)
{
@@ -689,6 +692,7 @@ static void ich_hwseq_set_addr(uint32_t addr)
{
ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);
uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;
writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);
}
@@ -773,8 +777,7 @@ static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,
hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */
hsfc |= HSFC_FGO; /* start */
writew_(hsfc, &cntlr->ich9_spi->hsfc);
if (ich_hwseq_wait_for_cycle_complete(timeout, len))
{
if (ich_hwseq_wait_for_cycle_complete(timeout, len)) {
printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);
ret = -1;
goto out;
@@ -908,8 +911,7 @@ static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,
hsfc |= HSFC_FGO; /* start */
writew_(hsfc, &cntlr->ich9_spi->hsfc);
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))
{
if (ich_hwseq_wait_for_cycle_complete(timeout, block_len)) {
printk(BIOS_ERR, "SF: write failure at %x\n",
addr);
return -1;
@@ -945,8 +947,7 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi,
flash->name = "Opaque HW-sequencing";
ich_hwseq_set_addr(0);
switch ((cntlr->hsfs >> 3) & 3)
{
switch ((cntlr->hsfs >> 3) & 3) {
case 0:
flash->sector_size = 256;
break;
@@ -991,6 +992,7 @@ static u32 spi_fpr(u32 base, u32 limit)
{
u32 ret;
u32 mask, limit_shift;
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX)) {
mask = ICH7_SPI_FPR_MASK;
limit_shift = ICH7_SPI_FPR_LIMIT_SHIFT;