From 98eeb961353d187a26085a07889bd0414cdaa910 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 11 Dec 2019 15:47:42 -0800 Subject: [PATCH 001/151] commonlib: Add commonlib/bsd This patch creates a new commonlib/bsd subdirectory with a similar purpose to the existing commonlib, with the difference that all files under this subdirectory shall be licensed under the BSD-3-Clause license (or compatible permissive license). The goal is to allow more code to be shared with libpayload in the future. Initially, I'm going to move a few files there that have already been BSD-licensed in the existing commonlib. I am also exracting most contents of the often-needed as long as they have either been written by me (and are hereby relicensed) or have an existing equivalent in BSD-licensed libpayload code. I am also relicensing (written by me) and (same stuff exists in libpayload). Finally, I am extracting the cb_err error code definitions from into a new BSD-licensed header so that future commonlib/bsd code can build upon a common set of error values. I am making the assumption here that the enum constants and the half-sentence fragments of documentation next to them by themselves do not meet the threshold of copyrightability. Change-Id: I316cea70930f131e8e93d4218542ddb5ae4b63a2 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38420 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- MAINTAINERS | 2 +- Makefile.inc | 4 +- src/arch/arm64/fit_payload.c | 5 +- src/arch/riscv/boot.c | 2 +- src/arch/riscv/fit_payload.c | 4 +- src/arch/riscv/sbi.c | 1 - src/arch/riscv/smp.c | 1 - src/commonlib/Makefile.inc | 12 +-- .../bsd/include/commonlib/bsd/cb_err.h | 42 +++++++++ .../include/commonlib/bsd}/cbfs_serialized.h | 46 +--------- .../include/commonlib/bsd}/compiler.h | 17 +--- .../include/commonlib/bsd}/compression.h | 13 +-- .../include/commonlib/bsd/fmap_serialized.h | 41 +++++++++ .../bsd/include/commonlib/bsd/helpers.h | 89 +++++++++++++++++++ src/commonlib/{ => bsd}/lz4.c.inc | 0 src/commonlib/{ => bsd}/lz4_wrapper.c | 45 ++-------- src/commonlib/include/commonlib/cbfs.h | 2 +- .../include/commonlib/fmap_serialized.h | 74 --------------- src/commonlib/include/commonlib/helpers.h | 89 +------------------ src/include/fmap.h | 2 +- src/include/types.h | 33 +------ src/lib/cbfs.c | 2 +- src/lib/decompressor.c | 2 +- src/lib/fit.c | 2 +- src/lib/fit_payload.c | 4 +- src/lib/fmap.c | 1 - src/lib/selfboot.c | 2 +- .../google/poppy/variants/nami/mainboard.c | 1 - src/soc/nvidia/tegra124/lp0/Makefile | 2 +- src/soc/nvidia/tegra210/lp0/Makefile | 2 +- src/vendorcode/amd/pi/00670F00/Makefile.inc | 12 +-- src/vendorcode/amd/pi/Makefile.inc | 13 +-- util/cbfstool/Makefile.inc | 8 +- util/cbfstool/cbfs-mkstage.c | 2 +- util/cbfstool/compress.c | 2 +- util/cbmem/Makefile | 4 +- util/ifdtool/Makefile | 4 +- util/inteltool/Makefile | 3 +- util/intelvbttool/Makefile | 2 +- util/sconfig/Makefile.inc | 2 +- 40 files changed, 244 insertions(+), 350 deletions(-) create mode 100644 src/commonlib/bsd/include/commonlib/bsd/cb_err.h rename src/commonlib/{include/commonlib => bsd/include/commonlib/bsd}/cbfs_serialized.h (67%) rename src/commonlib/{include/commonlib => bsd/include/commonlib/bsd}/compiler.h (72%) rename src/commonlib/{include/commonlib => bsd/include/commonlib/bsd}/compression.h (62%) create mode 100644 src/commonlib/bsd/include/commonlib/bsd/fmap_serialized.h create mode 100644 src/commonlib/bsd/include/commonlib/bsd/helpers.h rename src/commonlib/{ => bsd}/lz4.c.inc (100%) rename src/commonlib/{ => bsd}/lz4_wrapper.c (70%) delete mode 100644 src/commonlib/include/commonlib/fmap_serialized.h diff --git a/MAINTAINERS b/MAINTAINERS index 97ffaeeae5..77769c0487 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -490,7 +490,7 @@ F: src/device/oprom/ CBFS F: src/include/cbfs.h -F: src/include/cbfs_serialized.h +F: src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h F: util/cbfstool/ CBMEM diff --git a/Makefile.inc b/Makefile.inc index 002d3e7d0b..e9c5054e8a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -394,12 +394,12 @@ COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION endif -CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj) +CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -Isrc/commonlib/bsd/include -I$(obj) VBOOT_SOURCE ?= 3rdparty/vboot CPPFLAGS_common += -I$(VBOOT_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h CPPFLAGS_common += -include $(src)/include/rules.h -CPPFLAGS_common += -include $(src)/commonlib/include/commonlib/compiler.h +CPPFLAGS_common += -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h CPPFLAGS_common += -I3rdparty CPPFLAGS_common += -D__BUILD_DIR__=\"$(obj)\" diff --git a/src/arch/arm64/fit_payload.c b/src/arch/arm64/fit_payload.c index 002df44fcc..7009a3f25d 100644 --- a/src/arch/arm64/fit_payload.c +++ b/src/arch/arm64/fit_payload.c @@ -12,13 +12,12 @@ * GNU General Public License for more details. */ +#include +#include #include #include #include #include -#include -#include -#include #include #include #include diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index aaaac485ea..f9f94a7086 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include struct arch_prog_run_args { diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 89263d3fad..63cda846fc 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include +#include #include #include #include -#include -#include #include #include #include diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c index e0d7c60e5f..27701895dd 100644 --- a/src/arch/riscv/sbi.c +++ b/src/arch/riscv/sbi.c @@ -15,7 +15,6 @@ #include #include -#include #include #include #include diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index b32e4b8694..95d116a629 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -18,7 +18,6 @@ #include #include #include -#include #include void smp_pause(int working_hartid) diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index b6e8913cd1..5bd6cf9e65 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -30,11 +30,11 @@ ramstage-y += cbfs.c smm-y += cbfs.c postcar-y += cbfs.c -decompressor-y += lz4_wrapper.c -bootblock-y += lz4_wrapper.c -verstage-y += lz4_wrapper.c -romstage-y += lz4_wrapper.c -ramstage-y += lz4_wrapper.c -postcar-y += lz4_wrapper.c +decompressor-y += bsd/lz4_wrapper.c +bootblock-y += bsd/lz4_wrapper.c +verstage-y += bsd/lz4_wrapper.c +romstage-y += bsd/lz4_wrapper.c +ramstage-y += bsd/lz4_wrapper.c +postcar-y += bsd/lz4_wrapper.c ramstage-y += sort.c diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h new file mode 100644 index 0000000000..ab419a7709 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#ifndef _COMMONLIB_BSD_CB_ERR_H_ +#define _COMMONLIB_BSD_CB_ERR_H_ + +#include + +/** + * coreboot error codes + * + * Common error definitions that can be used for any function. All error values + * should be negative -- when useful, positive values can also be used to denote + * success. Allocate a new group or errors every 100 values. + */ +enum cb_err { + CB_SUCCESS = 0, /**< Call completed successfully */ + CB_ERR = -1, /**< Generic error code */ + CB_ERR_ARG = -2, /**< Invalid argument */ + + /* NVRAM/CMOS errors */ + CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */ + CB_CMOS_LAYOUT_NOT_FOUND = -101, /**< Layout file not found */ + CB_CMOS_OPTION_NOT_FOUND = -102, /**< Option string not found */ + CB_CMOS_ACCESS_ERROR = -103, /**< CMOS access error */ + CB_CMOS_CHECKSUM_INVALID = -104, /**< CMOS checksum is invalid */ + + /* Keyboard test failures */ + CB_KBD_CONTROLLER_FAILURE = -200, + CB_KBD_INTERFACE_FAILURE = -201, + + /* I2C controller failures */ + CB_I2C_NO_DEVICE = -300, /**< Device is not responding */ + CB_I2C_BUSY = -301, /**< Device tells it's busy */ + CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave + device response, try again? */ + CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ +}; + +/* Don't typedef the enum directly, so the size is unambiguous for serialization. */ +typedef int32_t cb_err_t; + +#endif /* _COMMONLIB_BSD_CB_ERR_H_ */ diff --git a/src/commonlib/include/commonlib/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h similarity index 67% rename from src/commonlib/include/commonlib/cbfs_serialized.h rename to src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index d3a18c600a..d2fc6267ad 100644 --- a/src/commonlib/include/commonlib/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -1,48 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Jordan Crouse - * Copyright (C) 2012 Google, Inc. - * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * - * This file is dual-licensed. You can choose between: - * - The GNU GPL, version 2, as published by the Free Software Foundation - * - The revised BSD license (without advertising clause) - * - * --------------------------------------------------------------------------- - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * --------------------------------------------------------------------------- - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * --------------------------------------------------------------------------- - */ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ #ifndef _CBFS_SERIALIZED_H_ #define _CBFS_SERIALIZED_H_ diff --git a/src/commonlib/include/commonlib/compiler.h b/src/commonlib/bsd/include/commonlib/bsd/compiler.h similarity index 72% rename from src/commonlib/include/commonlib/compiler.h rename to src/commonlib/bsd/include/commonlib/bsd/compiler.h index 972a2293a2..ee2ff88d10 100644 --- a/src/commonlib/include/commonlib/compiler.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compiler.h @@ -1,18 +1,7 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ -#ifndef _COMMONLIB_COMPILER_H_ -#define _COMMONLIB_COMPILER_H_ +#ifndef _COMMONLIB_BSD_COMPILER_H_ +#define _COMMONLIB_BSD_COMPILER_H_ #ifndef __packed #if defined(__WIN32) || defined(__WIN64) diff --git a/src/commonlib/include/commonlib/compression.h b/src/commonlib/bsd/include/commonlib/bsd/compression.h similarity index 62% rename from src/commonlib/include/commonlib/compression.h rename to src/commonlib/bsd/include/commonlib/bsd/compression.h index 3988ef8ade..873e7e4e15 100644 --- a/src/commonlib/include/commonlib/compression.h +++ b/src/commonlib/bsd/include/commonlib/bsd/compression.h @@ -1,15 +1,4 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ #ifndef _COMMONLIB_COMPRESSION_H_ #define _COMMONLIB_COMPRESSION_H_ diff --git a/src/commonlib/bsd/include/commonlib/bsd/fmap_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/fmap_serialized.h new file mode 100644 index 0000000000..3d328c45b8 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/fmap_serialized.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ + +#ifndef FLASHMAP_SERIALIZED_H__ +#define FLASHMAP_SERIALIZED_H__ + +#include + +#define FMAP_SIGNATURE "__FMAP__" +#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */ +#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */ +#define FMAP_STRLEN 32 /* maximum length for strings, */ + /* including null-terminator */ + +enum fmap_flags { + FMAP_AREA_STATIC = 1 << 0, + FMAP_AREA_COMPRESSED = 1 << 1, + FMAP_AREA_RO = 1 << 2, + FMAP_AREA_PRESERVE = 1 << 3, +}; + +/* Mapping of volatile and static regions in firmware binary */ +struct fmap_area { + uint32_t offset; /* offset relative to base */ + uint32_t size; /* size in bytes */ + uint8_t name[FMAP_STRLEN]; /* descriptive name */ + uint16_t flags; /* flags for this area */ +} __packed; + +struct fmap { + uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */ + uint8_t ver_major; /* major version */ + uint8_t ver_minor; /* minor version */ + uint64_t base; /* address of the firmware binary */ + uint32_t size; /* size of firmware binary in bytes */ + uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */ + uint16_t nareas; /* number of areas described by + fmap_areas[] below */ + struct fmap_area areas[]; +} __packed; + +#endif /* FLASHMAP_SERIALIZED_H__ */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/helpers.h b/src/commonlib/bsd/include/commonlib/bsd/helpers.h new file mode 100644 index 0000000000..a305df0cd5 --- /dev/null +++ b/src/commonlib/bsd/include/commonlib/bsd/helpers.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ + +#ifndef COMMONLIB_BSD_HELPERS_H +#define COMMONLIB_BSD_HELPERS_H + +#ifndef __ASSEMBLER__ +#include +#include +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#endif + +#define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) +#define ALIGN_UP(x, a) ALIGN((x), (a)) +#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL)) +#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0) + +/* Double-evaluation unsafe min/max, for bitfields and outside of functions */ +#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) +#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) +#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) + +#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ + __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ + __TYPEOF_UNLESS_CONST(b, a) var_b = (b); \ + var_a op var_b ? var_a : var_b; \ +}) + +#define __CMP(a, b, op) __builtin_choose_expr( \ + __builtin_constant_p(a) && __builtin_constant_p(b), \ + __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) + +#ifndef MIN +#define MIN(a, b) __CMP(a, b, <) +#endif +#ifndef MAX +#define MAX(a, b) __CMP(a, b, >) +#endif + +#ifndef ABS +#define ABS(a) ({ \ + __typeof__(a) _abs_local_a = (a); \ + (_abs_local_a < 0) ? (-_abs_local_a) : _abs_local_a; \ +}) +#endif + +#define IS_POWER_OF_2(x) ({ \ + __typeof__(x) _power_local_x = (x); \ + (_power_local_x & (_power_local_x - 1)) == 0; \ +}) + +#define DIV_ROUND_UP(x, y) ({ \ + __typeof__(x) _div_local_x = (x); \ + __typeof__(y) _div_local_y = (y); \ + (_div_local_x + _div_local_y - 1) / _div_local_y; \ +}) + +#define SWAP(a, b) do { \ + __typeof__(&(a)) _swap_local_a = &(a); \ + __typeof__(&(b)) _swap_local_b = &(b); \ + __typeof__(a) _swap_local_tmp = *_swap_local_a; \ + *_swap_local_a = *_swap_local_b; \ + *_swap_local_b = _swap_local_tmp; \ +} while (0) + +/* Standard units. */ +#define KiB (1<<10) +#define MiB (1<<20) +#define GiB (1<<30) + +#define KHz (1000) +#define MHz (1000 * KHz) +#define GHz (1000 * MHz) + +#ifndef offsetof +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) +#endif + +#define check_member(structure, member, offset) _Static_assert( \ + offsetof(struct structure, member) == offset, \ + "`struct " #structure "` offset for `" #member "` is not " #offset) + +/* Calculate size of structure member. */ +#define member_size(type, member) (sizeof(((type *)0)->member)) + +#endif /* COMMONLIB_BSD_HELPERS_H */ diff --git a/src/commonlib/lz4.c.inc b/src/commonlib/bsd/lz4.c.inc similarity index 100% rename from src/commonlib/lz4.c.inc rename to src/commonlib/bsd/lz4.c.inc diff --git a/src/commonlib/lz4_wrapper.c b/src/commonlib/bsd/lz4_wrapper.c similarity index 70% rename from src/commonlib/lz4_wrapper.c rename to src/commonlib/bsd/lz4_wrapper.c index 474df642c2..2367afceaf 100644 --- a/src/commonlib/lz4_wrapper.c +++ b/src/commonlib/bsd/lz4_wrapper.c @@ -1,37 +1,8 @@ -/* - * Copyright 2015-2016 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - */ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-only */ -#include -#include -#include +#include +#include +#include #include #include @@ -41,7 +12,7 @@ * access support), we can easily write the ones we need ourselves. */ static uint16_t LZ4_readLE16(const void *src) { - return read_le16(src); + return le16toh(*(const uint16_t *)src); } static void LZ4_copy8(void *dst, const void *src) { @@ -143,7 +114,7 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) return 0; /* input overrun */ /* We assume there's always only a single, standard frame. */ - if (read_le32(&h->magic) != LZ4F_MAGICNUMBER || h->version != 1) + if (le32toh(h->magic) != LZ4F_MAGICNUMBER || h->version != 1) return 0; /* unknown format */ if (h->reserved0 || h->reserved1 || h->reserved2) return 0; /* reserved must be zero */ @@ -158,7 +129,9 @@ size_t ulz4fn(const void *src, size_t srcn, void *dst, size_t dstn) } while (1) { - struct lz4_block_header b = { { .raw = read_le32(in) } }; + struct lz4_block_header b = { + { .raw = le32toh(*(const uint32_t *)in) } + }; in += sizeof(struct lz4_block_header); if ((size_t)(in - src) + b.size > srcn) diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index b0aa9d3ddb..470173023e 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -14,7 +14,7 @@ #ifndef _COMMONLIB_CBFS_H_ #define _COMMONLIB_CBFS_H_ -#include +#include #include #include diff --git a/src/commonlib/include/commonlib/fmap_serialized.h b/src/commonlib/include/commonlib/fmap_serialized.h deleted file mode 100644 index 53a09af7a8..0000000000 --- a/src/commonlib/include/commonlib/fmap_serialized.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright 2010, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * * Neither the name of Google Inc. nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Alternatively, this software may be distributed under the terms of the - * GNU General Public License ("GPL") version 2 as published by the Free - * Software Foundation. - */ - -#ifndef FLASHMAP_SERIALIZED_H__ -#define FLASHMAP_SERIALIZED_H__ - -#include - -#define FMAP_SIGNATURE "__FMAP__" -#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */ -#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */ -#define FMAP_STRLEN 32 /* maximum length for strings, */ - /* including null-terminator */ - -enum fmap_flags { - FMAP_AREA_STATIC = 1 << 0, - FMAP_AREA_COMPRESSED = 1 << 1, - FMAP_AREA_RO = 1 << 2, - FMAP_AREA_PRESERVE = 1 << 3, -}; - -/* Mapping of volatile and static regions in firmware binary */ -struct fmap_area { - uint32_t offset; /* offset relative to base */ - uint32_t size; /* size in bytes */ - uint8_t name[FMAP_STRLEN]; /* descriptive name */ - uint16_t flags; /* flags for this area */ -} __packed; - -struct fmap { - uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */ - uint8_t ver_major; /* major version */ - uint8_t ver_minor; /* minor version */ - uint64_t base; /* address of the firmware binary */ - uint32_t size; /* size of firmware binary in bytes */ - uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */ - uint16_t nareas; /* number of areas described by - fmap_areas[] below */ - struct fmap_area areas[]; -} __packed; - -#endif /* FLASHMAP_SERIALIZED_H__ */ diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h index f07b6c22f1..a5fe87d42e 100644 --- a/src/commonlib/include/commonlib/helpers.h +++ b/src/commonlib/include/commonlib/helpers.h @@ -13,71 +13,12 @@ #ifndef COMMONLIB_HELPERS_H #define COMMONLIB_HELPERS_H -/* This file is for helpers for both coreboot firmware and its utilities. */ -#ifndef __ASSEMBLER__ -#include -#include -#endif +/* This file is for helpers for both coreboot firmware and its utilities. Most + of this has moved into now, this wrapper is just + for the stuff that nobody bothered to confirm BSD-licensability of yet. */ -#ifndef ARRAY_SIZE -#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#endif - -#define ALIGN(x, a) __ALIGN_MASK(x, (__typeof__(x))(a)-1UL) -#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) -#define ALIGN_UP(x, a) ALIGN((x), (a)) -#define ALIGN_DOWN(x, a) ((x) & ~((__typeof__(x))(a)-1UL)) -#define IS_ALIGNED(x, a) (((x) & ((__typeof__(x))(a)-1UL)) == 0) - -/* Double-evaluation unsafe min/max, for bitfields and outside of functions */ -#define __CMP_UNSAFE(a, b, op) ((a) op (b) ? (a) : (b)) -#define MIN_UNSAFE(a, b) __CMP_UNSAFE(a, b, <) -#define MAX_UNSAFE(a, b) __CMP_UNSAFE(a, b, >) - -#define __CMP_SAFE(a, b, op, var_a, var_b) ({ \ - __TYPEOF_UNLESS_CONST(a, b) var_a = (a); \ - __TYPEOF_UNLESS_CONST(b, a) var_b = (b); \ - var_a op var_b ? var_a : var_b; \ -}) - - -#define __CMP(a, b, op) __builtin_choose_expr( \ - __builtin_constant_p(a) && __builtin_constant_p(b), \ - __CMP_UNSAFE(a, b, op), __CMP_SAFE(a, b, op, __TMPNAME, __TMPNAME)) - -#ifndef MIN -#define MIN(a, b) __CMP(a, b, <) -#endif -#ifndef MAX -#define MAX(a, b) __CMP(a, b, >) -#endif - -#ifndef ABS -#define ABS(a) ({ \ - __typeof__(a) _abs_local_a = (a); \ - (_abs_local_a < 0) ? (-_abs_local_a) : _abs_local_a; \ -}) -#endif - -#define IS_POWER_OF_2(x) ({ \ - __typeof__(x) _power_local_x = (x); \ - (_power_local_x & (_power_local_x - 1)) == 0; \ -}) - -#define DIV_ROUND_UP(x, y) ({ \ - __typeof__(x) _div_local_x = (x); \ - __typeof__(y) _div_local_y = (y); \ - (_div_local_x + _div_local_y - 1) / _div_local_y; \ -}) - -#define SWAP(a, b) do { \ - __typeof__(&(a)) _swap_local_a = &(a); \ - __typeof__(&(b)) _swap_local_b = &(b); \ - __typeof__(a) _swap_local_tmp = *_swap_local_a; \ - *_swap_local_a = *_swap_local_b; \ - *_swap_local_b = _swap_local_tmp; \ -} while (0) +#include /* * Divide positive or negative dividend by positive divisor and round @@ -93,25 +34,6 @@ ((_div_local_x - (_div_local_d / 2)) / _div_local_d); \ }) -/* Standard units. */ -#define KiB (1<<10) -#define MiB (1<<20) -#define GiB (1<<30) -/* Could we ever run into this one? I hope we get this much memory! */ -#define TiB (1<<40) - -#define KHz (1000) -#define MHz (1000 * KHz) -#define GHz (1000 * MHz) - -#ifndef offsetof -#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) -#endif - -#define check_member(structure, member, offset) _Static_assert( \ - offsetof(struct structure, member) == offset, \ - "`struct " #structure "` offset for `" #member "` is not " #offset) - /** * container_of - cast a member of a structure out to the containing structure * @param ptr: the pointer to the member. @@ -123,9 +45,6 @@ const __typeof__(((type *)0)->member) *__mptr = (ptr); \ (type *)((char *)__mptr - offsetof(type, member)); }) -/* Calculate size of structure member. */ -#define member_size(type, member) (sizeof(((type *)0)->member)) - #ifndef __unused #define __unused __attribute__((unused)) #endif diff --git a/src/include/fmap.h b/src/include/fmap.h index 649ecc0000..9c974cea2e 100644 --- a/src/include/fmap.h +++ b/src/include/fmap.h @@ -16,8 +16,8 @@ #ifndef _FMAP_H_ #define _FMAP_H_ +#include #include -#include /* Locate the named area in the fmap and fill in a region device representing * that area. The region is a sub-region of the readonly boot media. Return diff --git a/src/include/types.h b/src/include/types.h index 30f243ff99..ffb14c9db4 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -17,6 +17,7 @@ #define __TYPES_H /* types.h is supposed to provide the standard headers defined in here: */ +#include #include #include #include @@ -30,36 +31,4 @@ #define BIT(x) (1ul << (x)) #endif -/** - * coreboot error codes - * - * When building functions that return a status or an error code, use cb_err as - * the return type. When failure reason needs to be communicated by the return - * value, define a it here. Start new enum groups with values in decrements of - * 100. - */ -enum cb_err { - CB_SUCCESS = 0, /**< Call completed successfully */ - CB_ERR = -1, /**< Generic error code */ - CB_ERR_ARG = -2, /**< Invalid argument */ - - /* NVRAM/CMOS errors */ - CB_CMOS_OTABLE_DISABLED = -100, /**< Option table disabled */ - CB_CMOS_LAYOUT_NOT_FOUND = -101, /**< Layout file not found */ - CB_CMOS_OPTION_NOT_FOUND = -102, /**< Option string not found */ - CB_CMOS_ACCESS_ERROR = -103, /**< CMOS access error */ - CB_CMOS_CHECKSUM_INVALID = -104, /**< CMOS checksum is invalid */ - - /* Keyboard test failures */ - CB_KBD_CONTROLLER_FAILURE = -200, - CB_KBD_INTERFACE_FAILURE = -201, - - /* I2C controller failures */ - CB_I2C_NO_DEVICE = -300, /**< Device is not responding */ - CB_I2C_BUSY = -301, /**< Device tells it's busy */ - CB_I2C_PROTOCOL_ERROR = -302, /**< Data lost or spurious slave - device response, try again? */ - CB_I2C_TIMEOUT = -303, /**< Transmission timed out */ -}; - #endif /* __TYPES_H */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index e31c7cc925..c712f76be8 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index eb7f16cd88..947105920a 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -15,7 +15,7 @@ */ #include -#include +#include #include #include #include diff --git a/src/lib/fit.c b/src/lib/fit.c index 831e5180f0..edac1927e7 100644 --- a/src/lib/fit.c +++ b/src/lib/fit.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -27,7 +28,6 @@ #include #include #include -#include #include static struct list_node image_nodes; diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c index 1b6c9860f0..83e9b8e901 100644 --- a/src/lib/fit_payload.c +++ b/src/lib/fit_payload.c @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#include +#include #include #include #include @@ -25,8 +27,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/src/lib/fmap.c b/src/lib/fmap.c index 9d2b4e781f..c8843a7340 100644 --- a/src/lib/fmap.c +++ b/src/lib/fmap.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8cf7a6ff57..11fdff3ba1 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -15,7 +15,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include #include diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c index e3855bd794..6d54e174c8 100644 --- a/src/mainboard/google/poppy/variants/nami/mainboard.c +++ b/src/mainboard/google/poppy/variants/nami/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/nvidia/tegra124/lp0/Makefile b/src/soc/nvidia/tegra124/lp0/Makefile index e82edaa8c8..a4bbc07172 100644 --- a/src/soc/nvidia/tegra124/lp0/Makefile +++ b/src/soc/nvidia/tegra124/lp0/Makefile @@ -35,7 +35,7 @@ tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ -include ../../../../include/stdint.h \ - -include ../../../../commonlib/include/commonlib/compiler.h \ + -include ../../../../commonlib/bsd/include/commonlib/bsd/compiler.h \ -o $@ $(filter %.c,$+) tegra_lp0_resume.fw: tegra_lp0_resume.elf diff --git a/src/soc/nvidia/tegra210/lp0/Makefile b/src/soc/nvidia/tegra210/lp0/Makefile index e82edaa8c8..a4bbc07172 100644 --- a/src/soc/nvidia/tegra210/lp0/Makefile +++ b/src/soc/nvidia/tegra210/lp0/Makefile @@ -35,7 +35,7 @@ tegra_lp0_resume.elf: tegra_lp0_resume.ld tegra_lp0_resume.c $(CC) -marm -march=armv4t -mno-unaligned-access -nostdlib -static \ -Os -fpie -Wl,--build-id=none -ggdb3 -T tegra_lp0_resume.ld \ -include ../../../../include/stdint.h \ - -include ../../../../commonlib/include/commonlib/compiler.h \ + -include ../../../../commonlib/bsd/include/commonlib/bsd/compiler.h \ -o $@ $(filter %.c,$+) tegra_lp0_resume.fw: tegra_lp0_resume.elf diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index f6cd8ebbec..34dae71851 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -75,12 +75,12 @@ $(agesa_src_path)/$(notdir $1): $1 $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $(src)/include/kconfig.h @printf " CC $$(subst $(obj)/,,$$(@))\n" - $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ - $(AGESA_INC) \ - -include $(src)/include/kconfig.h \ - -include $(src)/include/rules.h \ - -include $(src)/commonlib/include/commonlib/compiler.h \ - -o $$@ \ + $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ + $(AGESA_INC) \ + -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ + -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h \ + -o $$@ \ $(agesa_src_path)/$(notdir $1) endef diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 9b3a0e6b12..8f27d64f20 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -66,6 +66,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include AGESA_INC += -I$(src)/include AGESA_INC += -I$(src)/commonlib/include +AGESA_INC += -I$(src)/commonlib/bsd/include AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include AGESA_CFLAGS += -march=amdfam10 -mno-3dnow @@ -98,12 +99,12 @@ $(agesa_src_path)/$(notdir $1): $1 $(call src-to-obj,libagesa,$1): $(agesa_src_path)/$(notdir $1) $(obj)/config.h $(src)/include/kconfig.h @printf " CC $$(subst $(obj)/,,$$(@))\n" - $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ - $(AGESA_INC) \ - -include $(src)/include/kconfig.h \ - -include $(src)/include/rules.h \ - -include $(src)/commonlib/include/commonlib/compiler.h \ - -o $$@ \ + $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ + $(AGESA_INC) \ + -include $(src)/include/kconfig.h \ + -include $(src)/include/rules.h \ + -include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h \ + -o $$@ \ $(agesa_src_path)/$(notdir $1) endef diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 066ef3495c..d8ad959f0d 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -113,8 +113,8 @@ TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool TOOLCPPFLAGS += -I$(objutil)/cbfstool -TOOLCPPFLAGS += -I$(top)/src/commonlib/include -TOOLCPPFLAGS += -include $(top)/src/commonlib/include/commonlib/compiler.h +TOOLCPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include +TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/include TOOLCPPFLAGS += -I$(VBOOT_SOURCE)/firmware/2lib/include # UEFI header file support. It's not pretty, but that's what we currently @@ -163,6 +163,10 @@ $(objutil)/cbfstool/%.o: $(top)/src/commonlib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< +$(objutil)/cbfstool/%.o: $(top)/src/commonlib/bsd/%.c + printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< + $(objutil)/cbfstool/%.o: $(top)/util/cbfstool/lz4/lib/%.c printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) $(TOOLCPPFLAGS) $(TOOLCFLAGS) $(HOSTCFLAGS) -c -o $@ $< diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 6071437d05..be920b4598 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -26,7 +26,7 @@ #include "cbfs.h" #include "rmodule.h" -#include +#include /* Checks if program segment contains the ignored section */ static int is_phdr_ignored(Elf64_Phdr *phdr, Elf64_Shdr *shdr) diff --git a/util/cbfstool/compress.c b/util/cbfstool/compress.c index a6a0df4dd1..993809426f 100644 --- a/util/cbfstool/compress.c +++ b/util/cbfstool/compress.c @@ -23,7 +23,7 @@ #include #include "common.h" #include "lz4/lib/lz4frame.h" -#include +#include static int lz4_compress(char *in, int in_len, char *out, int *out_len) { diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile index 55a4e10402..56445d8ad5 100644 --- a/util/cbmem/Makefile +++ b/util/cbmem/Makefile @@ -20,8 +20,8 @@ INSTALL ?= /usr/bin/env install PREFIX ?= /usr/local CFLAGS ?= -O2 CFLAGS += -Wall -Wextra -Wmissing-prototypes -Werror -CPPFLAGS += -I . -I $(ROOT)/commonlib/include -CPPFLAGS += -include commonlib/compiler.h +CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include +CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h OBJS = $(PROGRAM).o diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile index a4f0af6217..50c6c30650 100644 --- a/util/ifdtool/Makefile +++ b/util/ifdtool/Makefile @@ -19,9 +19,9 @@ CC = gcc INSTALL = /usr/bin/env install PREFIX = /usr/local CFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror -CFLAGS += -I../../src/commonlib/include +CFLAGS += -I../../src/commonlib/include -I../../src/commonlib/bsd/include CFLAGS += -I../cbfstool/flashmap -CFLAGS += -include ../../src/commonlib/include/commonlib/compiler.h +CFLAGS += -include ../../src/commonlib/bsd/include/commonlib/bsd/compiler.h LDFLAGS = OBJS = ifdtool.o diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index cd02fa8abe..23ea8a6ee6 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -25,7 +25,8 @@ PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -Wextra -Wmissing-prototypes LDFLAGS += -lpci -lz -CPPFLAGS += -I$(top)/src/commonlib/include +CPPFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include + OBJS = inteltool.o pcr.o cpu.o gpio.o gpio_groups.o rootcmplx.o powermgt.o \ memory.o pcie.o amb.o ivy_memory.o spi.o gfx.o ahci.o \ diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile index fb9aadefda..57f2627e49 100644 --- a/util/intelvbttool/Makefile +++ b/util/intelvbttool/Makefile @@ -17,7 +17,7 @@ PROGRAM = intelvbttool CC ?= gcc CFLAGS ?= -O2 -g CFLAGS += -Wall -Werror -CFLAGS += -I../../src/commonlib/include +CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include all: $(PROGRAM) diff --git a/util/sconfig/Makefile.inc b/util/sconfig/Makefile.inc index c47b43956d..b821f06f11 100644 --- a/util/sconfig/Makefile.inc +++ b/util/sconfig/Makefile.inc @@ -4,7 +4,7 @@ sconfigobj += sconfig.tab.o sconfigobj += main.o SCONFIGFLAGS += -I$(top)/util/sconfig -I$(objutil)/sconfig -SCONFIGFLAGS += -I$(top)/src/commonlib/include +SCONFIGFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include $(objutil)/sconfig: mkdir -p $@ From fc7b953366b776aa3eaaf0539af06086facda14e Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 23 Jan 2020 11:45:30 -0700 Subject: [PATCH 002/151] drivers/spi/spi_flash: remove spi flash names The names of each spi flash cause quite a bit of bloat in the text size of each stage/program. Remove the name entirely from spi flash in order to reduce overhead. In order to pack space as closely as possible the previous 32-bit id and mask were split into 2 16-bit ids and masks. On Chrome OS build of Aleena there's a savings of >2.21KiB in each of verstage, romstage, and ramstage. Change-Id: Ie98f7e1c7d116c5d7b4bf78605f62fee89dee0a5 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38380 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/drivers/spi/adesto.c | 50 ++++---- src/drivers/spi/amic.c | 38 +++--- src/drivers/spi/atmel.c | 30 ++--- src/drivers/spi/eon.c | 86 +++++++------- src/drivers/spi/gigadevice.c | 54 ++++----- src/drivers/spi/macronix.c | 78 ++++++------ src/drivers/spi/spansion.c | 65 +++++----- src/drivers/spi/spi_flash.c | 25 ++-- src/drivers/spi/spi_flash_internal.h | 12 +- src/drivers/spi/sst.c | 52 ++++---- src/drivers/spi/stmicro.c | 112 +++++++++--------- src/drivers/spi/winbond.c | 82 ++++++------- src/include/spi_flash.h | 1 - .../common/block/fast_spi/fast_spi_flash.c | 1 - src/soc/mediatek/mt8173/flash_controller.c | 1 - src/southbridge/intel/common/spi.c | 1 - 16 files changed, 349 insertions(+), 339 deletions(-) diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 89e33f78ef..fe4106afd0 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -41,63 +41,63 @@ static const struct spi_flash_part_id flash_table[] = { { - .id = 0x4218, - .name = "AT25SL128A", + /* AT25SL128A */ + .id[0] = 0x4218, .nr_sectors_shift = 12, }, { - .id = 0x4501, - .name = "AT25DF081A", /* Yes, 81A id < 81 */ + /* AT25DF081A Yes, 81A id < 81 */ + .id[0] = 0x4501, .nr_sectors_shift = 8, }, { - .id = 0x4502, - .name = "AT25DF081", + /* AT25DF081 */ + .id[0] = 0x4502, .nr_sectors_shift = 8, }, { - .id = 0x4602, - .name = "AT25DF161", + /* AT25DF161 */ + .id[0] = 0x4602, .nr_sectors_shift = 9, }, { - .id = 0x4603, - .name = "AT25DL161", + /* AT25DL161 */ + .id[0] = 0x4603, .nr_sectors_shift = 9, }, { - .id = 0x4700, - .name = "AT25DF321", + /* AT25DF321 */ + .id[0] = 0x4700, .nr_sectors_shift = 10, }, { - .id = 0x4701, - .name = "AT25DF321A", + /* AT25DF321A */ + .id[0] = 0x4701, .nr_sectors_shift = 10, }, { - .id = 0x4800, - .name = "AT25DF641", + /* AT25DF641 */ + .id[0] = 0x4800, .nr_sectors_shift = 11, }, { - .id = 0x8501, - .name = "AT25SF081", + /* AT25SF081 */ + .id[0] = 0x8501, .nr_sectors_shift = 8, }, { - .id = 0x8600, - .name = "AT25DQ161", + /* AT25DQ161 */ + .id[0] = 0x8600, .nr_sectors_shift = 9, }, { - .id = 0x8601, - .name = "AT25SF161", + /* AT25SF161 */ + .id[0] = 0x8601, .nr_sectors_shift = 9, }, { - .id = 0x8700, - .name = "AT25DQ321", + /* AT25DQ321 */ + .id[0] = 0x8700, .nr_sectors_shift = 10, }, }; @@ -106,7 +106,7 @@ const struct spi_flash_vendor_info spi_flash_adesto_vi = { .id = VENDOR_ID_ADESTO, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 8e25cd933c..cb4ada01ce 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -36,48 +36,48 @@ static const struct spi_flash_part_id flash_table[] = { { - .id = 0x2015, - .name = "A25L16PU", + /* A25L16PU */ + .id[0] = 0x2015, .nr_sectors_shift = 9, }, { - .id = 0x2025, - .name = "A25L16PT", + /* A25L16PT */ + .id[0] = 0x2025, .nr_sectors_shift = 9, }, { - .id = 0x3014, - .name = "A25L080", + /* A25L080 */ + .id[0] = 0x3014, .nr_sectors_shift = 8, }, { - .id = 0x3015, - .name = "A25L016", + /* A25L016 */ + .id[0] = 0x3015, .nr_sectors_shift = 9, }, { - .id = 0x3016, - .name = "A25L032", + /* A25L032 */ + .id[0] = 0x3016, .nr_sectors_shift = 10, }, { - .id = 0x4014, - .name = "A25LQ080", + /* A25LQ080 */ + .id[0] = 0x4014, .nr_sectors_shift = 8, }, { - .id = 0x4015, - .name = "A25LQ16", + /* A25LQ16 */ + .id[0] = 0x4015, .nr_sectors_shift = 9, }, { - .id = 0x4016, - .name = "A25LQ032", + /* A25LQ032 */ + .id[0] = 0x4016, .nr_sectors_shift = 10, }, { - .id = 0x4017, - .name = "A25LQ64", + /* A25LQ64 */ + .id[0] = 0x4017, .nr_sectors_shift = 11, }, }; @@ -86,7 +86,7 @@ const struct spi_flash_vendor_info spi_flash_amic_vi = { .id = VENDOR_ID_AMIC, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/atmel.c b/src/drivers/spi/atmel.c index ae282c323b..491a7ab04e 100644 --- a/src/drivers/spi/atmel.c +++ b/src/drivers/spi/atmel.c @@ -36,38 +36,38 @@ static const struct spi_flash_part_id flash_table[] = { { - .id = 0x3015, - .name = "AT25X16", + /* AT25X16 */ + .id[0] = 0x3015, .nr_sectors_shift = 9, }, { - .id = 0x47, - .name = "AT25DF32", + /* AT25DF32 */ + .id[0] = 0x47, .nr_sectors_shift = 10, }, { - .id = 0x3017, - .name = "AT25X64", + /* AT25X64 */ + .id[0] = 0x3017, .nr_sectors_shift = 11, }, { - .id = 0x4015, - .name = "AT25Q16", + /* AT25Q16 */ + .id[0] = 0x4015, .nr_sectors_shift = 9, }, { - .id = 0x4016, - .name = "AT25Q32", + /* AT25Q32 */ + .id[0] = 0x4016, .nr_sectors_shift = 10, }, { - .id = 0x4017, - .name = "AT25Q64", + /* AT25Q64 */ + .id[0] = 0x4017, .nr_sectors_shift = 11, }, { - .id = 0x4018, - .name = "AT25Q128", + /* AT25Q128 */ + .id[0] = 0x4018, .nr_sectors_shift = 12, }, }; @@ -76,7 +76,7 @@ const struct spi_flash_vendor_info spi_flash_atmel_vi = { .id = VENDOR_ID_ATMEL, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c index 6d4833ce22..706115a18c 100644 --- a/src/drivers/spi/eon.c +++ b/src/drivers/spi/eon.c @@ -57,108 +57,108 @@ static const struct spi_flash_part_id flash_table[] = { { - .id = EON_ID_EN25B80, - .name = "EN25B80", + /* EN25B80 */ + .id[0] = EON_ID_EN25B80, .nr_sectors_shift = 8, }, { - .id = EON_ID_EN25B16, - .name = "EN25B16", + /* EN25B16 */ + .id[0] = EON_ID_EN25B16, .nr_sectors_shift = 9, }, { - .id = EON_ID_EN25B32, - .name = "EN25B32", + /* EN25B32 */ + .id[0] = EON_ID_EN25B32, .nr_sectors_shift = 10, }, { - .id = EON_ID_EN25B64, - .name = "EN25B64", + /* EN25B64 */ + .id[0] = EON_ID_EN25B64, .nr_sectors_shift = 11, }, { - .id = EON_ID_EN25F80, - .name = "EN25F80", + /* EN25F80 */ + .id[0] = EON_ID_EN25F80, .nr_sectors_shift = 8, }, { - .id = EON_ID_EN25F16, - .name = "EN25F16", + /* EN25F16 */ + .id[0] = EON_ID_EN25F16, .nr_sectors_shift = 9, }, { - .id = EON_ID_EN25F32, - .name = "EN25F32", + /* EN25F32 */ + .id[0] = EON_ID_EN25F32, .nr_sectors_shift = 10, }, { - .id = EON_ID_EN25F64, - .name = "EN25F64", + /* EN25F64 */ + .id[0] = EON_ID_EN25F64, .nr_sectors_shift = 11, }, { - .id = EON_ID_EN25Q80, - .name = "EN25Q80(A)", + /* EN25Q80(A) */ + .id[0] = EON_ID_EN25Q80, .nr_sectors_shift = 8, }, { - .id = EON_ID_EN25Q16, - .name = "EN25Q16(D16)", + /* EN25Q16(D16) */ + .id[0] = EON_ID_EN25Q16, .nr_sectors_shift = 9, }, { - .id = EON_ID_EN25Q32, - .name = "EN25Q32(A/B)", + /* EN25Q32(A/B) */ + .id[0] = EON_ID_EN25Q32, .nr_sectors_shift = 10, }, { - .id = EON_ID_EN25Q64, - .name = "EN25Q64", + /* EN25Q64 */ + .id[0] = EON_ID_EN25Q64, .nr_sectors_shift = 11, }, { - .id = EON_ID_EN25Q128, - .name = "EN25Q128", + /* EN25Q128 */ + .id[0] = EON_ID_EN25Q128, .nr_sectors_shift = 12, }, { - .id = EON_ID_EN25QH16, - .name = "EN25QH16", + /* EN25QH16 */ + .id[0] = EON_ID_EN25QH16, .nr_sectors_shift = 9, }, { - .id = EON_ID_EN25QH32, - .name = "EN25QH32", + /* EN25QH32 */ + .id[0] = EON_ID_EN25QH32, .nr_sectors_shift = 10, }, { - .id = EON_ID_EN25QH64, - .name = "EN25QH64", + /* EN25QH64 */ + .id[0] = EON_ID_EN25QH64, .nr_sectors_shift = 11, }, { - .id = EON_ID_EN25QH128, - .name = "EN25QH128", + /* EN25QH128 */ + .id[0] = EON_ID_EN25QH128, .nr_sectors_shift = 12, }, { - .id = EON_ID_EN25S80, - .name = "EN25S80", + /* EN25S80 */ + .id[0] = EON_ID_EN25S80, .nr_sectors_shift = 8, }, { - .id = EON_ID_EN25S16, - .name = "EN25S16", + /* EN25S16 */ + .id[0] = EON_ID_EN25S16, .nr_sectors_shift = 9, }, { - .id = EON_ID_EN25S32, - .name = "EN25S32", + /* EN25S32 */ + .id[0] = EON_ID_EN25S32, .nr_sectors_shift = 10, }, { - .id = EON_ID_EN25S64, - .name = "EN25S64", + /* EN25S64 */ + .id[0] = EON_ID_EN25S64, .nr_sectors_shift = 11, }, }; @@ -167,7 +167,7 @@ const struct spi_flash_vendor_info spi_flash_eon_vi = { .id = VENDOR_ID_EON, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 64d9706551..717b01613f 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -36,79 +36,79 @@ static const struct spi_flash_part_id flash_table[] = { { - .id = 0x3114, - .name = "GD25T80", + /* GD25T80 */ + .id[0] = 0x3114, .nr_sectors_shift = 8, }, { - .id = 0x4014, - .name = "GD25Q80", + /* GD25Q80 */ + .id[0] = 0x4014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, }, /* also GD25Q80B */ { - .id = 0x4015, - .name = "GD25Q16", + /* GD25Q16 */ + .id[0] = 0x4015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, }, /* also GD25Q16B */ { - .id = 0x4016, - .name = "GD25Q32B", + /* GD25Q32B */ + .id[0] = 0x4016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, }, /* also GD25Q32B */ { - .id = 0x4017, - .name = "GD25Q64", + /* GD25Q64 */ + .id[0] = 0x4017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, }, /* also GD25Q64B, GD25B64C */ { - .id = 0x4018, - .name = "GD25Q128", + /* GD25Q128 */ + .id[0] = 0x4018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, }, /* also GD25Q128B */ { - .id = 0x4214, - .name = "GD25VQ80C", + /* GD25VQ80C */ + .id[0] = 0x4214, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, }, { - .id = 0x4215, - .name = "GD25VQ16C", + /* GD25VQ16C */ + .id[0] = 0x4215, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, }, { - .id = 0x6014, - .name = "GD25LQ80", + /* GD25LQ80 */ + .id[0] = 0x6014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, }, { - .id = 0x6015, - .name = "GD25LQ16", + /* GD25LQ16 */ + .id[0] = 0x6015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, }, { - .id = 0x6016, - .name = "GD25LQ32", + /* GD25LQ32 */ + .id[0] = 0x6016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, }, { - .id = 0x6017, - .name = "GD25LQ64C", + /* GD25LQ64C */ + .id[0] = 0x6017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, }, /* also GD25LB64C */ { - .id = 0x6018, - .name = "GD25LQ128", + /* GD25LQ128 */ + .id[0] = 0x6018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, }, @@ -118,7 +118,7 @@ const struct spi_flash_vendor_info spi_flash_gigadevice_vi = { .id = VENDOR_ID_GIGADEVICE, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index f23b421211..0c5bf14814 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -38,98 +38,98 @@ static const struct spi_flash_part_id flash_table[] = { { - .id = 0x2014, - .name = "MX25L8005", + /* MX25L8005 */ + .id[0] = 0x2014, .nr_sectors_shift = 8, }, { - .id = 0x2015, - .name = "MX25L1605D", + /* MX25L1605D */ + .id[0] = 0x2015, .nr_sectors_shift = 9, }, { - .id = 0x2016, - .name = "MX25L3205D", + /* MX25L3205D */ + .id[0] = 0x2016, .nr_sectors_shift = 10, }, { - .id = 0x2017, - .name = "MX25L6405D", + /* MX25L6405D */ + .id[0] = 0x2017, .nr_sectors_shift = 11, }, { - .id = 0x2018, - .name = "MX25L12805D", + /* MX25L12805D */ + .id[0] = 0x2018, .nr_sectors_shift = 12, }, { - .id = 0x2019, - .name = "MX25L25635F", + /* MX25L25635F */ + .id[0] = 0x2019, .nr_sectors_shift = 13, }, { - .id = 0x201a, - .name = "MX66L51235F", + /* MX66L51235F */ + .id[0] = 0x201a, .nr_sectors_shift = 14, }, { - .id = 0x2415, - .name = "MX25L1635D", + /* MX25L1635D */ + .id[0] = 0x2415, .nr_sectors_shift = 9, }, { - .id = 0x2515, - .name = "MX25L1635E", + /* MX25L1635E */ + .id[0] = 0x2515, .nr_sectors_shift = 9, }, { - .id = 0x2534, - .name = "MX25U8032E", + /* MX25U8032E */ + .id[0] = 0x2534, .nr_sectors_shift = 8, }, { - .id = 0x2535, - .name = "MX25U1635E", + /* MX25U1635E */ + .id[0] = 0x2535, .nr_sectors_shift = 9, }, { - .id = 0x2536, - .name = "MX25U3235E", + /* MX25U3235E */ + .id[0] = 0x2536, .nr_sectors_shift = 10, }, { - .id = 0x2537, - .name = "MX25U6435F", + /* MX25U6435F */ + .id[0] = 0x2537, .nr_sectors_shift = 11, }, { - .id = 0x2538, - .name = "MX25U12835F", + /* MX25U12835F */ + .id[0] = 0x2538, .nr_sectors_shift = 12, }, { - .id = 0x2539, - .name = "MX25U25635F", + /* MX25U25635F */ + .id[0] = 0x2539, .nr_sectors_shift = 13, }, { - .id = 0x253a, - .name = "MX25U51245G", + /* MX25U51245G */ + .id[0] = 0x253a, .nr_sectors_shift = 14, }, { - .id = 0x2618, - .name = "MX25L12855E", + /* MX25L12855E */ + .id[0] = 0x2618, .nr_sectors_shift = 12, }, { - .id = 0x5e16, - .name = "MX25L3235D", /* MX25L3225D/MX25L3236D/MX25L3237D */ + /* MX25L3235D/MX25L3225D/MX25L3236D/MX25L3237D */ + .id[0] = 0x5e16, .nr_sectors_shift = 10, }, { - .id = 0x9517, - .name = "MX25L6495F", + /* MX25L6495F */ + .id[0] = 0x9517, .nr_sectors_shift = 11, }, }; @@ -138,7 +138,7 @@ const struct spi_flash_vendor_info spi_flash_macronix_vi = { .id = VENDOR_ID_MACRONIX, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c index c694f4517e..29b7027b65 100644 --- a/src/drivers/spi/spansion.c +++ b/src/drivers/spi/spansion.c @@ -51,74 +51,79 @@ static const struct spi_flash_part_id flash_table_ext[] = { { - .id = SPSN_ID_S25FL008A, - .name = "S25FL008A", + /* S25FL008A */ + .id[0] = SPSN_ID_S25FL008A, .nr_sectors_shift = 4, }, { - .id = SPSN_ID_S25FL016A, - .name = "S25FL016A", + /* S25FL016A */ + .id[0] = SPSN_ID_S25FL016A, .nr_sectors_shift = 5, }, { - .id = SPSN_ID_S25FL032A, - .name = "S25FL032A", + /* S25FL032A */ + .id[0] = SPSN_ID_S25FL032A, .nr_sectors_shift = 6, }, { - .id = SPSN_ID_S25FL064A, - .name = "S25FL064A", + /* S25FL064A */ + .id[0] = SPSN_ID_S25FL064A, .nr_sectors_shift = 7, }, { - .id = (SPSN_EXT_ID_S25FL128P_64KB << 16) | SPSN_ID_S25FL128P, - .name = "S25FL128P_64K", + /* S25FL128P_64K */ + .id[0] = SPSN_ID_S25FL128P, + .id[1] = SPSN_EXT_ID_S25FL128P_64KB, .nr_sectors_shift = 8, }, { - .id = (SPSN_EXT_ID_S25FLXXS_64KB << 16) | SPSN_ID_S25FL128S, - .name = "S25FL128S_256K", + /* S25FL128S_256K */ + .id[0] = SPSN_ID_S25FL128S, + .id[1] = SPSN_EXT_ID_S25FLXXS_64KB, .nr_sectors_shift = 9, }, { - .id = (SPSN_EXT_ID_S25FL032P << 16) | SPSN_ID_S25FL032A, - .name = "S25FL032P", + /* S25FL032P */ + .id[0] = SPSN_ID_S25FL032A, + .id[1] = SPSN_EXT_ID_S25FL032P, .nr_sectors_shift = 6, }, { - .id = (SPSN_EXT_ID_S25FLXXS_64KB << 16) | SPSN_ID_S25FL128P, - .name = "S25FS128S", + /* S25FS128S */ + .id[0] = SPSN_ID_S25FL128P, + .id[1] = SPSN_EXT_ID_S25FLXXS_64KB, .nr_sectors_shift = 8, }, }; static const struct spi_flash_part_id flash_table_256k_sector[] = { { - .id = (SPSN_EXT_ID_S25FL128P_256KB << 16) | SPSN_ID_S25FL128P, - .name = "S25FL128P_256K", + /* S25FL128P_256K */ + .id[0] = SPSN_ID_S25FL128P, + .id[1] = SPSN_EXT_ID_S25FL128P_256KB, .nr_sectors_shift = 6, }, }; static const struct spi_flash_part_id flash_table[] = { { - .id = SPSN_ID_S25FL208K, - .name = "S25FL208K", + /* S25FL208K */ + .id[0] = SPSN_ID_S25FL208K, .nr_sectors_shift = 4, }, { - .id = SPSN_ID_S25FL116K, - .name = "S25FL116K_16M", + /* S25FL116K_16M */ + .id[0] = SPSN_ID_S25FL116K, .nr_sectors_shift = 5, }, { - .id = SPSN_ID_S25FL132K, - .name = "S25FL132K", + /* S25FL132K */ + .id[0] = SPSN_ID_S25FL132K, .nr_sectors_shift = 6, }, { - .id = SPSN_ID_S25FL164K, - .name = "S25FL164K", + /* S25FL164K */ + .id[0] = SPSN_ID_S25FL164K, .nr_sectors_shift = 7, }, }; @@ -127,7 +132,8 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext1_vi = { .id = VENDOR_ID_SPANSION, .page_size_shift = 8, .sector_size_kib_shift = 6, - .match_id_mask = 0xffffffff, + .match_id_mask[0] = 0xffff, + .match_id_mask[1] = 0xffff, .ids = flash_table_ext, .nr_part_ids = ARRAY_SIZE(flash_table_ext), .desc = &spi_flash_pp_0xd8_sector_desc, @@ -137,7 +143,8 @@ const struct spi_flash_vendor_info spi_flash_spansion_ext2_vi = { .id = VENDOR_ID_SPANSION, .page_size_shift = 8, .sector_size_kib_shift = 8, - .match_id_mask = 0xffffffff, + .match_id_mask[0] = 0xffff, + .match_id_mask[1] = 0xffff, .ids = flash_table_256k_sector, .nr_part_ids = ARRAY_SIZE(flash_table_256k_sector), .desc = &spi_flash_pp_0xd8_sector_desc, @@ -147,7 +154,7 @@ const struct spi_flash_vendor_info spi_flash_spansion_vi = { .id = VENDOR_ID_SPANSION, .page_size_shift = 8, .sector_size_kib_shift = 6, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0xd8_sector_desc, diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 90dd5877ff..51498296d6 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -355,8 +355,7 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash, { memcpy(&flash->spi, spi, sizeof(*spi)); flash->vendor = vi->id; - flash->model = part->id; - flash->name = part->name; + flash->model = part->id[0]; flash->page_size = 1U << vi->page_size_shift; flash->sector_size = (1U << vi->sector_size_kib_shift) * KiB; @@ -379,14 +378,19 @@ static int fill_spi_flash(const struct spi_slave *spi, struct spi_flash *flash, } static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_info *vi, - uint32_t id) + uint16_t id[2]) { size_t i; + const uint16_t lid[2] = { + [0] = id[0] & vi->match_id_mask[0], + [1] = id[1] & vi->match_id_mask[1], + }; + for (i = 0; i < vi->nr_part_ids; i++) { const struct spi_flash_part_id *part = &vi->ids[i]; - if (part->id == id) + if (part->id[0] == lid[0] && part->id[1] == lid[1]) return part; } @@ -394,7 +398,7 @@ static const struct spi_flash_part_id *find_part(const struct spi_flash_vendor_i } static int find_match(const struct spi_slave *spi, struct spi_flash *flash, - uint8_t manuf_id, uint32_t id) + uint8_t manuf_id, uint16_t id[2]) { int i; @@ -407,7 +411,7 @@ static int find_match(const struct spi_slave *spi, struct spi_flash *flash, if (manuf_id != vi->id) continue; - part = find_part(vi, id & vi->match_id_mask); + part = find_part(vi, id); if (part == NULL) continue; @@ -424,7 +428,7 @@ int spi_flash_generic_probe(const struct spi_slave *spi, int ret, i; u8 idcode[IDCODE_LEN]; u8 manuf_id; - u32 id; + u16 id[2]; /* Read the ID codes */ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); @@ -450,7 +454,8 @@ int spi_flash_generic_probe(const struct spi_slave *spi, manuf_id = idcode[0]; } - id = (idcode[3] << 24) | (idcode[4] << 16) | (idcode[1] << 8) | idcode[2]; + id[0] = (idcode[1] << 8) | idcode[2]; + id[1] = (idcode[3] << 8) | idcode[4]; return find_match(spi, flash, manuf_id, id); } @@ -483,8 +488,8 @@ int spi_flash_probe(unsigned int bus, unsigned int cs, struct spi_flash *flash) if (flash->flags.dual_spi && spi.ctrlr->xfer_dual) mode_string = " (Dual SPI mode)"; printk(BIOS_INFO, - "SF: Detected %s with sector size 0x%x, total 0x%x%s\n", - flash->name, flash->sector_size, flash->size, mode_string); + "SF: Detected %02x %04x with sector size 0x%x, total 0x%x%s\n", + flash->vendor, flash->model, flash->sector_size, flash->size, mode_string); if (bus == CONFIG_BOOT_DEVICE_SPI_FLASH_BUS && flash->size != CONFIG_ROM_SIZE) { printk(BIOS_ERR, "SF size 0x%x does not correspond to" diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index bd52d66075..0842961be7 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -73,10 +73,12 @@ int spi_flash_cmd_read(const struct spi_flash *flash, u32 offset, size_t len, vo int stmicro_release_deep_sleep_identify(const struct spi_slave *spi, u8 *idcode); struct spi_flash_part_id { - /* rdid command constructs a 32-bit id using the following method - * for matching: 31 | id[3] | id[4] | id[1] | id[2] | 0 */ - uint32_t id; - const char *name; + /* rdid command constructs 2x 16-bit id using the following method + * for matching after reading 5 bytes (1st byte is manuf id): + * id[0] = (id[1] << 8) | id[2] + * id[1] = (id[3] << 8) | id[4] + */ + uint16_t id[2]; /* Log based 2 total number of sectors. */ uint16_t nr_sectors_shift: 4; uint16_t fast_read_dual_output_support : 1; @@ -104,7 +106,7 @@ struct spi_flash_vendor_info { uint8_t sector_size_kib_shift : 4; uint16_t nr_part_ids; const struct spi_flash_part_id *ids; - uint32_t match_id_mask; /* matching bytes of the id for this set*/ + uint16_t match_id_mask[2]; /* matching bytes of the id for this set*/ const struct spi_flash_ops_descriptor *desc; const struct spi_flash_protection_ops *prot_ops; /* Returns 0 on success. !0 otherwise. */ diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c index 559f30f022..4b25b902f1 100644 --- a/src/drivers/spi/sst.c +++ b/src/drivers/spi/sst.c @@ -46,56 +46,56 @@ static const struct spi_flash_part_id flash_table_ai[] = { { - .id = 0x8d, - .name = "SST25VF040B", + /* SST25VF040B */ + .id[0] = 0x8d, .nr_sectors_shift = 7, },{ - .id = 0x8e, - .name = "SST25VF080B", + /* SST25VF080B */ + .id[0] = 0x8e, .nr_sectors_shift = 8, },{ - .id = 0x80, - .name = "SST25VF080", + /* SST25VF080 */ + .id[0] = 0x80, .nr_sectors_shift = 8, },{ - .id = 0x41, - .name = "SST25VF016B", + /* SST25VF016B */ + .id[0] = 0x41, .nr_sectors_shift = 9, },{ - .id = 0x4a, - .name = "SST25VF032B", + /* SST25VF032B */ + .id[0] = 0x4a, .nr_sectors_shift = 10, },{ - .id = 0x01, - .name = "SST25WF512", + /* SST25WF512 */ + .id[0] = 0x01, .nr_sectors_shift = 4, },{ - .id = 0x02, - .name = "SST25WF010", + /* SST25WF010 */ + .id[0] = 0x02, .nr_sectors_shift = 5, },{ - .id = 0x03, - .name = "SST25WF020", + /* SST25WF020 */ + .id[0] = 0x03, .nr_sectors_shift = 6, },{ - .id = 0x04, - .name = "SST25WF040", + /* SST25WF040 */ + .id[0] = 0x04, .nr_sectors_shift = 7, },{ - .id = 0x05, - .name = "SST25WF080", + /* SST25WF080 */ + .id[0] = 0x05, .nr_sectors_shift = 8, },{ - .id = 0x14, - .name = "SST25WF080B", + /* SST25WF080B */ + .id[0] = 0x14, .nr_sectors_shift = 8, }, }; static const struct spi_flash_part_id flash_table_pp256[] = { { - .id = 0x4b, - .name = "SST25VF064C", + /* SST25VF064C */ + .id[0] = 0x4b, .nr_sectors_shift = 11, }, }; @@ -254,7 +254,7 @@ static const struct spi_flash_ops_descriptor descai = { const struct spi_flash_vendor_info spi_flash_sst_ai_vi = { .id = VENDOR_ID_SST, .sector_size_kib_shift = 2, - .match_id_mask = 0xff, + .match_id_mask[0] = 0xff, .ids = flash_table_ai, .nr_part_ids = ARRAY_SIZE(flash_table_ai), .desc = &descai, @@ -265,7 +265,7 @@ const struct spi_flash_vendor_info spi_flash_sst_vi = { .id = VENDOR_ID_SST, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xff, + .match_id_mask[0] = 0xff, .ids = flash_table_pp256, .nr_part_ids = ARRAY_SIZE(flash_table_pp256), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 62755f4a01..e867d71450 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -66,142 +66,142 @@ static const struct spi_flash_part_id flash_table_se32k[] = { { - .id = STM_ID_M25P10, - .name = "M25P10", + /* M25P10 */ + .id[0] = STM_ID_M25P10, .nr_sectors_shift = 2, }, }; static const struct spi_flash_part_id flash_table_se64k[] = { { - .id = STM_ID_M25P16, - .name = "M25P16", + /* M25P16 */ + .id[0] = STM_ID_M25P16, .nr_sectors_shift = 5, }, { - .id = STM_ID_M25P20, - .name = "M25P20", + /* M25P20 */ + .id[0] = STM_ID_M25P20, .nr_sectors_shift = 2, }, { - .id = STM_ID_M25P32, - .name = "M25P32", + /* M25P32 */ + .id[0] = STM_ID_M25P32, .nr_sectors_shift = 6, }, { - .id = STM_ID_M25P40, - .name = "M25P40", + /* M25P40 */ + .id[0] = STM_ID_M25P40, .nr_sectors_shift = 3, }, { - .id = STM_ID_M25P64, - .name = "M25P64", + /* M25P64 */ + .id[0] = STM_ID_M25P64, .nr_sectors_shift = 7, }, { - .id = STM_ID_M25P80, - .name = "M25P80", + /* M25P80 */ + .id[0] = STM_ID_M25P80, .nr_sectors_shift = 4, }, { - .id = STM_ID_M25PX80, - .name = "M25PX80", + /* M25PX80 */ + .id[0] = STM_ID_M25PX80, .nr_sectors_shift = 4, }, { - .id = STM_ID_M25PX16, - .name = "M25PX16", + /* M25PX16 */ + .id[0] = STM_ID_M25PX16, .nr_sectors_shift = 5, }, { - .id = STM_ID_M25PX32, - .name = "M25PX32", + /* M25PX32 */ + .id[0] = STM_ID_M25PX32, .nr_sectors_shift = 6, }, { - .id = STM_ID_M25PX64, - .name = "M25PX64", + /* M25PX64 */ + .id[0] = STM_ID_M25PX64, .nr_sectors_shift = 7, }, { - .id = STM_ID_M25PE80, - .name = "M25PE80", + /* M25PE80 */ + .id[0] = STM_ID_M25PE80, .nr_sectors_shift = 4, }, { - .id = STM_ID_M25PE16, - .name = "M25PE16", + /* M25PE16 */ + .id[0] = STM_ID_M25PE16, .nr_sectors_shift = 5, }, { - .id = STM_ID_M25PE32, - .name = "M25PE32", + /* M25PE32 */ + .id[0] = STM_ID_M25PE32, .nr_sectors_shift = 6, }, { - .id = STM_ID_M25PE64, - .name = "M25PE64", + /* M25PE64 */ + .id[0] = STM_ID_M25PE64, .nr_sectors_shift = 7, }, }; static const struct spi_flash_part_id flash_table_se256k[] = { { - .id = STM_ID_M25P128, - .name = "M25P128", + /* M25P128 */ + .id[0] = STM_ID_M25P128, .nr_sectors_shift = 6, }, }; static const struct spi_flash_part_id flash_table_sse[] = { { - .id = STM_ID_N25Q016__3E, - .name = "N25Q016..3E", + /* N25Q016..3E */ + .id[0] = STM_ID_N25Q016__3E, .nr_sectors_shift = 9, }, { - .id = STM_ID_N25Q032__3E, - .name = "N25Q032..3E", + /* N25Q032..3E */ + .id[0] = STM_ID_N25Q032__3E, .nr_sectors_shift = 10, }, { - .id = STM_ID_N25Q064__3E, - .name = "N25Q064..3E", + /* N25Q064..3E */ + .id[0] = STM_ID_N25Q064__3E, .nr_sectors_shift = 11, }, { - .id = STM_ID_N25Q128__3E, - .name = "N25Q128..3E", + /* N25Q128..3E */ + .id[0] = STM_ID_N25Q128__3E, .nr_sectors_shift = 12, }, { - .id = STM_ID_N25Q256__3E, - .name = "N25Q256..3E", + /* N25Q256..3E */ + .id[0] = STM_ID_N25Q256__3E, .nr_sectors_shift = 13, }, { - .id = STM_ID_N25Q016__1E, - .name = "N25Q016..1E", + /* N25Q016..1E */ + .id[0] = STM_ID_N25Q016__1E, .nr_sectors_shift = 9, }, { - .id = STM_ID_N25Q032__1E, - .name = "N25Q032..1E", + /* N25Q032..1E */ + .id[0] = STM_ID_N25Q032__1E, .nr_sectors_shift = 10, }, { - .id = STM_ID_N25Q064__1E, - .name = "N25Q064..1E", + /* N25Q064..1E */ + .id[0] = STM_ID_N25Q064__1E, .nr_sectors_shift = 11, }, { - .id = STM_ID_N25Q128__1E, - .name = "N25Q128..1E", + /* N25Q128..1E */ + .id[0] = STM_ID_N25Q128__1E, .nr_sectors_shift = 12, }, { - .id = STM_ID_N25Q256__1E, - .name = "N25Q256..1E", + /* N25Q256..1E */ + .id[0] = STM_ID_N25Q256__1E, .nr_sectors_shift = 13, }, }; @@ -228,7 +228,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro1_vi = { .id = VENDOR_ID_STMICRO, .page_size_shift = 8, .sector_size_kib_shift = 5, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table_se32k, .nr_part_ids = ARRAY_SIZE(flash_table_se32k), .desc = &spi_flash_pp_0xd8_sector_desc, @@ -238,7 +238,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro2_vi = { .id = VENDOR_ID_STMICRO, .page_size_shift = 8, .sector_size_kib_shift = 6, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table_se64k, .nr_part_ids = ARRAY_SIZE(flash_table_se64k), .desc = &spi_flash_pp_0xd8_sector_desc, @@ -248,7 +248,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro3_vi = { .id = VENDOR_ID_STMICRO, .page_size_shift = 8, .sector_size_kib_shift = 8, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table_se256k, .nr_part_ids = ARRAY_SIZE(flash_table_se256k), .desc = &spi_flash_pp_0xd8_sector_desc, @@ -258,7 +258,7 @@ const struct spi_flash_vendor_info spi_flash_stmicro4_vi = { .id = VENDOR_ID_STMICRO, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table_sse, .nr_part_ids = ARRAY_SIZE(flash_table_sse), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e85f59db03..f1aa1c4186 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -81,141 +81,141 @@ struct status_regs { static const struct spi_flash_part_id flash_table[] = { { - .id = 0x2014, - .name = "W25P80", + /* W25P80 */ + .id[0] = 0x2014, .nr_sectors_shift = 8, }, { - .id = 0x2015, - .name = "W25P16", + /* W25P16 */ + .id[0] = 0x2015, .nr_sectors_shift = 9, }, { - .id = 0x2016, - .name = "W25P32", + /* W25P32 */ + .id[0] = 0x2016, .nr_sectors_shift = 10, }, { - .id = 0x3014, - .name = "W25X80", + /* W25X80 */ + .id[0] = 0x3014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, }, { - .id = 0x3015, - .name = "W25X16", + /* W25X16 */ + .id[0] = 0x3015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, }, { - .id = 0x3016, - .name = "W25X32", + /* W25X32 */ + .id[0] = 0x3016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, }, { - .id = 0x3017, - .name = "W25X64", + /* W25X64 */ + .id[0] = 0x3017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, }, { - .id = 0x4014, - .name = "W25Q80_V", + /* W25Q80_V */ + .id[0] = 0x4014, .nr_sectors_shift = 8, .fast_read_dual_output_support = 1, }, { - .id = 0x4015, - .name = "W25Q16_V", + /* W25Q16_V */ + .id[0] = 0x4015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, { - .id = 0x6015, - .name = "W25Q16DW", + /* W25Q16DW */ + .id[0] = 0x6015, .nr_sectors_shift = 9, .fast_read_dual_output_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, { - .id = 0x4016, - .name = "W25Q32_V", + /* W25Q32_V */ + .id[0] = 0x4016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, { - .id = 0x6016, - .name = "W25Q32DW", + /* W25Q32DW */ + .id[0] = 0x6016, .nr_sectors_shift = 10, .fast_read_dual_output_support = 1, .protection_granularity_shift = 16, .bp_bits = 3, }, { - .id = 0x4017, - .name = "W25Q64_V", + /* W25Q64_V */ + .id[0] = 0x4017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, { - .id = 0x6017, - .name = "W25Q64DW", + /* W25Q64DW */ + .id[0] = 0x6017, .nr_sectors_shift = 11, .fast_read_dual_output_support = 1, .protection_granularity_shift = 17, .bp_bits = 3, }, { - .id = 0x4018, - .name = "W25Q128_V", + /* W25Q128_V */ + .id[0] = 0x4018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, { - .id = 0x6018, - .name = "W25Q128FW", + /* W25Q128FW */ + .id[0] = 0x6018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, { - .id = 0x7018, - .name = "W25Q128J", + /* W25Q128J */ + .id[0] = 0x7018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, { - .id = 0x8018, - .name = "W25Q128JW", + /* W25Q128JW */ + .id[0] = 0x8018, .nr_sectors_shift = 12, .fast_read_dual_output_support = 1, .protection_granularity_shift = 18, .bp_bits = 3, }, { - .id = 0x4019, - .name = "W25Q256_V", + /* W25Q256_V */ + .id[0] = 0x4019, .nr_sectors_shift = 13, .fast_read_dual_output_support = 1, .protection_granularity_shift = 16, .bp_bits = 4, }, { - .id = 0x7019, - .name = "W25Q256J", + /* W25Q256J */ + .id[0] = 0x7019, .nr_sectors_shift = 13, .fast_read_dual_output_support = 1, .protection_granularity_shift = 16, @@ -551,7 +551,7 @@ const struct spi_flash_vendor_info spi_flash_winbond_vi = { .id = VENDOR_ID_WINBOND, .page_size_shift = 8, .sector_size_kib_shift = 2, - .match_id_mask = 0xffff, + .match_id_mask[0] = 0xffff, .ids = flash_table, .nr_part_ids = ARRAY_SIZE(flash_table), .desc = &spi_flash_pp_0x20_sector_desc, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 9acff3b104..c74ceaeed4 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -104,7 +104,6 @@ struct spi_flash { }; } flags; u16 model; - const char *name; u32 size; u32 sector_size; u32 page_size; diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c index f887b3c800..f3f4d4fd70 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c @@ -301,7 +301,6 @@ static int fast_spi_flash_probe(const struct spi_slave *dev, flash->size = (flash_bits >> 3) + 1; memcpy(&flash->spi, dev, sizeof(*dev)); - flash->name = "FAST_SPI Hardware Sequencer"; /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ flash->sector_size = 4 * KiB; diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index b491a41efd..9e459834f5 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -240,7 +240,6 @@ int mtk_spi_flash_probe(const struct spi_slave *spi, write32(&mt8173_nor->wrprot, SFLASH_COMMAND_ENABLE); memcpy(&flash->spi, spi, sizeof(*spi)); - flash->name = "mt8173 flash controller"; flash->sector_size = 0x1000; flash->erase_cmd = SECTOR_ERASE_CMD; flash->size = CONFIG_ROM_SIZE; diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 924fdcc810..828520095c 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -932,7 +932,6 @@ static int spi_flash_programmer_probe(const struct spi_slave *spi, return 0; memcpy(&flash->spi, spi, sizeof(*spi)); - flash->name = "Opaque HW-sequencing"; ich_hwseq_set_addr(0); switch ((cntlr.hsfs >> 3) & 3) { From 4b1bfe6d854f27f5a68950be8782555ab09b2fa9 Mon Sep 17 00:00:00 2001 From: Jeff Chase Date: Thu, 16 Jan 2020 16:36:20 -0500 Subject: [PATCH 003/151] mb/google/fizz/variants/endeavour: Enable root ports for TPUs BUG=b:148221635 TEST=build;install;lspci Change-Id: I1732f7fe64ace41a721a2d6a964988efc97b2579 Signed-off-by: Jeff Chase Reviewed-on: https://review.coreboot.org/c/coreboot/+/38550 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../fizz/variants/endeavour/overridetree.cb | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 65b5f73397..861e1b194a 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -1,5 +1,31 @@ chip soc/intel/skylake + # Enable Root port 7(x1) for TPU1 + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # RP 7 uses SRCCLKREQ4# + register "PcieRpClkReqNumber[6]" = "4" + # RP 7, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # RP 7, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # RP 7 uses uses CLK SRC 4 + register "PcieRpClkSrcNumber[6]" = "4" + + # Enable Root port 8(x1) for TPU0 + register "PcieRpEnable[7]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[7]" = "1" + # RP 8 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[7]" = "2" + # RP 8, Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[7]" = "1" + # RP 8, Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[7]" = "1" + # RP 8 uses uses CLK SRC 2 + register "PcieRpClkSrcNumber[7]" = "2" + # Enable Root port 9(x4) for i350 LAN register "PcieRpEnable[8]" = "1" # Disable CLKREQ# @@ -133,6 +159,8 @@ chip soc/intel/skylake device i2c 13 on end end end # I2C #5 + device pci 1c.6 on end # PCI Express Port 7 for TPU1 + device pci 1c.7 on end # PCI Express Port 8 for TPU0 device pci 1d.0 on end # PCI Express Port 9 for POE LAN device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 From 23e73613348f08d7aab3832063c94d0d66cd0bd2 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 23 Jan 2020 00:32:50 -0700 Subject: [PATCH 004/151] mb/google/dedede: Add helper functions to get board_info Add helper functions to get board's sku_id and fw_config. Enable EC_GOOGLE_CHROMEEC_BOARDID to get board_id. Add board's SKU ID and OEM name into SMBIOS table. BUG=b:144768001 TEST=Build Test. Change-Id: Id1729e245accf5acc29307a22721362fb1ce0878 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/38551 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/Kconfig | 1 + src/mainboard/google/dedede/Makefile.inc | 1 + src/mainboard/google/dedede/board_info.c | 80 +++++++++++++++++++ .../baseboard/include/baseboard/variants.h | 8 ++ 4 files changed, 90 insertions(+) create mode 100644 src/mainboard/google/dedede/board_info.c diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index da6dc81c77..5254d16b7c 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -1,6 +1,7 @@ config BOARD_GOOGLE_BASEBOARD_DEDEDE def_bool n select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES diff --git a/src/mainboard/google/dedede/Makefile.inc b/src/mainboard/google/dedede/Makefile.inc index c240dede62..2be3feb679 100644 --- a/src/mainboard/google/dedede/Makefile.inc +++ b/src/mainboard/google/dedede/Makefile.inc @@ -8,6 +8,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += ec.c +ramstage-y += board_info.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/google/dedede/board_info.c b/src/mainboard/google/dedede/board_info.c new file mode 100644 index 0000000000..ee89beb56d --- /dev/null +++ b/src/mainboard/google/dedede/board_info.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +#define SKU_UNKNOWN 0xffffffff +#define SKU_MAX 0x7fffffff + +static uint32_t board_info_get_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *smbios_system_sku(void) +{ + /* sku{0..2147483647} */ + static char sku_str[14]; + uint32_t sku_id = board_info_get_sku(); + + if (sku_id == SKU_UNKNOWN || sku_id > SKU_MAX) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} + +const char *smbios_mainboard_manufacturer(void) +{ + static char oem_name[32]; + static const char *manuf; + + if (manuf) + return manuf; + + if (google_chromeec_cbi_get_oem_name(&oem_name[0], + ARRAY_SIZE(oem_name)) < 0) { + printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n"); + manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER; + } else { + manuf = &oem_name[0]; + } + + return manuf; +} + +int board_info_get_fw_config(uint32_t *fw_config) +{ + uint32_t sku_id = board_info_get_sku(); + + /* + * FW_CONFIG can potentially have all the bits set. So check the + * sku_id to ensure that the CBI is provisioned before reading the + * FW_CONFIG. + */ + if (sku_id == SKU_UNKNOWN || sku_id > SKU_MAX) + return -1; + + return google_chromeec_cbi_get_fw_config(fw_config); +} diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index d7c482c172..32b2c8b4e7 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -20,4 +20,12 @@ const struct pad_config *variant_early_gpio_table(size_t *num); const struct pad_config *variant_sleep_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +/** + * Get board's Hardware features as defined in FW_CONFIG + * + * @param fw_config Address where the fw_config is stored. + * @return 0 on success or negative integer for errors. + */ +int board_info_get_fw_config(uint32_t *fw_config); + #endif /*__BASEBOARD_VARIANTS_H__ */ From 61657c2fae46e1ed8e2a4ddd42a2aa3caa8accfa Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Tue, 14 Jan 2020 17:13:27 +0100 Subject: [PATCH 005/151] mainboard/supermicro/x11-lga1151-series: Disable UART3 and 4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With UART3 and 4 enabled, the serial console in LinuxBoot crashes. This is a short-term solution until we found and fixed the original bug. Change-Id: I75cb387ef12944232b51f6d8d41810bb27754b05 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/38404 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- .../x11-lga1151-series/variants/x11ssh-tf/overridetree.cb | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index aace4f7487..3d46fe02a7 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -10,8 +10,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - register "gen3_dec" = "0x000c03e1" # UART3 - register "gen4_dec" = "0x000c02e1" # UART4 # PCIe configuration # Enable JPCIE1 @@ -116,11 +114,11 @@ chip soc/intel/skylake end device pnp 2e.5 off end # KBC device pnp 2e.7 on end # GPIO - device pnp 2e.b on # SUART3 + device pnp 2e.b off # SUART3 io 0x60 = 0x3e8 irq 0x70 = 4 end - device pnp 2e.c on # SUART4 + device pnp 2e.c off # SUART4 io 0x60 = 0x2e8 irq 0x70 = 3 end From 9f2e3ad6280000b818c71ebd250430509a819553 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 23 Jan 2020 00:06:07 -0800 Subject: [PATCH 006/151] soc/intel/tigerlake: Enable DP ports according to board design BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim Change-Id: Ia6e9271a11a1f9e6f98923772219ccc1e7daecda Reviewed-on: https://review.coreboot.org/c/coreboot/+/38528 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/chip.h | 26 +++++++++++++++++++ .../intel/tigerlake/romstage/fsp_params_tgl.c | 18 +++++++++++++ 2 files changed, 44 insertions(+) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 4907f4921d..3f980d1552 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -236,6 +236,32 @@ struct soc_intel_tigerlake_config { * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* DP config */ + /* + * Port config + * 0:Disabled, 1:eDP, 2:MIPI DSI + */ + uint8_t DdiPortAConfig; + uint8_t DdiPortBConfig; + + /* Enable(1)/Disable(0) HPD */ + uint8_t DdiPortAHpd; + uint8_t DdiPortBHpd; + uint8_t DdiPortCHpd; + uint8_t DdiPort1Hpd; + uint8_t DdiPort2Hpd; + uint8_t DdiPort3Hpd; + uint8_t DdiPort4Hpd; + + /* Enable(1)/Disable(0) DDC */ + uint8_t DdiPortADdc; + uint8_t DdiPortBDdc; + uint8_t DdiPortCDdc; + uint8_t DdiPort1Ddc; + uint8_t DdiPort2Ddc; + uint8_t DdiPort3Ddc; + uint8_t DdiPort4Ddc; }; typedef struct soc_intel_tigerlake_config config_t; diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index a4533c9e6c..6ed3dcd2de 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -84,6 +84,24 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, else m_cfg->InternalGfx = 0x1; + /* DP port config */ + m_cfg->DdiPortAConfig = config->DdiPortAConfig; + m_cfg->DdiPortBConfig = config->DdiPortBConfig; + m_cfg->DdiPortAHpd = config->DdiPortAHpd; + m_cfg->DdiPortBHpd = config->DdiPortBHpd; + m_cfg->DdiPortCHpd = config->DdiPortCHpd; + m_cfg->DdiPort1Hpd = config->DdiPort1Hpd; + m_cfg->DdiPort2Hpd = config->DdiPort2Hpd; + m_cfg->DdiPort3Hpd = config->DdiPort3Hpd; + m_cfg->DdiPort4Hpd = config->DdiPort4Hpd; + m_cfg->DdiPortADdc = config->DdiPortADdc; + m_cfg->DdiPortBDdc = config->DdiPortBDdc; + m_cfg->DdiPortCDdc = config->DdiPortCDdc; + m_cfg->DdiPort1Ddc = config->DdiPort1Ddc; + m_cfg->DdiPort2Ddc = config->DdiPort2Ddc; + m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; + m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ From 46cef44dad8f796b9c5ac0ed3a684266b88cec62 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 23 Jan 2020 00:12:46 -0800 Subject: [PATCH 007/151] mb/intel/tglrvp: Enable DP ports for TGLRVP TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux from pinctl driver. Signed-off-by: Wonkyu Kim Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529 Reviewed-by: Furquan Shaikh Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- .../intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e7bfe337f9..d4b5a39bfd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -49,6 +49,12 @@ chip soc/intel/tigerlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + # enabling EDP in PortA + register "DdiPortAConfig" = "1" + + register "DdiPort1Hpd" = "1" + register "DdiPort1Ddc" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, From 6b7d40a973c2cb61cfa683065db38601537b5dd5 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 22 Jan 2020 11:40:16 +0100 Subject: [PATCH 008/151] mb/lenovo: Remove unnecessary whitespace in comments This makes diff between boards even smaller in some cases. Change-Id: I42ecaf5de657275708ddaf2c926fe31fe16a7220 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38515 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/lenovo/g505s/acpi/gpe.asl | 14 +++++++------- src/mainboard/lenovo/g505s/acpi/usb_oc.asl | 2 +- src/mainboard/lenovo/g505s/buildOpts.c | 8 ++++---- src/mainboard/lenovo/g505s/dsdt.asl | 2 +- src/mainboard/lenovo/g505s/ec.h | 2 +- src/mainboard/lenovo/g505s/mainboard.h | 2 +- src/mainboard/lenovo/g505s/mptable.c | 2 +- src/mainboard/lenovo/l520/acpi/platform.asl | 4 ++-- src/mainboard/lenovo/l520/dsdt.asl | 2 +- src/mainboard/lenovo/l520/smihandler.c | 4 ++-- src/mainboard/lenovo/s230u/early_init.c | 2 +- src/mainboard/lenovo/s230u/ec.h | 2 +- src/mainboard/lenovo/t400/acpi/gpe.asl | 2 +- src/mainboard/lenovo/t410/acpi/gpe.asl | 2 +- src/mainboard/lenovo/t410/hda_verb.c | 6 +++--- src/mainboard/lenovo/t420s/smihandler.c | 2 +- src/mainboard/lenovo/t430/acpi/platform.asl | 2 +- src/mainboard/lenovo/t430/dsdt.asl | 2 +- src/mainboard/lenovo/t430/smihandler.c | 2 +- .../lenovo/t430s/variants/t431s/romstage.c | 2 +- src/mainboard/lenovo/t440p/acpi/platform.asl | 2 +- src/mainboard/lenovo/t440p/smihandler.c | 4 ++-- src/mainboard/lenovo/t520/smihandler.c | 2 +- src/mainboard/lenovo/t530/acpi/platform.asl | 4 ++-- src/mainboard/lenovo/t530/smihandler.c | 2 +- src/mainboard/lenovo/t60/acpi/gpe.asl | 2 +- src/mainboard/lenovo/x131e/acpi/platform.asl | 4 ++-- src/mainboard/lenovo/x131e/hda_verb.c | 2 +- .../lenovo/x1_carbon_gen1/acpi/platform.asl | 4 ++-- src/mainboard/lenovo/x1_carbon_gen1/smihandler.c | 4 ++-- src/mainboard/lenovo/x200/acpi/gpe.asl | 2 +- src/mainboard/lenovo/x200/blc.c | 2 +- src/mainboard/lenovo/x200/romstage.c | 2 +- src/mainboard/lenovo/x201/acpi/gpe.asl | 2 +- src/mainboard/lenovo/x201/acpi/platform.asl | 6 +++--- src/mainboard/lenovo/x201/hda_verb.c | 6 +++--- src/mainboard/lenovo/x220/acpi/platform.asl | 4 ++-- src/mainboard/lenovo/x220/smihandler.c | 2 +- src/mainboard/lenovo/x230/acpi/platform.asl | 4 ++-- src/mainboard/lenovo/x230/smihandler.c | 4 ++-- src/mainboard/lenovo/x60/acpi/gpe.asl | 2 +- 41 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/mainboard/lenovo/g505s/acpi/gpe.asl b/src/mainboard/lenovo/g505s/acpi/gpe.asl index ace1d2692e..f28ad50207 100644 --- a/src/mainboard/lenovo/g505s/acpi/gpe.asl +++ b/src/mainboard/lenovo/g505s/acpi/gpe.asl @@ -15,18 +15,18 @@ Scope(\_GPE) { /* Start Scope GPE */ - /* Legacy PM event */ + /* Legacy PM event */ Method(_L08) { /* DBGO("\\_GPE\\_L08\n") */ } - /* Temp warning (TWarn) event */ + /* Temp warning (TWarn) event */ Method(_L09) { /* DBGO("\\_GPE\\_L09\n") */ /* Notify (\_TZ.TZ00, 0x80) */ } - /* USB controller PME# */ + /* USB controller PME# */ Method(_L0B) { Store("USB PME", Debug) /* Notify devices of wake event */ @@ -39,13 +39,13 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PWRB, 0x02) } - /* ExtEvent0 SCI event */ + /* ExtEvent0 SCI event */ Method(_L10) { /* DBGO("\\_GPE\\_L10\n") */ } - /* ExtEvent1 SCI event */ + /* ExtEvent1 SCI event */ Method(_L11) { /* DBGO("\\_GPE\\_L11\n") */ } @@ -59,7 +59,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.LID, 0x80) } - /* GPIO0 or GEvent8 event */ + /* GPIO0 or GEvent8 event */ Method(_L18) { Store("PCI bridge wake event", Debug) /* Notify PCI bridges of wake event */ @@ -67,7 +67,7 @@ Scope(\_GPE) { /* Start Scope GPE */ Notify(\_SB.PCI0.PBR5, 0x02) } - /* Azalia SCI event */ + /* Azalia SCI event */ Method(_L1B) { /* DBGO("\\_GPE\\_L1B\n") */ Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ diff --git a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl index f5d6980d15..ae064feb1f 100644 --- a/src/mainboard/lenovo/g505s/acpi/usb_oc.asl +++ b/src/mainboard/lenovo/g505s/acpi/usb_oc.asl @@ -14,7 +14,7 @@ * GNU General Public License for more details. */ -/* USB overcurrent mapping pins. */ +/* USB overcurrent mapping pins. */ Name(UOM0, 0) Name(UOM1, 2) Name(UOM2, 0) diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 3adf20d99d..66cdefda67 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -30,7 +30,7 @@ #include -/* Include the files that instantiate the configuration definitions. */ +/* Include the files that instantiate the configuration definitions. */ #include #include #include @@ -43,13 +43,13 @@ #include -/* Select the CPU family. */ +/* Select the CPU family. */ #define INSTALL_FAMILY_10_SUPPORT FALSE #define INSTALL_FAMILY_12_SUPPORT FALSE #define INSTALL_FAMILY_14_SUPPORT FALSE #define INSTALL_FAMILY_15_MODEL_1x_SUPPORT TRUE -/* Select the CPU socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT FALSE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE @@ -182,7 +182,7 @@ //#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID //#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID -/* Process the options... +/* Process the options... * This file include MUST occur AFTER the user option selection settings */ /* diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index bc9a13f73a..ce11be8caa 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -66,7 +66,7 @@ DefinitionBlock ( /* Describe PCI INT[A-H] for the Southbridge */ #include - } /* End Scope(_SB) */ + } /* End Scope(_SB) */ Scope(\_SB.PCI0.LIBR) { #include "acpi/ec.asl" diff --git a/src/mainboard/lenovo/g505s/ec.h b/src/mainboard/lenovo/g505s/ec.h index 52a3ab71d8..63579b1bc4 100644 --- a/src/mainboard/lenovo/g505s/ec.h +++ b/src/mainboard/lenovo/g505s/ec.h @@ -21,4 +21,4 @@ void lenovo_g505s_ec_init(void); -#endif /* _MAINBOARD_LENOVO_G505S_EC_H */ +#endif /* _MAINBOARD_LENOVO_G505S_EC_H */ diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index 0a7ccd72dc..ebae80c8c4 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -38,4 +38,4 @@ /* Enable PS/2 Keyboard and Mouse */ #define SIO_EC_ENABLE_PS2K -#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */ +#endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */ diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index f3c2f0a572..3b2c4a2988 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -138,7 +138,7 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ + /* on board NIC & Slot PCIE. */ /* PCI slots */ struct device *dev = pcidev_on_root(0x14, 4); diff --git a/src/mainboard/lenovo/l520/acpi/platform.asl b/src/mainboard/lenovo/l520/acpi/platform.asl index 2d016faa9d..534408e509 100644 --- a/src/mainboard/lenovo/l520/acpi/platform.asl +++ b/src/mainboard/lenovo/l520/acpi/platform.asl @@ -16,14 +16,14 @@ Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index 4fefb5e6de..08b38d2f3a 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -30,7 +30,7 @@ DefinitionBlock( #include "acpi/platform.asl" #include #include - /* global NVS and variables. */ + /* global NVS and variables. */ #include #include diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index 982233d4bc..425c05d47c 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -75,9 +75,9 @@ void mainboard_smi_sleep(u8 slp_typ) { if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/s230u/early_init.c b/src/mainboard/lenovo/s230u/early_init.c index 10ce300432..a0fc2ecd59 100644 --- a/src/mainboard/lenovo/s230u/early_init.c +++ b/src/mainboard/lenovo/s230u/early_init.c @@ -83,7 +83,7 @@ void mainboard_get_spd(spd_raw_data *spd, bool id_only) printk(BIOS_INFO, "SPD index %d (%s)\n", spd_index, mainboard_spd_names[spd_index]); - /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ + /* C0S0 is a soldered RAM with no real SPD. Use stored SPD. */ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); diff --git a/src/mainboard/lenovo/s230u/ec.h b/src/mainboard/lenovo/s230u/ec.h index a5bc4236ff..d65b2e1026 100644 --- a/src/mainboard/lenovo/s230u/ec.h +++ b/src/mainboard/lenovo/s230u/ec.h @@ -25,4 +25,4 @@ void lenovo_s230u_ec_init(void); #define ec_mm_set_bit(addr, bit) (ECMM(0x100 + addr) |= 1 << bit) #define ec_mm_clr_bit(addr, bit) (ECMM(0x100 + addr) &= ~(1 << bit)) -#endif /* _MAINBOARD_LENOVO_S230U_EC_H */ +#endif /* _MAINBOARD_LENOVO_S230U_EC_H */ diff --git a/src/mainboard/lenovo/t400/acpi/gpe.asl b/src/mainboard/lenovo/t400/acpi/gpe.asl index 5c900ca3a9..3b45262652 100644 --- a/src/mainboard/lenovo/t400/acpi/gpe.asl +++ b/src/mainboard/lenovo/t400/acpi/gpe.asl @@ -20,7 +20,7 @@ Scope (\_GPE) { /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ + /* So that we don't get a warning that Local0 is unused. */ Increment (Local0) } } diff --git a/src/mainboard/lenovo/t410/acpi/gpe.asl b/src/mainboard/lenovo/t410/acpi/gpe.asl index 5c900ca3a9..3b45262652 100644 --- a/src/mainboard/lenovo/t410/acpi/gpe.asl +++ b/src/mainboard/lenovo/t410/acpi/gpe.asl @@ -20,7 +20,7 @@ Scope (\_GPE) { /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ + /* So that we don't get a warning that Local0 is unused. */ Increment (Local0) } } diff --git a/src/mainboard/lenovo/t410/hda_verb.c b/src/mainboard/lenovo/t410/hda_verb.c index 70e8a6d057..7f60c0d10d 100644 --- a/src/mainboard/lenovo/t410/hda_verb.c +++ b/src/mainboard/lenovo/t410/hda_verb.c @@ -18,7 +18,7 @@ const u32 cim_verb_data[] = { 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17aa214c, /* Subsystem ID */ + 0x17aa214c, /* Subsystem ID */ 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x17aa214c), AZALIA_PIN_CFG(0, 0x19, 0x042110f0), @@ -32,8 +32,8 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), AZALIA_PIN_CFG(0, 0x23, 0x90a601f0), - 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ - 0x17aa21b5, /* Subsystem ID */ + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x17aa21b5, /* Subsystem ID */ 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(3, 0x17aa21b5), AZALIA_PIN_CFG(3, 0x04, 0x18560010), diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index bc72a12e23..044da44021 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -76,7 +76,7 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl index 13ea2c1b40..ed8e16c09e 100644 --- a/src/mainboard/lenovo/t430/acpi/platform.asl +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -15,7 +15,7 @@ Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 68f91e9014..b22dc37041 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -34,7 +34,7 @@ DefinitionBlock( #include "acpi/platform.asl" #include #include - /* global NVS and variables. */ + /* global NVS and variables. */ #include #include diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index 9a567ab40f..6c887d608f 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -76,7 +76,7 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index fa6028dbee..04ddbe070f 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -42,7 +42,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { void mainboard_get_spd(spd_raw_data *spd, bool id_only) { - /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ + /* C1S0 is a soldered RAM with no real SPD. Use stored SPD. */ size_t spd_file_len = 0; void *spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); diff --git a/src/mainboard/lenovo/t440p/acpi/platform.asl b/src/mainboard/lenovo/t440p/acpi/platform.asl index db142f0e5b..add8c2da18 100644 --- a/src/mainboard/lenovo/t440p/acpi/platform.asl +++ b/src/mainboard/lenovo/t440p/acpi/platform.asl @@ -16,7 +16,7 @@ Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) Return(Package(){0,0}) diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index 9f5044a3d5..eafb2aee9b 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -91,9 +91,9 @@ void mainboard_smi_sleep(u8 slp_typ) if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, - * enable wake on EC WAKE GPE. */ + * enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 35a26c0ebd..f06eaf717f 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -76,7 +76,7 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/t530/acpi/platform.asl b/src/mainboard/lenovo/t530/acpi/platform.asl index bf686f444f..e4c8a24f78 100644 --- a/src/mainboard/lenovo/t530/acpi/platform.asl +++ b/src/mainboard/lenovo/t530/acpi/platform.asl @@ -28,13 +28,13 @@ Method(_PTS,1) Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 35a26c0ebd..f06eaf717f 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -76,7 +76,7 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/t60/acpi/gpe.asl b/src/mainboard/lenovo/t60/acpi/gpe.asl index 5c900ca3a9..3b45262652 100644 --- a/src/mainboard/lenovo/t60/acpi/gpe.asl +++ b/src/mainboard/lenovo/t60/acpi/gpe.asl @@ -20,7 +20,7 @@ Scope (\_GPE) { /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ + /* So that we don't get a warning that Local0 is unused. */ Increment (Local0) } } diff --git a/src/mainboard/lenovo/x131e/acpi/platform.asl b/src/mainboard/lenovo/x131e/acpi/platform.asl index bf686f444f..e4c8a24f78 100644 --- a/src/mainboard/lenovo/x131e/acpi/platform.asl +++ b/src/mainboard/lenovo/x131e/acpi/platform.asl @@ -28,13 +28,13 @@ Method(_PTS,1) Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/x131e/hda_verb.c b/src/mainboard/lenovo/x131e/hda_verb.c index 37c4bc0bce..0c3dac910b 100644 --- a/src/mainboard/lenovo/x131e/hda_verb.c +++ b/src/mainboard/lenovo/x131e/hda_verb.c @@ -76,7 +76,7 @@ const u32 cim_verb_data[] = { }; const u32 pc_beep_verbs[] = { - 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ 0x01470740, /* enable speaker out */ 0x01470c02, /* set speaker EAPD pin */ 0x0143b01f, /* unmute speaker */ diff --git a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl index bf686f444f..e4c8a24f78 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/acpi/platform.asl @@ -28,13 +28,13 @@ Method(_PTS,1) Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c index 24259270b3..6c887d608f 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c @@ -74,9 +74,9 @@ void mainboard_smi_sleep(u8 slp_typ) { if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/x200/acpi/gpe.asl b/src/mainboard/lenovo/x200/acpi/gpe.asl index 5c900ca3a9..3b45262652 100644 --- a/src/mainboard/lenovo/x200/acpi/gpe.asl +++ b/src/mainboard/lenovo/x200/acpi/gpe.asl @@ -20,7 +20,7 @@ Scope (\_GPE) { /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ + /* So that we don't get a warning that Local0 is unused. */ Increment (Local0) } } diff --git a/src/mainboard/lenovo/x200/blc.c b/src/mainboard/lenovo/x200/blc.c index 0856060e86..42b5df24ed 100644 --- a/src/mainboard/lenovo/x200/blc.c +++ b/src/mainboard/lenovo/x200/blc.c @@ -23,7 +23,7 @@ static const struct blc_pwm_t blc_entries[] = { /* corrected to 320MHz CDClk, vendor set 753; works fine at both: */ {"LTD121EQ3B", 447}, {"LTD121EWVB", 165}, - {"LTD133EQ1B", 264}, /* Found on an X301 */ + {"LTD133EQ1B", 264}, /* Found on an X301 */ {"B121EW03 V6 ", 165}, /* datasheets: between 100 and 20k, typical 200 */ /* TESTED: works best at 400 */ diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 41be94f357..f7d8487530 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -25,7 +25,7 @@ void get_mb_spd_addrmap(u8 *spd_addrmap) void mb_post_raminit_setup(void) { - /* FIXME: make a proper SMBUS mux support. */ + /* FIXME: make a proper SMBUS mux support. */ /* Set the SMBUS mux to the eeprom */ set_gpio(42, GPIO_LEVEL_LOW); } diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index 5c900ca3a9..3b45262652 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -20,7 +20,7 @@ Scope (\_GPE) { /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ + /* So that we don't get a warning that Local0 is unused. */ Increment (Local0) } } diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index bcd6de67c8..ac7c00fbbc 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -29,14 +29,14 @@ Method(_PTS,1) Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } @@ -69,7 +69,7 @@ Scope(\_SB) * interrupts can happen */ - /* TRAP(71) */ /* TODO */ + /* TRAP(71) */ /* TODO */ /* Determine the Operating System and save the value in OSYS. * We have to do this in order to be able to work around diff --git a/src/mainboard/lenovo/x201/hda_verb.c b/src/mainboard/lenovo/x201/hda_verb.c index 37517fcb5d..5e9a9fd8e5 100644 --- a/src/mainboard/lenovo/x201/hda_verb.c +++ b/src/mainboard/lenovo/x201/hda_verb.c @@ -18,7 +18,7 @@ const u32 cim_verb_data[] = { 0x14f15069, /* Codec Vendor / Device ID: Conexant CX20585 */ - 0x17aa2155, /* Subsystem ID */ + 0x17aa2155, /* Subsystem ID */ 11, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(0, 0x17aa2155), AZALIA_PIN_CFG(0, 0x19, 0x042140f0), /* Headphone jack */ @@ -32,8 +32,8 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x22, 0x40f001f0), AZALIA_PIN_CFG(0, 0x23, 0x90a601f0), /* Internal mic boost volume */ - 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ - 0x17aa21b5, /* Subsystem ID */ + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x17aa21b5, /* Subsystem ID */ 4, /* Number of 4 dword sets */ AZALIA_SUBVENDOR(3, 0x17aa21b5), AZALIA_PIN_CFG(3, 0x04, 0x58560010), diff --git a/src/mainboard/lenovo/x220/acpi/platform.asl b/src/mainboard/lenovo/x220/acpi/platform.asl index bf686f444f..e4c8a24f78 100644 --- a/src/mainboard/lenovo/x220/acpi/platform.asl +++ b/src/mainboard/lenovo/x220/acpi/platform.asl @@ -28,13 +28,13 @@ Method(_PTS,1) Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index 35a26c0ebd..f06eaf717f 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -76,7 +76,7 @@ void mainboard_smi_sleep(u8 slp_typ) u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/x230/acpi/platform.asl b/src/mainboard/lenovo/x230/acpi/platform.asl index bf686f444f..e4c8a24f78 100644 --- a/src/mainboard/lenovo/x230/acpi/platform.asl +++ b/src/mainboard/lenovo/x230/acpi/platform.asl @@ -28,13 +28,13 @@ Method(_PTS,1) Method(_WAK,1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store (0, \_TZ.MEB1) Store (0, \_TZ.MEB2) /* Wake the HKEY to init BT/WWAN */ \_SB.PCI0.LPCB.EC.HKEY.WAKE (Arg0) - /* Not implemented. */ + /* Not implemented. */ Return(Package(){0,0}) } diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index 24259270b3..6c887d608f 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -74,9 +74,9 @@ void mainboard_smi_sleep(u8 slp_typ) { if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } diff --git a/src/mainboard/lenovo/x60/acpi/gpe.asl b/src/mainboard/lenovo/x60/acpi/gpe.asl index 5c900ca3a9..3b45262652 100644 --- a/src/mainboard/lenovo/x60/acpi/gpe.asl +++ b/src/mainboard/lenovo/x60/acpi/gpe.asl @@ -20,7 +20,7 @@ Scope (\_GPE) { /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) - /* So that we don't get a warning that Local0 is unused. */ + /* So that we don't get a warning that Local0 is unused. */ Increment (Local0) } } From 71a7ca786e520eaa48f7a660da44d88d64cd2375 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 22 Jan 2020 11:48:55 +0100 Subject: [PATCH 009/151] autoport: Don't add useless whitespace in comments Change-Id: Ie6c94c0627743f9e965347ecfd28f1b0441178ad Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38516 Reviewed-by: HAOUAS Elyes Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/autoport/ec_lenovo.go | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/autoport/ec_lenovo.go b/util/autoport/ec_lenovo.go index e847e76eb8..3113a33fbc 100644 --- a/util/autoport/ec_lenovo.go +++ b/util/autoport/ec_lenovo.go @@ -42,7 +42,7 @@ func LenovoEC(ctx Context) { ap.WriteString( `Method(_WAK, 1) { - /* ME may not be up yet. */ + /* ME may not be up yet. */ Store(0, \_TZ.MEB1) Store(0, \_TZ.MEB2) Return(Package() {0, 0}) @@ -151,9 +151,9 @@ void mainboard_smi_sleep(u8 slp_typ) { if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); - /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { - /* Redirect EC WAKE GPE to SCI. */ + /* Redirect EC WAKE GPE to SCI. */ gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); } } From 291e88a01ceb5949b89f334e1428d7a160a2637e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 11 Jan 2020 19:50:30 +0100 Subject: [PATCH 010/151] mb/hp/pavilion_m6_1035dx: Fix typos Change-Id: Ibd6f6bf7983382901a5327121d277606f609eca4 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38365 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../hp/pavilion_m6_1035dx/BiosCallOuts.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 2eb36fa4d9..dfe53eaad9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -92,15 +92,15 @@ static const CODEC_TBL_LIST CodecTableList[] = #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF -/* Parmer Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -155,12 +155,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ From e0cd2eb6d3d4bb01cfffa7833cc720362e955350 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sun, 19 Jan 2020 00:07:05 +0100 Subject: [PATCH 011/151] nb/intel/i945: Use boot path macros Change-Id: I932bd0cb97507fa159d1fe3cf2335beb31ca1caf Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38597 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Georgi --- src/northbridge/intel/i945/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index ff4ccc195e..6274e099c8 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -68,7 +68,7 @@ void mainboard_romstage_entry(void) mainboard_get_spd_map(spd_map); - sdram_initialize(s3resume ? 2 : 0, spd_map); + sdram_initialize(s3resume ? BOOT_PATH_RESUME : BOOT_PATH_NORMAL, spd_map); /* This should probably go away. Until now it is required * and mainboard specific From 03b20350e39c46b141a2f033332b459ab2d4e3d6 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 24 Jan 2020 17:31:51 -0800 Subject: [PATCH 012/151] mb/intel/tglrvp: pin mux for image clocks pin mux for IMGCLKOUT_0 and IMGCLKOUT_1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux for Image clocks pins(GPP_D4, GPP_H20) Signed-off-by: Wonkyu Kim Change-Id: Ifb0c2b17dd481ef6c19bdf9ee84f47ef08d7b9a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38563 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 69bb931611..d1dc4ca251 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -28,6 +28,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C15, 0, PLTRST), PAD_CFG_GPO(GPP_R6, 0, PLTRST), PAD_CFG_GPO(GPP_H12, 0, PLTRST), + + /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ + PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), }; /* Early pad configuration in bootblock */ From c332a47c54f6e9b025a36e14eb0d3b115400d21c Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Fri, 24 Jan 2020 17:02:08 -0800 Subject: [PATCH 013/151] soc/intel/tigerlake: Disable image clocks TGL FSP does just pin mux for image clock pins by UPD and image clocks are controlled by ACPI(camera_clock_ctl.asl) under tigerlake SOC folder. Disable image clocks by UPD for bypassing FSP pin mux and do pin mux in gpio.c according to board design. BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim Change-Id: I5aba5b2fb6deee231e3ec34c8dbc9972b01041f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38562 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 6ed3dcd2de..9c105cadc2 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -102,6 +102,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->DdiPort3Ddc = config->DdiPort3Ddc; m_cfg->DdiPort4Ddc = config->DdiPort4Ddc; + /* Image clock: disable all clocks for bypassing FSP pin mux */ + memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ From 272fecafbba9c5708ee745bf07b1262ac54cd446 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 27 Jan 2020 16:56:03 +0530 Subject: [PATCH 014/151] mb/intel/kblrvp: Replace whitespaces with tabs in dsdt.asl Change-Id: I66e2cfd041f9a93668e41d79c40cec9cb1bd917e Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38589 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: V Sowmya Reviewed-by: HAOUAS Elyes --- src/mainboard/intel/kblrvp/dsdt.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl index e34b6c768f..3da6547f54 100644 --- a/src/mainboard/intel/kblrvp/dsdt.asl +++ b/src/mainboard/intel/kblrvp/dsdt.asl @@ -36,8 +36,8 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - /* Image processing unit */ - #include + /* Image processing unit */ + #include #include #include } From c4a71467d1f9807d93f0a943219f511773447050 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Fri, 24 Jan 2020 15:37:39 +0100 Subject: [PATCH 015/151] Documentation/mainboard/facebook/monolith.md: Add flash components Add description of the procedure to create the flash components for this system. BUG=N/A TEST=N/A Change-Id: I2690dfbe715fa120f840d98c57fdc3fd7e8b45b1 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38588 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- Documentation/mainboard/facebook/monolith.md | 38 ++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index 0bc1448c45..dca2d6a688 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -13,12 +13,50 @@ fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd Microcode 3rdparty/intel-microcode/intel-ucode +## Flash components + +To create a complete flash image, the flash descriptor, GBE and ME blobs are required. The +complete image can be used when e.g. a blank flash should be programmed. In other cases (when +only coreboot needs to be replaced) placeholders can be used for the GBE and ME regions. + +These can be extracted from the original flash image as follows: +1) Read the complete image from flash. +2) Create a layout file with the following content: +``` +00000000:00000fff fd +00700000:00ffffff bios +00003000:006FFFFF me +00001000:00002fff gbe +``` +3) Use `ifdtool -n ` to resize the *bios* region from the default 6MB + to 9 MB, this is required to create sufficient space for LinuxBoot. + NOTE: Please make sure only the firmware descriptor (*fd*) region is changed. Older versions + of the ifdtool corrupt the *me* region. +4) Use `ifdtool -x ` to extract the components. + +The regions extracted can be used to generate a full flash image. The *bios* region is +not needed as this is replaced by the coreboot image. + +NOTE: The gbe region contains the MAC address so be careful. When updating the flash using + flashrom it is advisable to leave out the *gbe* area. + ## Flashing coreboot ### Internal programming The SPI flash can be accessed using [flashrom]. +The descriptor area needs to be updated once to resize the *bios* region. +`flashrom -p internal --ifd -i fd -w ` + +After that only the bios area should to be updated. +`flashrom -p internal --ifd -i bios -w ` + +The *gbe* and *me* regions should not be updated. + +NOTE: As `flashrom --ifd` uses the flash descriptor it is required to update the + descriptor and bios regions in the right sequence. Don't update both in one command. + ### External programming The system has an internal flash chip which is a 16 MiB soldered SOIC-8 chip. From d5f0b4a17b7a3b617614d8b8c100a274a49fc49e Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 2 Jan 2020 16:04:28 -0700 Subject: [PATCH 016/151] amdblocks/biosram: Do small reformatting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove two blank lines and reorder functions by read/write sizes. Change-Id: I7bd6ed44546d49b65135a98e424a5669d90f2867 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/38146 Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki Reviewed-by: Michał Żygowski Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/acpimmio/biosram.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/soc/amd/common/block/acpimmio/biosram.c b/src/soc/amd/common/block/acpimmio/biosram.c index 814fdf3b00..1b1fcadee3 100644 --- a/src/soc/amd/common/block/acpimmio/biosram.c +++ b/src/soc/amd/common/block/acpimmio/biosram.c @@ -38,12 +38,6 @@ static uint16_t biosram_read16(uint8_t reg) /* Must be 1 byte at a time */ return (biosram_read8(reg + sizeof(uint8_t)) << 8 | biosram_read8(reg)); } -static uint32_t biosram_read32(uint8_t reg) -{ - uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; - return value | biosram_read16(reg); -} - static void biosram_write16(uint8_t reg, uint16_t value) { biosram_write8(reg, value & 0xff); @@ -51,6 +45,12 @@ static void biosram_write16(uint8_t reg, uint16_t value) biosram_write8(reg + sizeof(uint8_t), value & 0xff); } +static uint32_t biosram_read32(uint8_t reg) +{ + uint32_t value = biosram_read16(reg + sizeof(uint16_t)) << 16; + return value | biosram_read16(reg); +} + static void biosram_write32(uint8_t reg, uint32_t value) { biosram_write16(reg, value & 0xffff); @@ -58,7 +58,6 @@ static void biosram_write32(uint8_t reg, uint32_t value) biosram_write16(reg + sizeof(uint16_t), value & 0xffff); } - /* Access to BIOSRAM is only allowed through the abstractions below. */ void *get_ap_entry_ptr(void) @@ -71,7 +70,6 @@ void set_ap_entry_ptr(void *entry) biosram_write32(BIOSRAM_AP_ENTRY, (uintptr_t)entry); } - void backup_top_of_low_cacheable(uintptr_t ramtop) { biosram_write32(BIOSRAM_CBMEM_TOP, ramtop); From 06f855cfe900ea76811d9640f3525664f1d447c7 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 23 Dec 2019 16:16:18 +0100 Subject: [PATCH 017/151] soc/intel/skylake/acpi/dptf: Remove processor throttling controls The fwts method test reports errors on the methods implementing processor throttling control. The T states are not supported in coreboot at this moment. Remove the methods required by processor throttling control. They can be restored when the required support has been added to the SoC implementation. BUG=https://ticket.coreboot.org/issues/252 TEST=tested using fwts on facebook monolith. Found-by: fwts 19.12.00 Change-Id: Ib50607f60cdb2ad03e613d18b40f56a4c4a4c714 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38132 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Frans Hendriks --- src/soc/intel/skylake/acpi/dptf/cpu.asl | 65 ------------------------- 1 file changed, 65 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 6278b9ff13..c614aaf265 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -23,10 +23,6 @@ #endif External (\_PR.CP00._PSS, PkgObj) -External (\_PR.CP00._TSS, PkgObj) -External (\_PR.CP00._TPC, MethodObj) -External (\_PR.CP00._PTC, PkgObj) -External (\_PR.CP00._TSD, PkgObj) External (\_SB.MPDL, IntObj) Device (B0D4) @@ -42,67 +38,6 @@ Device (B0D4) } } - /* - * Processor Throttling Controls - */ - - Method (_TSS) - { - If (CondRefOf (\_PR.CP00._TSS)) { - Return (\_PR.CP00._TSS) - } Else { - Return (Package () - { - Package () { 0, 0, 0, 0, 0 } - }) - } - } - - Method (_TPC) - { - If (CondRefOf (\_PR.CP00._TPC)) { - Return (\_PR.CP00._TPC) - } Else { - Return (0) - } - } - - Method (_PTC) - { - If (CondRefOf (\_PR.CP00._PTC)) { - Return (\_PR.CP00._PTC) - } Else { - Return (Package () - { - Buffer () { 0 }, - Buffer () { 0 } - }) - } - } - - Method (_TSD) - { - If (CondRefOf (\_PR.CP00._TSD)) { - Return (\_PR.CP00._TSD) - } Else { - Return (Package () - { - Package () { 5, 0, 0, 0, 0 } - }) - } - } - - Method (_TDL) - { - If (CondRefOf (\_PR.CP00._TSS)) { - Store (SizeOf (\_PR.CP00._TSS), Local0) - Decrement (Local0) - Return (Local0) - } Else { - Return (0) - } - } - /* * Processor Performance Control */ From e6111a9e014b973e9282a225fd6089314a690398 Mon Sep 17 00:00:00 2001 From: Jorge Fernandez Date: Fri, 6 Dec 2019 08:18:13 +0100 Subject: [PATCH 018/151] amd/pi/00660F01: Add missing domain_acpi_name function It's symmetric to the code found in 00730F01 northbridge. Change-Id: I1ee439213ff128b534f5bf130661d0ae2b9558ab Signed-off-by: Jorge Fernandez Reviewed-on: https://review.coreboot.org/c/coreboot/+/37547 Reviewed-by: Marshall Dawson Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/northbridge/amd/pi/00660F01/northbridge.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 16b5734a49..3e04ec3167 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -757,12 +757,21 @@ static void domain_set_resources(struct device *dev) } } +static const char *domain_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, .init = NULL, .scan_bus = pci_domain_scan_bus, + .acpi_name = domain_acpi_name, }; static void sysconf_init(struct device *dev) // first node From b52354b6be065e1ec57e6333dfa757c57ba04605 Mon Sep 17 00:00:00 2001 From: Gaggery Tsai Date: Tue, 7 Jan 2020 07:03:56 -0800 Subject: [PATCH 019/151] soc/intel/common/block/lpc: Add CMP-H LPC IDs This patch adds CMP-H LPC IDs. TEST=Build an image and boot with discrete TPM chip. Enable measured boot and kernel could get the measured data from TPM chip. Change-Id: I7eac8b0514f79b47a05973210e2472dd1dc3d0ed Signed-off-by: Gaggery Tsai Reviewed-on: https://review.coreboot.org/c/coreboot/+/38251 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/lpc/lpc.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 8493d93786..af90df6e6c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -192,6 +192,13 @@ static const unsigned short pci_device_ids[] = { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC, PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_HM470, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_WM490, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_QM480, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_W480, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_H470, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_Z490, + PCI_DEVICE_ID_INTEL_CMP_H_LPC_Q470, PCI_DEVICE_ID_INTEL_TGP_ESPI_0, PCI_DEVICE_ID_INTEL_TGP_SUPER_U_ESPI, PCI_DEVICE_ID_INTEL_TGP_PREMIUM_U_ESPI, From ea4d1246e84f5bd14b216a11bb6829b4d9e6f05d Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Tue, 28 Jan 2020 16:43:45 +0100 Subject: [PATCH 020/151] Documentation/mainboard/facebook/monolith.md: Update to beta status Update to reflect the beta status of the code. BUG=N/A TEST=build Change-Id: I9d1c42d24578c9420569da7e294d5c723da3c772 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38607 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Paul Menzel --- Documentation/mainboard/facebook/monolith.md | 37 ++++++++++++++------ 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/Documentation/mainboard/facebook/monolith.md b/Documentation/mainboard/facebook/monolith.md index dca2d6a688..cdd32089e6 100644 --- a/Documentation/mainboard/facebook/monolith.md +++ b/Documentation/mainboard/facebook/monolith.md @@ -3,15 +3,28 @@ This page describes how to run coreboot on the Facebook Monolith. Please note: the coreboot implementation for this boards is in its -Alpha state and isn't fully tested yet. +Beta state and isn't fully tested yet. ## Required blobs -This board currently requires: -fsp blobs 3rdparty/fsp/KabylakeFspBinPkg/Fsp_M.fd - 3rdparty/fsp/KabylakeFspBinPkg/Fsp_S.fd +Mainboard is based on the Intel Kaby Lake U SoC. +Intel company provides [Firmware Support Package (2.0)](../../soc/intel/fsp/index.md) +(intel FSP 2.0) to initialize this generation silicon. Please see this +[document](../../soc/intel/code_development_model/code_development_model.md). -Microcode 3rdparty/intel-microcode/intel-ucode +FSP Information: + +```eval_rst ++-----------------------------+-------------------+-------------------+ +| FSP Project Name | Directory | Specification | ++-----------------------------+-------------------+-------------------+ +| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 | +| processors and chipsets | | | +| (formerly Kaby Lake) | | | ++-----------------------------+-------------------+-------------------+ +``` + +Microcode: 3rdparty/intel-microcode/intel-ucode ## Flash components @@ -75,25 +88,29 @@ solution. Wires need to be connected to be able to flash using an external progr ## Untested - Hardware monitor -- SDIO - Full Embedded Controller support -- eMMC - SATA +- xDCI ## Working - USB -- Gigabit Ethernet +- Gigabit Ethernet (i219 and i210) - Graphics (Using FSP GOP) - flashrom -- PCIe +- PCIe including hotplug on FPGA root port - EC serial port +- EC CPU temperature - SMBus - Initialization with FSP - SeaBIOS payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) - TianoCore payload (commit a5cab58e9a3fb6e168aba919c5669bea406573b4) +- LinuxBoot (kernel kernel-4_19_97) (uroot commit 9c9db9dbd6b532f5f91a511a0de885c6562aadd7) +- eMMC + +All of the above has been briefly tested by booting Linux from eMMC using the TianoCore payload +and LinuxBoot. -All of the above has been briefly tested by booting Linux from the TianoCore payload. SeaBios has been checked to the extend that it runs to the boot selection and provides display output. From 71299c274b09373e8776de55f245754cb48dbdaa Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Mon, 27 Jan 2020 11:38:57 -0800 Subject: [PATCH 021/151] arch/x86: add acpigen resource support Add Word/DWord/QWord Address Space Descriptor helper functions. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Change-Id: I707f8a443090b6f30e2940b721f9555ccdf49d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38594 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Patrick Rudolph --- src/arch/x86/acpigen.c | 75 +++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 9 ++++ 2 files changed, 84 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 2e6078358a..72605bb766 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1758,3 +1758,78 @@ int acpigen_disable_tx_gpio(struct acpi_gpio *gpio) else return acpigen_soc_clear_tx_gpio(gpio->pins[0]); } + +/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ +void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, + u16 range_min, u16 range_max, u16 translation, u16 length) +{ + acpigen_emit_byte(0x88); + /* Byte 1+2: length (0x000d) */ + acpigen_emit_byte(0x0d); + acpigen_emit_byte(0x00); + /* resource type */ + acpigen_emit_byte(res_type); // 0 - mem, 1 - io, 2 - bus + /* general flags */ + acpigen_emit_byte(gen_flags); + /* type flags */ + // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details + acpigen_emit_byte(type_flags); + /* granularity, min, max, translation, length */ + acpigen_emit_word(gran); + acpigen_emit_word(range_min); + acpigen_emit_word(range_max); + acpigen_emit_word(translation); + acpigen_emit_word(length); +} + +/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */ +void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, + u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length) +{ + acpigen_emit_byte(0x87); + /* Byte 1+2: length (0023) */ + acpigen_emit_byte(23); + acpigen_emit_byte(0x00); + /* resource type */ + acpigen_emit_byte(res_type); // 0 - mem, 1 - io, 2 - bus + /* general flags */ + acpigen_emit_byte(gen_flags); + /* type flags */ + // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details + acpigen_emit_byte(type_flags); + /* granularity, min, max, translation, length */ + acpigen_emit_dword(gran); + acpigen_emit_dword(range_min); + acpigen_emit_dword(range_max); + acpigen_emit_dword(translation); + acpigen_emit_dword(length); +} + +static void acpigen_emit_qword(u64 data) +{ + acpigen_emit_dword(data & 0xffffffff); + acpigen_emit_dword((data >> 32) & 0xffffffff); +} + +/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ +void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, + u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length) +{ + acpigen_emit_byte(0x8a); + /* Byte 1+2: length (0x002b) */ + acpigen_emit_byte(0x2b); + acpigen_emit_byte(0x00); + /* resource type */ + acpigen_emit_byte(res_type); // 0 - mem, 1 - io, 2 - bus + /* general flags */ + acpigen_emit_byte(gen_flags); + /* type flags */ + // refer to ACPI Table 6-234 (Memory), 6-235 (IO), 6-236 (Bus) for details + acpigen_emit_byte(type_flags); + /* granularity, min, max, translation, length */ + acpigen_emit_qword(gran); + acpigen_emit_qword(range_min); + acpigen_emit_qword(range_max); + acpigen_emit_qword(translation); + acpigen_emit_qword(length); +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 6317091512..08075585ca 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -472,4 +472,13 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); int acpigen_enable_tx_gpio(struct acpi_gpio *gpio); int acpigen_disable_tx_gpio(struct acpi_gpio *gpio); +/* refer to ACPI 6.4.3.5.3 Word Address Space Descriptor section for details */ +void acpigen_resource_word(u16 res_type, u16 gen_flags, u16 type_flags, u16 gran, + u16 range_min, u16 range_max, u16 translation, u16 length); +/* refer to ACPI 6.4.3.5.2 DWord Address Space Descriptor section for details */ +void acpigen_resource_dword(u16 res_type, u16 gen_flags, u16 type_flags, + u32 gran, u32 range_min, u32 range_max, u32 translation, u32 length); +/* refer to ACPI 6.4.3.5.1 QWord Address Space Descriptor section for details */ +void acpigen_resource_qword(u16 res_type, u16 gen_flags, u16 type_flags, + u64 gran, u64 range_min, u64 range_max, u64 translation, u64 length); #endif From 7e2625587d11209bdecbeffda3267b2336477b78 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 23 Jan 2020 10:32:33 +1100 Subject: [PATCH 022/151] x86/acpi_device: Allow acpi_device_add_power_res params as optional Allow for making both reset_gpio && enable_gpio as optional in the params by fixing a potential NULL deref and defaulting to zero values. BUG=b:147026979 BRANCH=none TEST=builds Change-Id: I8053d7a080dfed898400c0994bcea492c826fe3d Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38522 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/arch/x86/acpi_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c index d51278975b..1092c7317b 100644 --- a/src/arch/x86/acpi_device.c +++ b/src/arch/x86/acpi_device.c @@ -537,9 +537,9 @@ void acpi_device_write_spi(const struct acpi_spi *spi) void acpi_device_add_power_res(const struct acpi_power_res_params *params) { static const char *power_res_dev_states[] = { "_PR0", "_PR3" }; - unsigned int reset_gpio = params->reset_gpio->pins[0]; - unsigned int enable_gpio = params->enable_gpio->pins[0]; - unsigned int stop_gpio = params->stop_gpio->pins[0]; + unsigned int reset_gpio = params->reset_gpio ? params->reset_gpio->pins[0] : 0; + unsigned int enable_gpio = params->enable_gpio ? params->enable_gpio->pins[0] : 0; + unsigned int stop_gpio = params->stop_gpio ? params->stop_gpio->pins[0] : 0; if (!reset_gpio && !enable_gpio && !stop_gpio) return; From b765fa6e4789a160cd3fc543e6f659c333a17110 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Tue, 21 Jan 2020 21:01:32 +1100 Subject: [PATCH 023/151] drivers/net/r8168: Add SSDT Power Resource Methods Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again. V.2: Ensure reset_gpio && enable_gpio are optional. BUG=b:147026979 BRANCH=none TEST=Boot puff and do 100 cycles of S0ix. Change-Id: I3ae8dc30f45f55eec23f45e7b5fbc67a4542f87d Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38494 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/drivers/net/chip.h | 12 ++++++++++++ src/drivers/net/r8168.c | 10 ++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 430bc334a5..249b80f740 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -15,10 +15,22 @@ #define __DRIVERS_R8168_CHIP_H__ #include +#include struct drivers_net_config { uint16_t customized_leds; unsigned int wake; /* Wake pin for ACPI _PRW */ + + /* Does the device have a power resource? */ + bool has_power_resource; + + /* GPIO used to stop operation of device. */ + struct acpi_gpio stop_gpio; + /* Delay to be inserted after disabling stop. */ + unsigned int stop_delay_ms; + /* Delay to be inserted after enabling stop. */ + unsigned int stop_off_delay_ms; + /* * There maybe many NIC cards in a system. * This parameter is for driver to identify what diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 1bca8799aa..07069aa88b 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -317,6 +317,16 @@ static void r8168_net_fill_ssdt(struct device *dev) if (dev->chip_ops) acpigen_write_name_string("_DDN", dev->chip_ops->name); + /* Power Resource */ + if (config->has_power_resource) { + const struct acpi_power_res_params power_res_params = { + .stop_gpio = &config->stop_gpio, + .stop_delay_ms = config->stop_delay_ms, + .stop_off_delay_ms = config->stop_off_delay_ms + }; + acpi_device_add_power_res(&power_res_params); + } + /* Address */ address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; address <<= 16; From 38f7db79b59dcc45b353e1c28943588309ac9571 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Thu, 23 Jan 2020 10:45:00 +1100 Subject: [PATCH 024/151] mainboard/google/hatch: Fix Puff _PR to toggle NIC ISOLATE# for S0ix Turns out when going into S0ix we want the kernel to toggle de-assert to 0 for the ISOLATE# pin on the NIC for S0ix not to be woken by PCIe traffic on PCH. Upon resume the ISOLATE# pin on the NIC is then re-asserted for it to become lively again. BUG=b:147026979 BRANCH=none TEST=Boot puff and do 1500 cycles of S0ix. Change-Id: I3470e1edd93b461b66fc6444541a64339bcdcce3 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38523 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index 45d05d0928..d84b36986d 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -271,6 +271,10 @@ chip soc/intel/cannonlake chip drivers/net register "customized_leds" = "0x05af" register "wake" = "GPE0_DW1_07" # GPP_C7 + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A18)" + register "stop_delay_ms" = "12" # NIC needs time to quiesce + register "stop_off_delay_ms" = "1" + register "has_power_resource" = "1" device pci 00.0 on end end end # FSP requires func0 be enabled. From 2cbfadd1dece1df0d74fd0160206bc9f74f34ee9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Jan 2020 18:11:14 +0100 Subject: [PATCH 025/151] mb: Fix typos in comments in AGESA boards Change-Id: I4821c48ccac92f412126cea0f22cca5fd8bf8647 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38609 Tested-by: build bot (Jenkins) Reviewed-by: Peter Lemenkov --- src/mainboard/amd/olivehill/BiosCallOuts.c | 16 ++++++++-------- src/mainboard/amd/parmer/BiosCallOuts.c | 16 ++++++++-------- src/mainboard/amd/thatcher/BiosCallOuts.c | 18 +++++++++--------- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 18 +++++++++--------- src/mainboard/biostar/a68n_5200/BiosCallOuts.c | 18 +++++++++--------- .../gizmosphere/gizmo2/BiosCallOuts.c | 18 +++++++++--------- src/mainboard/lenovo/g505s/BiosCallOuts.c | 18 +++++++++--------- 7 files changed, 61 insertions(+), 61 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 4f780b35c1..6e29d84179 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -95,13 +95,13 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] = /* Olivehill Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 59d6bf6f0b..322b22019a 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -95,13 +95,13 @@ static const CODEC_TBL_LIST CodecTableList[] = /* Parmer Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index f8b7539ed8..01dc5ab777 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -93,15 +93,15 @@ static const CODEC_TBL_LIST CodecTableList[] = #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF -/* Parmer Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 9ebef559a5..27d1dcaa9a 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -97,15 +97,15 @@ static const CODEC_TBL_LIST CodecTableList[] = #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF -/* Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -160,12 +160,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ diff --git a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c index 0caa71899d..fe4fab5a12 100644 --- a/src/mainboard/biostar/a68n_5200/BiosCallOuts.c +++ b/src/mainboard/biostar/a68n_5200/BiosCallOuts.c @@ -93,15 +93,15 @@ static const CODEC_TBL_LIST OlivehillCodecTableList[] = #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF -/* Olivehill Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ diff --git a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c index a3fbb25c79..8fa8ab5bf3 100644 --- a/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo2/BiosCallOuts.c @@ -93,15 +93,15 @@ static const CODEC_TBL_LIST CodecTableList[] = #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF -/* Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommand way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -156,12 +156,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommand */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ diff --git a/src/mainboard/lenovo/g505s/BiosCallOuts.c b/src/mainboard/lenovo/g505s/BiosCallOuts.c index 876b524a78..dfe53eaad9 100644 --- a/src/mainboard/lenovo/g505s/BiosCallOuts.c +++ b/src/mainboard/lenovo/g505s/BiosCallOuts.c @@ -92,15 +92,15 @@ static const CODEC_TBL_LIST CodecTableList[] = #define FREQ_14HZ 0xFE #define FREQ_11HZ 0xFF -/* Parmer Hardware Monitor Fan Control +/* Hardware Monitor Fan Control * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. + * HWM failed to read the input temperature via I2C, + * if other software switches the I2C switch by mistake or intention. + * We recommend using IMC to control Fans, instead of HWM. */ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { - /* Enable IMC fan control. the recommend way */ + /* Enable IMC fan control, the recommended way */ if (CONFIG(HUDSON_IMC_FWM)) { imc_reg_init(); @@ -155,12 +155,12 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8; /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwrite it. - * so we remove it from AGESA code. Please See FchInitLateHwm. + * FchInitLateHwm will overwrite the EcStruct with EcDefaultMessage, + * AGESA puts EcDefaultMessage as global data in ROM, so we can't overwrite it. + * So we remove it from AGESA code. Please See FchInitLateHwm. */ } else { - /* HWM fan control, the way not recommend */ + /* HWM fan control, the way not recommended */ FchParams->Imc.ImcEnable = FALSE; FchParams->Hwm.HwMonitorEnable = TRUE; FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ From 874466481c59bbaceafc64c3631e8c705224033a Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 23 Jan 2020 16:05:53 +0100 Subject: [PATCH 026/151] AUTHORS: add authors from src/superio Change-Id: I6d56380beef7023c60d6fbb47c520ec6f6a7c9db Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38543 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons --- AUTHORS | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/AUTHORS b/AUTHORS index 6fbee9d19c..d41c9583b5 100644 --- a/AUTHORS +++ b/AUTHORS @@ -10,6 +10,7 @@ 9elements Agency GmbH Advanced Micro Devices, Inc. +AG Electronics Ltd. Alex Züpke Alexander Couzens Alexandru Gagniuc @@ -20,20 +21,27 @@ Arthur Heymans ASPEED Technology Inc. Atheros Corporation Atmel Corporation +BAP - Bruhnspace Advanced Projects Carl-Daniel Hailfinger +Christoph Grenz coresystems GmbH +Corey Osgood Damien Zammit David Brownell David Hendricks David Mosberger-Tang Denis Dowling DENX Software Engineering +Digital Design Corporation DMP Electronics Inc. Drew Eckhardt +Dynon Avionics +Edward O'Callaghan Egbert Eich Eltan B.V Eric Biederman Eswar Nallusamy +Fabian Kunkel Facebook, Inc. Felix Held Frederic Potter @@ -41,6 +49,7 @@ Free Software Foundation, Inc. Freescale Semiconductor, Inc. Gary Jennejohn Gerd Hoffmann +Gergely Kiss Google LLC Greg Watson Idwer Vollering @@ -53,11 +62,13 @@ Jordan Crouse Joseph Smith Keith Hui Keith Packard +Kevin Cody-Little Kshitij Kyösti Mälkki Lei Wen Li-Ta Lo Libra Li +Libretrend LDA Linus Torvalds Linux Networx, Inc. Luc Verhaegen @@ -67,34 +78,44 @@ Marius Gröger Martin Mares Marvell International Ltd. Marvell Semiconductor Inc. +Matt DeVillier MediaTek Inc. +Mondrian Nuessle MontaVista Software, Inc. Myles Watson Network Appliance Inc. Nicholas Sielicki Nick Barker Nico Huber +Nicola Corna Ollie Lo +Omar Pakker Orion Technologies, LLC Patrick Georgi Patrick Rudolph +Pavel Sayekat PC Engines GmbH Per Odlund Peter Stuge +Philipp Degler +Protectli Raptor Engineering, LLC Red Hat Inc Reinhard Meyer +Richard Spiegel Richard Woodruff Ronald G. Minnich Rudolf Marek Russell King Sage Electronic Engineering, LLC Samsung Electronics +Samuel Holland SciTech Software, Inc. Sebastian Grzywna secunet Security Networks AG Siemens AG Silicon Integrated System Corporation +Silverback ltd. Stefan Reinauer Steve Magnani ST Microelectronics @@ -102,16 +123,22 @@ SUSE LINUX AG Sven Schnelle Syed Mohammed Khasim Texas Instruments +The ChromiumOS Authors The Linux Foundation Thomas Winischhofer Timothy Pearson +Tobias Diedrich Tungsten Graphics, Inc. Tyan Computer Corp. ucRobotics Inc. +University of Heidelberg Uwe Hermann VIA Technologies, Inc Vipin Kumar +Vladimir Serbinenko +Wang Qing Pei Ward Vandewege +Win Enterprises Wolfgang Denk Yinghai Lu @@ -125,3 +152,4 @@ src/console src/cpu src/device src/drivers +src/superio From 3f3eca9b32f7472469b6d4ce1ac155d9ce425749 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 23 Jan 2020 17:12:32 +0100 Subject: [PATCH 027/151] src/superio: replace license boilerplate with SPDX The authors from the header of the files are added in a previous commit. Change-Id: Iafeaafb9689c65bd2f5de3960097ec0d4c1009e7 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38544 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/superio/Makefile.inc | 17 ++------------ src/superio/acpi/pnp.asl | 16 ++------------ src/superio/acpi/pnp_config.asl | 17 ++------------ src/superio/acpi/pnp_generic.asl | 16 ++------------ src/superio/acpi/pnp_kbc.asl | 17 ++------------ src/superio/acpi/pnp_uart.asl | 17 ++------------ src/superio/aspeed/Makefile.inc | 17 ++------------ src/superio/aspeed/ast2400/Kconfig | 18 ++------------- src/superio/aspeed/ast2400/Makefile.inc | 18 ++------------- src/superio/aspeed/ast2400/ast2400.h | 18 ++------------- src/superio/aspeed/ast2400/chip.h | 14 ++---------- src/superio/aspeed/ast2400/superio.c | 18 ++------------- src/superio/aspeed/common/Kconfig | 18 ++------------- src/superio/aspeed/common/aspeed.h | 18 ++------------- src/superio/aspeed/common/early_serial.c | 18 ++------------- src/superio/common/chip.h | 14 ++---------- src/superio/common/conf_mode.c | 17 ++------------ src/superio/common/generic.c | 15 ++----------- src/superio/common/ssdt.c | 15 ++----------- src/superio/common/ssdt.h | 15 ++----------- src/superio/fintek/Makefile.inc | 16 ++------------ src/superio/fintek/common/Kconfig | 17 ++------------ src/superio/fintek/common/early_serial.c | 17 ++------------ src/superio/fintek/common/fan_api_call.c | 17 ++------------ src/superio/fintek/common/fan_control.h | 17 ++------------ src/superio/fintek/common/fintek.h | 17 ++------------ src/superio/fintek/f71808a/Kconfig | 16 ++------------ src/superio/fintek/f71808a/Makefile.inc | 17 ++------------ src/superio/fintek/f71808a/chip.h | 18 ++------------- src/superio/fintek/f71808a/f71808a.h | 17 ++------------ src/superio/fintek/f71808a/f71808a_hwm.c | 18 ++------------- .../fintek/f71808a/f71808a_multifunc.c | 18 ++------------- src/superio/fintek/f71808a/fintek_internal.h | 18 ++------------- src/superio/fintek/f71808a/superio.c | 18 ++------------- src/superio/fintek/f71859/Kconfig | 17 ++------------ src/superio/fintek/f71859/Makefile.inc | 17 ++------------ src/superio/fintek/f71859/f71859.h | 17 ++------------ src/superio/fintek/f71859/superio.c | 18 ++------------- src/superio/fintek/f71863fg/Kconfig | 17 ++------------ src/superio/fintek/f71863fg/Makefile.inc | 17 ++------------ src/superio/fintek/f71863fg/f71863fg.h | 17 ++------------ src/superio/fintek/f71863fg/superio.c | 17 ++------------ src/superio/fintek/f71869ad/Kconfig | 17 ++------------ src/superio/fintek/f71869ad/Makefile.inc | 17 ++------------ src/superio/fintek/f71869ad/chip.h | 17 ++------------ src/superio/fintek/f71869ad/f71869ad.h | 17 ++------------ src/superio/fintek/f71869ad/f71869ad_hwm.c | 17 ++------------ .../fintek/f71869ad/f71869ad_multifunc.c | 17 ++------------ src/superio/fintek/f71869ad/fintek_internal.h | 17 ++------------ src/superio/fintek/f71869ad/superio.c | 17 ++------------ src/superio/fintek/f81216h/Kconfig | 17 ++------------ src/superio/fintek/f81216h/Makefile.inc | 17 ++------------ src/superio/fintek/f81216h/chip.h | 17 ++------------ src/superio/fintek/f81216h/early_serial.c | 17 ++------------ src/superio/fintek/f81216h/f81216h.h | 17 ++------------ src/superio/fintek/f81216h/superio.c | 17 ++------------ src/superio/fintek/f81803a/Kconfig | 17 ++------------ src/superio/fintek/f81803a/Makefile.inc | 17 ++------------ src/superio/fintek/f81803a/acpi/superio.asl | 18 ++------------- src/superio/fintek/f81803a/f81803a.h | 17 ++------------ src/superio/fintek/f81803a/f81803a_hwm.h | 17 ++------------ src/superio/fintek/f81803a/fan_control.c | 17 ++------------ src/superio/fintek/f81803a/superio.c | 17 ++------------ src/superio/fintek/f81865f/Kconfig | 17 ++------------ src/superio/fintek/f81865f/Makefile.inc | 17 ++------------ src/superio/fintek/f81865f/f81865f.h | 17 ++------------ src/superio/fintek/f81865f/superio.c | 17 ++------------ src/superio/fintek/f81866d/Kconfig | 17 ++------------ src/superio/fintek/f81866d/Makefile.inc | 19 ++-------------- src/superio/fintek/f81866d/chip.h | 19 ++-------------- src/superio/fintek/f81866d/f81866d.h | 19 ++-------------- src/superio/fintek/f81866d/f81866d_hwm.c | 19 ++-------------- src/superio/fintek/f81866d/f81866d_uart.c | 18 ++------------- src/superio/fintek/f81866d/fintek_internal.h | 19 ++-------------- src/superio/fintek/f81866d/superio.c | 19 ++-------------- src/superio/ite/Makefile.inc | 17 ++------------ src/superio/ite/common/Kconfig | 19 ++-------------- src/superio/ite/common/early_serial.c | 18 ++------------- src/superio/ite/common/env_ctrl.c | 20 ++--------------- src/superio/ite/common/env_ctrl.h | 20 ++--------------- src/superio/ite/common/env_ctrl_chip.h | 19 ++-------------- src/superio/ite/common/ite.h | 17 ++------------ src/superio/ite/it8528e/Kconfig | 16 ++------------ src/superio/ite/it8528e/Makefile.inc | 17 ++------------ src/superio/ite/it8528e/it8528e.h | 17 ++------------ src/superio/ite/it8528e/superio.c | 20 ++--------------- src/superio/ite/it8613e/Kconfig | 20 ++--------------- src/superio/ite/it8613e/Makefile.inc | 19 ++-------------- src/superio/ite/it8613e/chip.h | 18 ++------------- src/superio/ite/it8613e/it8613e.h | 19 ++-------------- src/superio/ite/it8613e/superio.c | 20 ++--------------- src/superio/ite/it8623e/Kconfig | 19 ++-------------- src/superio/ite/it8623e/Makefile.inc | 18 ++------------- src/superio/ite/it8623e/chip.h | 17 ++------------ src/superio/ite/it8623e/it8623e.h | 18 ++------------- src/superio/ite/it8623e/superio.c | 19 ++-------------- src/superio/ite/it8712f/Kconfig | 17 ++------------ src/superio/ite/it8712f/Makefile.inc | 17 ++------------ src/superio/ite/it8712f/it8712f.h | 17 ++------------ src/superio/ite/it8712f/superio.c | 18 ++------------- src/superio/ite/it8718f/Kconfig | 17 ++------------ src/superio/ite/it8718f/Makefile.inc | 17 ++------------ src/superio/ite/it8718f/chip.h | 17 ++------------ src/superio/ite/it8718f/early_serial.c | 17 ++------------ src/superio/ite/it8718f/it8718f.h | 17 ++------------ src/superio/ite/it8718f/superio.c | 17 ++------------ src/superio/ite/it8720f/Kconfig | 18 ++------------- src/superio/ite/it8720f/Makefile.inc | 18 ++------------- src/superio/ite/it8720f/acpi/superio.asl | 18 ++------------- src/superio/ite/it8720f/chip.h | 18 ++------------- src/superio/ite/it8720f/it8720f.h | 19 ++-------------- src/superio/ite/it8720f/superio.c | 18 ++------------- src/superio/ite/it8721f/Kconfig | 17 ++------------ src/superio/ite/it8721f/Makefile.inc | 17 ++------------ src/superio/ite/it8721f/acpi/superio.asl | 18 ++------------- src/superio/ite/it8721f/it8721f.h | 18 ++------------- src/superio/ite/it8721f/superio.c | 18 ++------------- src/superio/ite/it8728f/Kconfig | 17 ++------------ src/superio/ite/it8728f/Makefile.inc | 17 ++------------ src/superio/ite/it8728f/chip.h | 17 ++------------ src/superio/ite/it8728f/it8728f.h | 18 ++------------- src/superio/ite/it8728f/superio.c | 17 ++------------ src/superio/ite/it8772f/Kconfig | 17 ++------------ src/superio/ite/it8772f/Makefile.inc | 17 ++------------ src/superio/ite/it8772f/acpi/superio.asl | 16 ++------------ src/superio/ite/it8772f/chip.h | 17 ++------------ src/superio/ite/it8772f/early_init.c | 17 ++------------ src/superio/ite/it8772f/it8772f.h | 17 ++------------ src/superio/ite/it8772f/superio.c | 17 ++------------ src/superio/ite/it8783ef/Kconfig | 16 ++------------ src/superio/ite/it8783ef/Makefile.inc | 17 ++------------ src/superio/ite/it8783ef/acpi/superio.asl | 17 ++------------ src/superio/ite/it8783ef/chip.h | 17 ++------------ src/superio/ite/it8783ef/it8783ef.h | 17 ++------------ src/superio/ite/it8783ef/superio.c | 17 ++------------ src/superio/ite/it8786e/Kconfig | 17 ++------------ src/superio/ite/it8786e/Makefile.inc | 18 ++------------- src/superio/ite/it8786e/acpi/superio.asl | 17 ++------------ src/superio/ite/it8786e/chip.h | 18 ++------------- src/superio/ite/it8786e/it8786e.h | 18 ++------------- src/superio/ite/it8786e/superio.c | 18 ++------------- src/superio/nsc/Makefile.inc | 16 ++------------ src/superio/nsc/common/Kconfig | 16 ++------------ src/superio/nsc/common/early_serial.c | 20 ++--------------- src/superio/nsc/common/nsc.h | 18 ++------------- src/superio/nsc/pc87382/Kconfig | 16 ++------------ src/superio/nsc/pc87382/Makefile.inc | 17 ++------------ src/superio/nsc/pc87382/pc87382.h | 17 ++------------ src/superio/nsc/pc87382/superio.c | 17 ++------------ src/superio/nsc/pc87384/Kconfig | 16 ++------------ src/superio/nsc/pc87384/Makefile.inc | 17 ++------------ src/superio/nsc/pc87384/pc87384.h | 17 ++------------ src/superio/nsc/pc87384/superio.c | 17 ++------------ src/superio/nsc/pc87392/Kconfig | 16 ++------------ src/superio/nsc/pc87392/Makefile.inc | 17 ++------------ src/superio/nsc/pc87392/pc87392.h | 17 ++------------ src/superio/nsc/pc87392/superio.c | 17 ++------------ src/superio/nsc/pc87417/Kconfig | 16 ++------------ src/superio/nsc/pc87417/Makefile.inc | 19 ++-------------- src/superio/nsc/pc87417/early_init.c | 19 ++-------------- src/superio/nsc/pc87417/pc87417.h | 19 ++-------------- src/superio/nsc/pc87417/superio.c | 19 ++-------------- src/superio/nuvoton/Makefile.inc | 16 ++------------ src/superio/nuvoton/common/Kconfig | 16 ++------------ src/superio/nuvoton/common/early_serial.c | 19 ++-------------- src/superio/nuvoton/common/hwm.c | 17 ++------------ src/superio/nuvoton/common/hwm.h | 17 ++------------ src/superio/nuvoton/common/nuvoton.h | 18 ++------------- src/superio/nuvoton/nct5104d/Kconfig | 16 ++------------ src/superio/nuvoton/nct5104d/Makefile.inc | 17 ++------------ src/superio/nuvoton/nct5104d/chip.h | 17 ++------------ src/superio/nuvoton/nct5104d/early_init.c | 17 ++------------ src/superio/nuvoton/nct5104d/nct5104d.h | 18 ++------------- src/superio/nuvoton/nct5104d/superio.c | 17 ++------------ src/superio/nuvoton/nct5539d/Kconfig | 16 ++------------ src/superio/nuvoton/nct5539d/Makefile.inc | 16 ++------------ src/superio/nuvoton/nct5539d/acpi/superio.asl | 19 ++-------------- src/superio/nuvoton/nct5539d/nct5539d.h | 17 ++------------ src/superio/nuvoton/nct5539d/superio.c | 22 ++----------------- src/superio/nuvoton/nct5572d/Kconfig | 16 ++------------ src/superio/nuvoton/nct5572d/Makefile.inc | 18 ++------------- src/superio/nuvoton/nct5572d/nct5572d.h | 17 ++------------ src/superio/nuvoton/nct5572d/superio.c | 19 ++-------------- src/superio/nuvoton/nct6776/Kconfig | 17 ++------------ src/superio/nuvoton/nct6776/Makefile.inc | 18 ++------------- src/superio/nuvoton/nct6776/acpi/superio.asl | 18 ++------------- src/superio/nuvoton/nct6776/nct6776.h | 17 ++------------ src/superio/nuvoton/nct6776/superio.c | 19 ++-------------- src/superio/nuvoton/nct6779d/Kconfig | 16 ++------------ src/superio/nuvoton/nct6779d/Makefile.inc | 17 ++------------ src/superio/nuvoton/nct6779d/nct6779d.h | 17 ++------------ src/superio/nuvoton/nct6779d/superio.c | 20 ++--------------- src/superio/nuvoton/nct6791d/Kconfig | 16 ++------------ src/superio/nuvoton/nct6791d/Makefile.inc | 16 ++------------ src/superio/nuvoton/nct6791d/nct6791d.h | 17 ++------------ src/superio/nuvoton/nct6791d/superio.c | 21 ++---------------- src/superio/nuvoton/npcd378/Kconfig | 16 ++------------ src/superio/nuvoton/npcd378/Makefile.inc | 17 ++------------ src/superio/nuvoton/npcd378/acpi/superio.asl | 19 ++-------------- src/superio/nuvoton/npcd378/npcd378.h | 17 ++------------ src/superio/nuvoton/npcd378/superio.c | 20 ++--------------- src/superio/nuvoton/wpcm450/Kconfig | 16 ++------------ src/superio/nuvoton/wpcm450/Makefile.inc | 17 ++------------ src/superio/nuvoton/wpcm450/early_init.c | 17 ++------------ src/superio/nuvoton/wpcm450/superio.c | 17 ++------------ src/superio/nuvoton/wpcm450/wpcm450.h | 17 ++------------ src/superio/renesas/Makefile.inc | 16 ++------------ src/superio/renesas/m3885x/Kconfig | 16 ++------------ src/superio/renesas/m3885x/Makefile.inc | 16 ++------------ src/superio/renesas/m3885x/superio.c | 16 ++------------ src/superio/serverengines/Makefile.inc | 16 ++------------ src/superio/serverengines/pilot/Kconfig | 16 ++------------ src/superio/serverengines/pilot/Makefile.inc | 17 ++------------ src/superio/serverengines/pilot/early_init.c | 18 ++------------- .../serverengines/pilot/early_serial.c | 18 ++------------- src/superio/serverengines/pilot/pilot.h | 18 ++------------- src/superio/smsc/Makefile.inc | 17 ++------------ src/superio/smsc/fdc37n972/Kconfig | 17 ++------------ src/superio/smsc/fdc37n972/Makefile.inc | 16 ++------------ src/superio/smsc/fdc37n972/fdc37n972.h | 16 ++------------ src/superio/smsc/fdc37n972/superio.c | 16 ++------------ src/superio/smsc/kbc1100/Kconfig | 17 ++------------ src/superio/smsc/kbc1100/Makefile.inc | 14 +----------- src/superio/smsc/kbc1100/early_init.c | 17 ++------------ src/superio/smsc/kbc1100/kbc1100.h | 17 ++------------ src/superio/smsc/kbc1100/superio.c | 16 ++------------ src/superio/smsc/lpc47m10x/Kconfig | 17 ++------------ src/superio/smsc/lpc47m10x/Makefile.inc | 21 ++---------------- src/superio/smsc/lpc47m10x/early_serial.c | 17 ++------------ src/superio/smsc/lpc47m10x/lpc47m10x.h | 19 ++-------------- src/superio/smsc/lpc47m10x/superio.c | 21 ++---------------- src/superio/smsc/lpc47m15x/Kconfig | 17 ++------------ src/superio/smsc/lpc47m15x/Makefile.inc | 16 ++------------ src/superio/smsc/lpc47m15x/early_serial.c | 16 ++------------ src/superio/smsc/lpc47m15x/lpc47m15x.h | 16 ++------------ src/superio/smsc/lpc47m15x/superio.c | 16 ++------------ src/superio/smsc/lpc47n207/Kconfig | 17 ++------------ src/superio/smsc/lpc47n207/Makefile.inc | 17 ++------------ src/superio/smsc/lpc47n207/early_serial.c | 16 ++------------ src/superio/smsc/lpc47n207/lpc47n207.h | 16 ++------------ src/superio/smsc/lpc47n217/Kconfig | 17 ++------------ src/superio/smsc/lpc47n217/Makefile.inc | 17 ++------------ src/superio/smsc/lpc47n217/early_serial.c | 17 ++------------ src/superio/smsc/lpc47n217/lpc47n217.h | 17 ++------------ src/superio/smsc/lpc47n217/superio.c | 20 ++--------------- src/superio/smsc/lpc47n227/Kconfig | 17 ++------------ src/superio/smsc/lpc47n227/Makefile.inc | 16 ++------------ src/superio/smsc/lpc47n227/early_serial.c | 17 ++------------ src/superio/smsc/lpc47n227/lpc47n227.h | 16 ++------------ src/superio/smsc/lpc47n227/superio.c | 17 ++------------ src/superio/smsc/mec1308/Kconfig | 17 ++------------ src/superio/smsc/mec1308/Makefile.inc | 14 +----------- src/superio/smsc/mec1308/acpi/superio.asl | 16 ++------------ src/superio/smsc/mec1308/mec1308.h | 16 ++------------ src/superio/smsc/mec1308/superio.c | 16 ++------------ src/superio/smsc/sch5147/acpi/superio.asl | 14 ++---------- src/superio/smsc/sio1007/Kconfig | 17 ++------------ src/superio/smsc/sio1007/Makefile.inc | 16 ++------------ src/superio/smsc/sio1007/acpi/superio.asl | 16 ++------------ src/superio/smsc/sio1007/early_serial.c | 16 ++------------ src/superio/smsc/sio1007/sio1007.h | 16 ++------------ src/superio/smsc/sio1036/Kconfig | 17 ++------------ src/superio/smsc/sio1036/Makefile.inc | 14 +----------- src/superio/smsc/sio1036/sio1036.h | 16 ++------------ src/superio/smsc/sio1036/sio1036_early_init.c | 16 ++------------ src/superio/smsc/sio1036/superio.c | 16 ++------------ src/superio/smsc/sio10n268/Kconfig | 17 ++------------ src/superio/smsc/sio10n268/Makefile.inc | 16 ++------------ src/superio/smsc/sio10n268/sio10n268.h | 16 ++------------ src/superio/smsc/sio10n268/superio.c | 16 ++------------ src/superio/smsc/smscsuperio/Kconfig | 17 ++------------ src/superio/smsc/smscsuperio/Makefile.inc | 17 ++------------ src/superio/smsc/smscsuperio/early_serial.c | 18 ++------------- src/superio/smsc/smscsuperio/smscsuperio.h | 17 ++------------ src/superio/smsc/smscsuperio/superio.c | 17 ++------------ src/superio/winbond/Makefile.inc | 16 ++------------ src/superio/winbond/common/Kconfig | 17 ++------------ src/superio/winbond/common/early_init.c | 17 ++------------ src/superio/winbond/common/winbond.h | 17 ++------------ src/superio/winbond/w83627dhg/Kconfig | 17 ++------------ src/superio/winbond/w83627dhg/Makefile.inc | 18 ++------------- .../winbond/w83627dhg/acpi/superio.asl | 17 ++------------ src/superio/winbond/w83627dhg/early_serial.c | 18 ++------------- src/superio/winbond/w83627dhg/superio.c | 16 ++------------ src/superio/winbond/w83627dhg/w83627dhg.h | 18 ++------------- src/superio/winbond/w83627ehg/Kconfig | 17 ++------------ src/superio/winbond/w83627ehg/Makefile.inc | 18 ++------------- src/superio/winbond/w83627ehg/superio.c | 20 ++--------------- src/superio/winbond/w83627ehg/w83627ehg.h | 18 ++------------- src/superio/winbond/w83627hf/Kconfig | 17 ++------------ src/superio/winbond/w83627hf/Makefile.inc | 19 ++-------------- src/superio/winbond/w83627hf/acpi/superio.asl | 16 ++------------ src/superio/winbond/w83627hf/superio.c | 20 ++--------------- src/superio/winbond/w83627hf/w83627hf.h | 19 ++-------------- src/superio/winbond/w83627thg/Kconfig | 17 ++------------ src/superio/winbond/w83627thg/Makefile.inc | 19 ++-------------- src/superio/winbond/w83627thg/superio.c | 19 ++-------------- src/superio/winbond/w83627thg/w83627thg.h | 19 ++-------------- src/superio/winbond/w83627uhg/Kconfig | 17 ++------------ src/superio/winbond/w83627uhg/Makefile.inc | 17 ++------------ src/superio/winbond/w83627uhg/superio.c | 17 ++------------ src/superio/winbond/w83627uhg/w83627uhg.h | 17 ++------------ src/superio/winbond/w83667hg-a/Kconfig | 17 ++------------ src/superio/winbond/w83667hg-a/Makefile.inc | 19 ++-------------- .../winbond/w83667hg-a/ps2_controller.asl | 18 ++------------- src/superio/winbond/w83667hg-a/superio.c | 19 ++-------------- src/superio/winbond/w83667hg-a/w83667hg-a.h | 18 ++------------- src/superio/winbond/w83977tf/Kconfig | 17 ++------------ src/superio/winbond/w83977tf/Makefile.inc | 19 ++-------------- src/superio/winbond/w83977tf/acpi/superio.asl | 18 ++------------- src/superio/winbond/w83977tf/superio.c | 19 ++-------------- src/superio/winbond/w83977tf/w83977tf.h | 19 ++-------------- 312 files changed, 621 insertions(+), 4768 deletions(-) diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index ca96343858..4c353f8328 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2018 Eltan B.V. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. subdirs-y += aspeed subdirs-y += fintek diff --git a/src/superio/acpi/pnp.asl b/src/superio/acpi/pnp.asl index d127eb51b9..1f607ebba4 100644 --- a/src/superio/acpi/pnp.asl +++ b/src/superio/acpi/pnp.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ACPI_PNP_DEFS_ASL #define SUPERIO_ACPI_PNP_DEFS_ASL diff --git a/src/superio/acpi/pnp_config.asl b/src/superio/acpi/pnp_config.asl index abebb6e933..294d70e757 100644 --- a/src/superio/acpi/pnp_config.asl +++ b/src/superio/acpi/pnp_config.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* ======== General PnP configuration functions ======= */ diff --git a/src/superio/acpi/pnp_generic.asl b/src/superio/acpi/pnp_generic.asl index dbae2ac902..482d73e40e 100644 --- a/src/superio/acpi/pnp_generic.asl +++ b/src/superio/acpi/pnp_generic.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* =================== Generic PnP Device =================== */ diff --git a/src/superio/acpi/pnp_kbc.asl b/src/superio/acpi/pnp_kbc.asl index 541dce3c89..924c0d5ad1 100644 --- a/src/superio/acpi/pnp_kbc.asl +++ b/src/superio/acpi/pnp_kbc.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* =================== Keyboard Controller ================== */ diff --git a/src/superio/acpi/pnp_uart.asl b/src/superio/acpi/pnp_uart.asl index 3cbe65aa05..e7278891a1 100644 --- a/src/superio/acpi/pnp_uart.asl +++ b/src/superio/acpi/pnp_uart.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* ========================== UART ========================== */ diff --git a/src/superio/aspeed/Makefile.inc b/src/superio/aspeed/Makefile.inc index b9494fae61..769334e8d8 100644 --- a/src/superio/aspeed/Makefile.inc +++ b/src/superio/aspeed/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2018 Eltan B.V. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ## include generic fintek pre-ram stage driver romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM) += common/early_serial.c diff --git a/src/superio/aspeed/ast2400/Kconfig b/src/superio/aspeed/ast2400/Kconfig index 1ced5afdc2..99e9192254 100644 --- a/src/superio/aspeed/ast2400/Kconfig +++ b/src/superio/aspeed/ast2400/Kconfig @@ -1,19 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2018 Eltan B.V. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ASPEED_AST2400 bool diff --git a/src/superio/aspeed/ast2400/Makefile.inc b/src/superio/aspeed/ast2400/Makefile.inc index 625390fdf8..317779a63c 100644 --- a/src/superio/aspeed/ast2400/Makefile.inc +++ b/src/superio/aspeed/ast2400/Makefile.inc @@ -1,19 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Corey Osgood -## Copyright (C) 2018 Eltan B.V. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += superio.c ramstage-$(CONFIG_SUPERIO_ASPEED_AST2400) += ../../common/ssdt.c diff --git a/src/superio/aspeed/ast2400/ast2400.h b/src/superio/aspeed/ast2400/ast2400.h index aa9b0a9899..d9e4ea1b02 100644 --- a/src/superio/aspeed/ast2400/ast2400.h +++ b/src/superio/aspeed/ast2400/ast2400.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ASPEED_AST2400_H #define SUPERIO_ASPEED_AST2400_H diff --git a/src/superio/aspeed/ast2400/chip.h b/src/superio/aspeed/ast2400/chip.h index 4f1c5f022d..5175db5d2a 100644 --- a/src/superio/aspeed/ast2400/chip.h +++ b/src/superio/aspeed/ast2400/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SUPERIO_ASPEED__AST2400_CHIP_H__ #define __SUPERIO_ASPEED__AST2400_CHIP_H__ diff --git a/src/superio/aspeed/ast2400/superio.c b/src/superio/aspeed/ast2400/superio.c index 6f2cbcdb70..0941663e2b 100644 --- a/src/superio/aspeed/ast2400/superio.c +++ b/src/superio/aspeed/ast2400/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Corey Osgood - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/aspeed/common/Kconfig b/src/superio/aspeed/common/Kconfig index f310f3ef98..f10c7be8dc 100644 --- a/src/superio/aspeed/common/Kconfig +++ b/src/superio/aspeed/common/Kconfig @@ -1,19 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2018 Eltan B.V. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # Generic Aspeed preram driver - Just enough UART initialisation code for # preram phase. diff --git a/src/superio/aspeed/common/aspeed.h b/src/superio/aspeed/common/aspeed.h index 8c54b0c750..f77258912d 100644 --- a/src/superio/aspeed/common/aspeed.h +++ b/src/superio/aspeed/common/aspeed.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ASPEED_COMMON_ROMSTAGE_H #define SUPERIO_ASPEED_COMMON_ROMSTAGE_H diff --git a/src/superio/aspeed/common/early_serial.c b/src/superio/aspeed/common/early_serial.c index d2de8ed322..086e9ddf1a 100644 --- a/src/superio/aspeed/common/early_serial.c +++ b/src/superio/aspeed/common/early_serial.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * A generic pre-ram driver for Aspeed variant Super I/O chips. diff --git a/src/superio/common/chip.h b/src/superio/common/chip.h index fd618c54ce..1be2802ed3 100644 --- a/src/superio/common/chip.h +++ b/src/superio/common/chip.h @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef __SUPERIO_COMMON_CHIP_H__ #define __SUPERIO_COMMON_CHIP_H__ diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index 1e62285444..83cf074fe1 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Nico Huber - * Copyright (C) 2017-2018 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/common/generic.c b/src/superio/common/generic.c index 85b70df1b5..de781999bf 100644 --- a/src/superio/common/generic.c +++ b/src/superio/common/generic.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 541fa9922c..7aa24ea794 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include diff --git a/src/superio/common/ssdt.h b/src/superio/common/ssdt.h index 8c63742798..1f9918950f 100644 --- a/src/superio/common/ssdt.h +++ b/src/superio/common/ssdt.h @@ -1,16 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef __SUPERIO_COMMON_SSDT_H__ #define __SUPERIO_COMMON_SSDT_H__ diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index db683fdfe6..a4dbd2cb56 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ## include generic fintek pre-ram stage driver bootblock-$(CONFIG_SUPERIO_FINTEK_COMMON_PRE_RAM) += common/early_serial.c diff --git a/src/superio/fintek/common/Kconfig b/src/superio/fintek/common/Kconfig index 22fe82bd2a..30d106a432 100644 --- a/src/superio/fintek/common/Kconfig +++ b/src/superio/fintek/common/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # Generic Fintek romstage driver - Just enough UART initialisation code for # romstage. diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index d0e0ab072f..ed5cd8c1d4 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * A generic romstage (pre-ram) driver for Fintek variant Super I/O chips. diff --git a/src/superio/fintek/common/fan_api_call.c b/src/superio/fintek/common/fan_api_call.c index 1bd5b2e7d4..9e10681c4b 100644 --- a/src/superio/fintek/common/fan_api_call.c +++ b/src/superio/fintek/common/fan_api_call.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Richard Spiegel - * Copyright (C) 2019 Silverback ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include "fan_control.h" diff --git a/src/superio/fintek/common/fan_control.h b/src/superio/fintek/common/fan_control.h index 80f17dd0c2..b82681830f 100644 --- a/src/superio/fintek/common/fan_control.h +++ b/src/superio/fintek/common/fan_control.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Richard Spiegel - * Copyright (C) 2019 Silverback ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_FAN_CONTROL_H #define SUPERIO_FINTEK_FAN_CONTROL_H diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index 306edeea7e..81e8e67238 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_COMMON_PRE_RAM_H #define SUPERIO_FINTEK_COMMON_PRE_RAM_H diff --git a/src/superio/fintek/f71808a/Kconfig b/src/superio/fintek/f71808a/Kconfig index 1fb9a49fba..9d58ab4559 100644 --- a/src/superio/fintek/f71808a/Kconfig +++ b/src/superio/fintek/f71808a/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2017 Nicola Corna -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F71808A bool diff --git a/src/superio/fintek/f71808a/Makefile.inc b/src/superio/fintek/f71808a/Makefile.inc index f43e60245c..80abe51835 100644 --- a/src/superio/fintek/f71808a/Makefile.inc +++ b/src/superio/fintek/f71808a/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2017 Nicola Corna -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_multifunc.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71808A) += f71808a_hwm.c diff --git a/src/superio/fintek/f71808a/chip.h b/src/superio/fintek/f71808a/chip.h index d838f3aec1..4806f6f997 100644 --- a/src/superio/fintek/f71808a/chip.h +++ b/src/superio/fintek/f71808a/chip.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2017 Nicola Corna - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71808A_CHIP_H #define SUPERIO_FINTEK_F71808A_CHIP_H diff --git a/src/superio/fintek/f71808a/f71808a.h b/src/superio/fintek/f71808a/f71808a.h index fbce494224..8d2eaff043 100644 --- a/src/superio/fintek/f71808a/f71808a.h +++ b/src/superio/fintek/f71808a/f71808a.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Nicola Corna - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71808A_H #define SUPERIO_FINTEK_F71808A_H diff --git a/src/superio/fintek/f71808a/f71808a_hwm.c b/src/superio/fintek/f71808a/f71808a_hwm.c index f5e62f942e..0642450752 100644 --- a/src/superio/fintek/f71808a/f71808a_hwm.c +++ b/src/superio/fintek/f71808a/f71808a_hwm.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2017 Nicola Corna - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71808a/f71808a_multifunc.c b/src/superio/fintek/f71808a/f71808a_multifunc.c index 32119e2919..571242452c 100644 --- a/src/superio/fintek/f71808a/f71808a_multifunc.c +++ b/src/superio/fintek/f71808a/f71808a_multifunc.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2017 Nicola Corna - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71808a/fintek_internal.h b/src/superio/fintek/f71808a/fintek_internal.h index 7bdb94dcd4..25e259e9ba 100644 --- a/src/superio/fintek/f71808a/fintek_internal.h +++ b/src/superio/fintek/f71808a/fintek_internal.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2017 Nicola Corna - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71808A_INTERNAL_H #define SUPERIO_FINTEK_F71808A_INTERNAL_H diff --git a/src/superio/fintek/f71808a/superio.c b/src/superio/fintek/f71808a/superio.c index 05132cc0ea..c5b659aa78 100644 --- a/src/superio/fintek/f71808a/superio.c +++ b/src/superio/fintek/f71808a/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Corey Osgood - * Copyright (C) 2017 Nicola Corna - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71859/Kconfig b/src/superio/fintek/f71859/Kconfig index eaeefd949a..18aab86860 100644 --- a/src/superio/fintek/f71859/Kconfig +++ b/src/superio/fintek/f71859/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F71859 bool diff --git a/src/superio/fintek/f71859/Makefile.inc b/src/superio/fintek/f71859/Makefile.inc index 1471a05558..9828426665 100644 --- a/src/superio/fintek/f71859/Makefile.inc +++ b/src/superio/fintek/f71859/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Marc Jones -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_FINTEK_F71859) += superio.c diff --git a/src/superio/fintek/f71859/f71859.h b/src/superio/fintek/f71859/f71859.h index a4d0366bf6..f0c18a9e00 100644 --- a/src/superio/fintek/f71859/f71859.h +++ b/src/superio/fintek/f71859/f71859.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71859_H #define SUPERIO_FINTEK_F71859_H diff --git a/src/superio/fintek/f71859/superio.c b/src/superio/fintek/f71859/superio.c index 2cd1bb1d81..2fc4ccd394 100644 --- a/src/superio/fintek/f71859/superio.c +++ b/src/superio/fintek/f71859/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Marc Jones - * Copyright (C) 2008 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71863fg/Kconfig b/src/superio/fintek/f71863fg/Kconfig index a1def52a12..3e335b9089 100644 --- a/src/superio/fintek/f71863fg/Kconfig +++ b/src/superio/fintek/f71863fg/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F71863FG bool diff --git a/src/superio/fintek/f71863fg/Makefile.inc b/src/superio/fintek/f71863fg/Makefile.inc index 2dd12c8186..4a15ed466c 100644 --- a/src/superio/fintek/f71863fg/Makefile.inc +++ b/src/superio/fintek/f71863fg/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2010 Wang Qing Pei -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_FINTEK_F71863FG) += superio.c diff --git a/src/superio/fintek/f71863fg/f71863fg.h b/src/superio/fintek/f71863fg/f71863fg.h index fb9bb69e9c..9386ebdc1b 100644 --- a/src/superio/fintek/f71863fg/f71863fg.h +++ b/src/superio/fintek/f71863fg/f71863fg.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Wang Qing Pei - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71863FG_H #define SUPERIO_FINTEK_F71863FG_H diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 5a33a716cd..f48be0e1e3 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Corey Osgood - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71869ad/Kconfig b/src/superio/fintek/f71869ad/Kconfig index 550af5ad76..aa97c1193e 100644 --- a/src/superio/fintek/f71869ad/Kconfig +++ b/src/superio/fintek/f71869ad/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F71869AD bool diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index d79c646201..44d64f06b2 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_hwm.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 42d451dbee..5aeb128e57 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71869AD_CHIP_H #define SUPERIO_FINTEK_F71869AD_CHIP_H diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index f3574213f0..d038c3d9e5 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71869AD_H #define SUPERIO_FINTEK_F71869AD_H diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index 329da350c0..5576c6f12c 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c index dcfbb4d578..ee5bce22d9 100644 --- a/src/superio/fintek/f71869ad/f71869ad_multifunc.c +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h index 2aeb896902..a40fadad55 100644 --- a/src/superio/fintek/f71869ad/fintek_internal.h +++ b/src/superio/fintek/f71869ad/fintek_internal.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F71869AD_INTERNAL_H #define SUPERIO_FINTEK_F71869AD_INTERNAL_H diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 67b39ef066..10633cee31 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81216h/Kconfig b/src/superio/fintek/f81216h/Kconfig index ce17d83823..17da818414 100644 --- a/src/superio/fintek/f81216h/Kconfig +++ b/src/superio/fintek/f81216h/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F81216H bool diff --git a/src/superio/fintek/f81216h/Makefile.inc b/src/superio/fintek/f81216h/Makefile.inc index 7dbf20e8cf..6dd48a1198 100644 --- a/src/superio/fintek/f81216h/Makefile.inc +++ b/src/superio/fintek/f81216h/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c romstage-$(CONFIG_SUPERIO_FINTEK_F81216H) += early_serial.c diff --git a/src/superio/fintek/f81216h/chip.h b/src/superio/fintek/f81216h/chip.h index 726b5bdaa7..f5f7575f43 100644 --- a/src/superio/fintek/f81216h/chip.h +++ b/src/superio/fintek/f81216h/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F81216H_CHIP_H #define SUPERIO_FINTEK_F81216H_CHIP_H diff --git a/src/superio/fintek/f81216h/early_serial.c b/src/superio/fintek/f81216h/early_serial.c index 1990c37ae7..d2fa0fe9ec 100644 --- a/src/superio/fintek/f81216h/early_serial.c +++ b/src/superio/fintek/f81216h/early_serial.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81216h/f81216h.h b/src/superio/fintek/f81216h/f81216h.h index 1a6b6406f8..865cecbf6a 100644 --- a/src/superio/fintek/f81216h/f81216h.h +++ b/src/superio/fintek/f81216h/f81216h.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F81216H_H #define SUPERIO_FINTEK_F81216H_H diff --git a/src/superio/fintek/f81216h/superio.c b/src/superio/fintek/f81216h/superio.c index 106ab0ea42..52eedd6fc8 100644 --- a/src/superio/fintek/f81216h/superio.c +++ b/src/superio/fintek/f81216h/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81803a/Kconfig b/src/superio/fintek/f81803a/Kconfig index e1aa537e78..e023616784 100644 --- a/src/superio/fintek/f81803a/Kconfig +++ b/src/superio/fintek/f81803a/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F81803A bool diff --git a/src/superio/fintek/f81803a/Makefile.inc b/src/superio/fintek/f81803a/Makefile.inc index 6fe13aaab7..9dda9d6187 100644 --- a/src/superio/fintek/f81803a/Makefile.inc +++ b/src/superio/fintek/f81803a/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) bootblock-$(CONFIG_SUPERIO_FINTEK_F81803A) += ../common/early_serial.c diff --git a/src/superio/fintek/f81803a/acpi/superio.asl b/src/superio/fintek/f81803a/acpi/superio.asl index 3112a4ba5a..0887d6a9db 100644 --- a/src/superio/fintek/f81803a/acpi/superio.asl +++ b/src/superio/fintek/f81803a/acpi/superio.asl @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013 secunet Security Networks AG - * Copyright (C) 2019, Silverback, ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/fintek/f81803a/f81803a.h b/src/superio/fintek/f81803a/f81803a.h index c986cb806e..fdf9ecf504 100644 --- a/src/superio/fintek/f81803a/f81803a.h +++ b/src/superio/fintek/f81803a/f81803a.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * Datasheet: diff --git a/src/superio/fintek/f81803a/f81803a_hwm.h b/src/superio/fintek/f81803a/f81803a_hwm.h index a7647057d1..7de47a1e86 100644 --- a/src/superio/fintek/f81803a/f81803a_hwm.h +++ b/src/superio/fintek/f81803a/f81803a_hwm.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Richard Spiegel - * Copyright (C) 2019 Silverback ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F81803_HWM_H #define SUPERIO_FINTEK_F81803_HWM_H diff --git a/src/superio/fintek/f81803a/fan_control.c b/src/superio/fintek/f81803a/fan_control.c index a08180a7f9..3b01a64e4f 100644 --- a/src/superio/fintek/f81803a/fan_control.c +++ b/src/superio/fintek/f81803a/fan_control.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Richard Spiegel - * Copyright (C) 2019 Silverback ltd. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81803a/superio.c b/src/superio/fintek/f81803a/superio.c index 5a54f54f52..5508374600 100644 --- a/src/superio/fintek/f81803a/superio.c +++ b/src/superio/fintek/f81803a/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81865f/Kconfig b/src/superio/fintek/f81865f/Kconfig index 84eca4d272..08cefc11ac 100644 --- a/src/superio/fintek/f81865f/Kconfig +++ b/src/superio/fintek/f81865f/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F81865F bool diff --git a/src/superio/fintek/f81865f/Makefile.inc b/src/superio/fintek/f81865f/Makefile.inc index b02016ffa2..e560bb31b0 100644 --- a/src/superio/fintek/f81865f/Makefile.inc +++ b/src/superio/fintek/f81865f/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_FINTEK_F81865F) += superio.c diff --git a/src/superio/fintek/f81865f/f81865f.h b/src/superio/fintek/f81865f/f81865f.h index 15c945019b..688abe23ad 100644 --- a/src/superio/fintek/f81865f/f81865f.h +++ b/src/superio/fintek/f81865f/f81865f.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * Datasheet: diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index d62fc82793..9ebfed365c 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81866d/Kconfig b/src/superio/fintek/f81866d/Kconfig index ffe9b762e2..8ffd702214 100644 --- a/src/superio/fintek/f81866d/Kconfig +++ b/src/superio/fintek/f81866d/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_FINTEK_F81866D bool diff --git a/src/superio/fintek/f81866d/Makefile.inc b/src/superio/fintek/f81866d/Makefile.inc index b3fd34fd56..2c30231155 100644 --- a/src/superio/fintek/f81866d/Makefile.inc +++ b/src/superio/fintek/f81866d/Makefile.inc @@ -1,20 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2015 BAP - Bruhnspace Advanced Projects -## (Written by Fabian Kunkel for BAP) -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += f81866d_hwm.c f81866d_uart.c ramstage-$(CONFIG_SUPERIO_FINTEK_F81866D) += superio.c diff --git a/src/superio/fintek/f81866d/chip.h b/src/superio/fintek/f81866d/chip.h index aa15b9a214..0e1efe7a16 100644 --- a/src/superio/fintek/f81866d/chip.h +++ b/src/superio/fintek/f81866d/chip.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F81866D_CHIP_H #define SUPERIO_FINTEK_F81866D_CHIP_H diff --git a/src/superio/fintek/f81866d/f81866d.h b/src/superio/fintek/f81866d/f81866d.h index 5ee4be0a22..fc9690fec5 100644 --- a/src/superio/fintek/f81866d/f81866d.h +++ b/src/superio/fintek/f81866d/f81866d.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * Datasheet: diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index 1b499689b1..515bc41200 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* Setup only for Fan2 * TODO: Add support for Fan1 and Fan3 diff --git a/src/superio/fintek/f81866d/f81866d_uart.c b/src/superio/fintek/f81866d/f81866d_uart.c index 79d5b31888..c6c18890b0 100644 --- a/src/superio/fintek/f81866d/f81866d_uart.c +++ b/src/superio/fintek/f81866d/f81866d_uart.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/fintek/f81866d/fintek_internal.h b/src/superio/fintek/f81866d/fintek_internal.h index 3b06f48bb7..0a6e1bb25d 100644 --- a/src/superio/fintek/f81866d/fintek_internal.h +++ b/src/superio/fintek/f81866d/fintek_internal.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_FINTEK_F81866D_INTERNAL_H #define SUPERIO_FINTEK_F81866D_INTERNAL_H diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index c66bf27745..6c6b5fbed5 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 BAP - Bruhnspace Advanced Projects - * (Written by Fabian Kunkel for BAP) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 8388c7aa38..4e03704e7c 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2018 Libretrend LDA -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ## include generic ite pre-ram stage driver bootblock-$(CONFIG_SUPERIO_ITE_COMMON_PRE_RAM) += common/early_serial.c diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 55f765004c..a80abfb2c7 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -1,20 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2016 secunet Security Networks AG -## Copyright (C) 2019 Protectli -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # Generic ITE romstage driver - Just enough UART initialisation code for # romstage. diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 6402ae9c59..fa881a07f6 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Damien Zammit - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 9d7594fc42..23fd87dd9e 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Protectli - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 20e44ad5f1..ee69ea1ea9 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Protectli - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_ENV_CTRL_H #define SUPERIO_ITE_ENV_CTRL_H diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f5116e6465..025be074f1 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_ENV_CTRL_CHIP_H #define SUPERIO_ITE_ENV_CTRL_CHIP_H diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 151ba12533..96a8520819 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_COMMON_PRE_RAM_H #define SUPERIO_ITE_COMMON_PRE_RAM_H diff --git a/src/superio/ite/it8528e/Kconfig b/src/superio/ite/it8528e/Kconfig index 86f4048a98..da5eeed879 100644 --- a/src/superio/ite/it8528e/Kconfig +++ b/src/superio/ite/it8528e/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 9Elements GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8528E bool diff --git a/src/superio/ite/it8528e/Makefile.inc b/src/superio/ite/it8528e/Makefile.inc index deb1bc0108..b16c3d23cd 100644 --- a/src/superio/ite/it8528e/Makefile.inc +++ b/src/superio/ite/it8528e/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 9Elements GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8528E) += superio.c diff --git a/src/superio/ite/it8528e/it8528e.h b/src/superio/ite/it8528e/it8528e.h index a065b7d5de..af9c582cd8 100644 --- a/src/superio/ite/it8528e/it8528e.h +++ b/src/superio/ite/it8528e/it8528e.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 9Elements GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8528E_H #define SUPERIO_ITE_IT8528E_H diff --git a/src/superio/ite/it8528e/superio.c b/src/superio/ite/it8528e/superio.c index d7169e6d4e..33e8003fd5 100644 --- a/src/superio/ite/it8528e/superio.c +++ b/src/superio/ite/it8528e/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2007 Philipp Degler - * Copyright (C) 2017 Gergely Kiss - * Copyright (C) 2019 9Elements GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8613e/Kconfig b/src/superio/ite/it8613e/Kconfig index f09cac2fa8..89ff897efd 100644 --- a/src/superio/ite/it8613e/Kconfig +++ b/src/superio/ite/it8613e/Kconfig @@ -1,21 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2017 Gergely Kiss -## Copyright (C) 2018 Kevin Cody-Little -## Copyright (C) 2019 Protectli -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8613E bool diff --git a/src/superio/ite/it8613e/Makefile.inc b/src/superio/ite/it8613e/Makefile.inc index 75ab26bc5e..3faa6ba625 100644 --- a/src/superio/ite/it8613e/Makefile.inc +++ b/src/superio/ite/it8613e/Makefile.inc @@ -1,19 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## Copyright (C) 2017 Gergely Kiss -## Copyright (C) 2019 Protectli -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8613E) += superio.c diff --git a/src/superio/ite/it8613e/chip.h b/src/superio/ite/it8613e/chip.h index 65875c8fc2..db69de1de0 100644 --- a/src/superio/ite/it8613e/chip.h +++ b/src/superio/ite/it8613e/chip.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8613E_CHIP_H #define SUPERIO_ITE_IT8613E_CHIP_H diff --git a/src/superio/ite/it8613e/it8613e.h b/src/superio/ite/it8613e/it8613e.h index 890c24925d..7e048af2e7 100644 --- a/src/superio/ite/it8613e/it8613e.h +++ b/src/superio/ite/it8613e/it8613e.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2017 Gergely Kiss - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8613E_H #define SUPERIO_ITE_IT8613E_H diff --git a/src/superio/ite/it8613e/superio.c b/src/superio/ite/it8613e/superio.c index 7a4e336278..e8ccae9c7d 100644 --- a/src/superio/ite/it8613e/superio.c +++ b/src/superio/ite/it8613e/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2007 Philipp Degler - * Copyright (C) 2017 Gergely Kiss - * Copyright (C) 2019 Protectli - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8623e/Kconfig b/src/superio/ite/it8623e/Kconfig index 756c7ff71d..8cac5784c2 100644 --- a/src/superio/ite/it8623e/Kconfig +++ b/src/superio/ite/it8623e/Kconfig @@ -1,20 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2017 Gergely Kiss -## Copyright (C) 2018 Kevin Cody-Little -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8623E bool diff --git a/src/superio/ite/it8623e/Makefile.inc b/src/superio/ite/it8623e/Makefile.inc index 2afaecfd75..b196f9e9a2 100644 --- a/src/superio/ite/it8623e/Makefile.inc +++ b/src/superio/ite/it8623e/Makefile.inc @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## Copyright (C) 2017 Gergely Kiss -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8623E) += superio.c diff --git a/src/superio/ite/it8623e/chip.h b/src/superio/ite/it8623e/chip.h index c92b4512f7..24cdcf300c 100644 --- a/src/superio/ite/it8623e/chip.h +++ b/src/superio/ite/it8623e/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8623E_CHIP_H #define SUPERIO_ITE_IT8623E_CHIP_H diff --git a/src/superio/ite/it8623e/it8623e.h b/src/superio/ite/it8623e/it8623e.h index 25670c58af..dafc0c9a50 100644 --- a/src/superio/ite/it8623e/it8623e.h +++ b/src/superio/ite/it8623e/it8623e.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2017 Gergely Kiss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8623E_H #define SUPERIO_ITE_IT8623E_H diff --git a/src/superio/ite/it8623e/superio.c b/src/superio/ite/it8623e/superio.c index 044883267f..a085d355c1 100644 --- a/src/superio/ite/it8623e/superio.c +++ b/src/superio/ite/it8623e/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2007 Philipp Degler - * Copyright (C) 2017 Gergely Kiss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8712f/Kconfig b/src/superio/ite/it8712f/Kconfig index 3c43c7ed73..4975920293 100644 --- a/src/superio/ite/it8712f/Kconfig +++ b/src/superio/ite/it8712f/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8712F bool diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 967cf435de..56d8894d3a 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index d040a10b37..ead056fdff 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8712F_H #define SUPERIO_ITE_IT8712F_H diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 2004236396..4c69c71c75 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2007 Philipp Degler - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8718f/Kconfig b/src/superio/ite/it8718f/Kconfig index 848d71d913..9b42b1b4cd 100644 --- a/src/superio/ite/it8718f/Kconfig +++ b/src/superio/ite/it8718f/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8718F bool diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc index 89382caa30..fc959d7a71 100644 --- a/src/superio/ite/it8718f/Makefile.inc +++ b/src/superio/ite/it8718f/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c romstage-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c diff --git a/src/superio/ite/it8718f/chip.h b/src/superio/ite/it8718f/chip.h index 23511bbd5e..92b6a7a800 100644 --- a/src/superio/ite/it8718f/chip.h +++ b/src/superio/ite/it8718f/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8718F_CHIP_H #define SUPERIO_ITE_IT8718F_CHIP_H diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 74233c4fc1..1690e2a4eb 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index ebf8c4cae2..82329716ea 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8718F_H #define SUPERIO_ITE_IT8718F_H diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index 297aead5fb..6295d571e4 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8720f/Kconfig b/src/superio/ite/it8720f/Kconfig index b8b9262500..cbd3f9dab0 100644 --- a/src/superio/ite/it8720f/Kconfig +++ b/src/superio/ite/it8720f/Kconfig @@ -1,19 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## Copyright (C) 2017 Samuel Holland -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8720F bool diff --git a/src/superio/ite/it8720f/Makefile.inc b/src/superio/ite/it8720f/Makefile.inc index 87f89dc190..dfb08c6116 100644 --- a/src/superio/ite/it8720f/Makefile.inc +++ b/src/superio/ite/it8720f/Makefile.inc @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2006 Uwe Hermann -## Copyright (C) 2017 Samuel Holland -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8720F) += superio.c diff --git a/src/superio/ite/it8720f/acpi/superio.asl b/src/superio/ite/it8720f/acpi/superio.asl index 1c793e2ec9..4f3a8e0b9f 100644 --- a/src/superio/ite/it8720f/acpi/superio.asl +++ b/src/superio/ite/it8720f/acpi/superio.asl @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/ite/it8720f/chip.h b/src/superio/ite/it8720f/chip.h index 2c623a997f..f98469c6f4 100644 --- a/src/superio/ite/it8720f/chip.h +++ b/src/superio/ite/it8720f/chip.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8720F_CHIP_H #define SUPERIO_ITE_IT8720F_CHIP_H diff --git a/src/superio/ite/it8720f/it8720f.h b/src/superio/ite/it8720f/it8720f.h index 093e895821..a56a7a4b55 100644 --- a/src/superio/ite/it8720f/it8720f.h +++ b/src/superio/ite/it8720f/it8720f.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2011 QingPei Wang - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8720F_H #define SUPERIO_ITE_IT8720F_H diff --git a/src/superio/ite/it8720f/superio.c b/src/superio/ite/it8720f/superio.c index b5198e7d51..8c7fc695cc 100644 --- a/src/superio/ite/it8720f/superio.c +++ b/src/superio/ite/it8720f/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8721f/Kconfig b/src/superio/ite/it8721f/Kconfig index cf01242d31..a49231c7b9 100644 --- a/src/superio/ite/it8721f/Kconfig +++ b/src/superio/ite/it8721f/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8721F bool diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc index e20bc32e2d..6b515594f5 100644 --- a/src/superio/ite/it8721f/Makefile.inc +++ b/src/superio/ite/it8721f/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 QingPei Wang -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c diff --git a/src/superio/ite/it8721f/acpi/superio.asl b/src/superio/ite/it8721f/acpi/superio.asl index 4c54a4a6e0..0679159332 100644 --- a/src/superio/ite/it8721f/acpi/superio.asl +++ b/src/superio/ite/it8721f/acpi/superio.asl @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index 8f6dfe3017..21d305909c 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2011 QingPei Wang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8721F_H #define SUPERIO_ITE_IT8721F_H diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 5426992ce2..116eaf684a 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2011 QingPei Wang - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 40a2f49529..7092f2bff9 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8728F bool diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index fb75418e43..dc5bedcb8a 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Damien Zammit -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h index 3442439b02..e97b138f7d 100644 --- a/src/superio/ite/it8728f/chip.h +++ b/src/superio/ite/it8728f/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8728F_CHIP_H #define SUPERIO_ITE_IT8728F_CHIP_H diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 3ce1cfb9df..ff89016065 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann - * Copyright (C) 2013 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8728F_H #define SUPERIO_ITE_IT8728F_H diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 58a837ea8f..e53aa3710f 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8772f/Kconfig b/src/superio/ite/it8772f/Kconfig index ad6ba08350..f9a492c200 100644 --- a/src/superio/ite/it8772f/Kconfig +++ b/src/superio/ite/it8772f/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8772F bool diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index 6c06c36740..bd08a1f151 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c diff --git a/src/superio/ite/it8772f/acpi/superio.asl b/src/superio/ite/it8772f/acpi/superio.asl index a8a0564173..c301a79806 100644 --- a/src/superio/ite/it8772f/acpi/superio.asl +++ b/src/superio/ite/it8772f/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index abeff09720..8acf54033c 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8772F_CHIP_H #define SUPERIO_ITE_IT8772F_CHIP_H diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c index d605fb1a9e..00c8f38f6c 100644 --- a/src/superio/ite/it8772f/early_init.c +++ b/src/superio/ite/it8772f/early_init.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 8e8836def0..9445829856 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8772F_H #define SUPERIO_ITE_IT8772F_H diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index bf6726412d..f5388f1821 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8783ef/Kconfig b/src/superio/ite/it8783ef/Kconfig index 0e1f6c3ddd..3bbdd283d7 100644 --- a/src/superio/ite/it8783ef/Kconfig +++ b/src/superio/ite/it8783ef/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 secunet Security Networks AG -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8783EF bool diff --git a/src/superio/ite/it8783ef/Makefile.inc b/src/superio/ite/it8783ef/Makefile.inc index d67a218163..da077e21b7 100644 --- a/src/superio/ite/it8783ef/Makefile.inc +++ b/src/superio/ite/it8783ef/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 secunet Security Networks AG -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8783EF) += superio.c diff --git a/src/superio/ite/it8783ef/acpi/superio.asl b/src/superio/ite/it8783ef/acpi/superio.asl index ed30a810c1..67dcf2692c 100644 --- a/src/superio/ite/it8783ef/acpi/superio.asl +++ b/src/superio/ite/it8783ef/acpi/superio.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/ite/it8783ef/chip.h b/src/superio/ite/it8783ef/chip.h index 2f173aec52..d19869045d 100644 --- a/src/superio/ite/it8783ef/chip.h +++ b/src/superio/ite/it8783ef/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8783EF_CHIP_H #define SUPERIO_ITE_IT8783EF_CHIP_H diff --git a/src/superio/ite/it8783ef/it8783ef.h b/src/superio/ite/it8783ef/it8783ef.h index b2b7edced5..52bba213c6 100644 --- a/src/superio/ite/it8783ef/it8783ef.h +++ b/src/superio/ite/it8783ef/it8783ef.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8783EF_H #define SUPERIO_ITE_IT8783EF_H diff --git a/src/superio/ite/it8783ef/superio.c b/src/superio/ite/it8783ef/superio.c index d734e7c0ba..65ced9589d 100644 --- a/src/superio/ite/it8783ef/superio.c +++ b/src/superio/ite/it8783ef/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig index 9d3f258a5a..19920859ac 100644 --- a/src/superio/ite/it8786e/Kconfig +++ b/src/superio/ite/it8786e/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 secunet Security Networks AG -## Copyright (C) 2018 Libretrend LDA -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_ITE_IT8786E bool diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc index 560957ffc5..6d30694f20 100644 --- a/src/superio/ite/it8786e/Makefile.inc +++ b/src/superio/ite/it8786e/Makefile.inc @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 secunet Security Networks AG -## Copyright (C) 2018 Libretrend LDA -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl index 8ea0df1114..ba210bd0dd 100644 --- a/src/superio/ite/it8786e/acpi/superio.asl +++ b/src/superio/ite/it8786e/acpi/superio.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h index 4b2e811475..abac0f3a39 100644 --- a/src/superio/ite/it8786e/chip.h +++ b/src/superio/ite/it8786e/chip.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8786E_CHIP_H #define SUPERIO_ITE_IT8786E_CHIP_H diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h index b73b71d5b3..4c74f82ac7 100644 --- a/src/superio/ite/it8786e/it8786e.h +++ b/src/superio/ite/it8786e/it8786e.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_ITE_IT8786E_H #define SUPERIO_ITE_IT8786E_H diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c index ac9dc4bc75..ba1bfa3c7a 100644 --- a/src/superio/ite/it8786e/superio.c +++ b/src/superio/ite/it8786e/superio.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 secunet Security Networks AG - * Copyright (C) 2019 Libretrend LDA - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nsc/Makefile.inc b/src/superio/nsc/Makefile.inc index 832359140f..1e9582195f 100644 --- a/src/superio/nsc/Makefile.inc +++ b/src/superio/nsc/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ## include generic nsc pre-ram stage driver bootblock-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c diff --git a/src/superio/nsc/common/Kconfig b/src/superio/nsc/common/Kconfig index e486071410..9b03b717ae 100644 --- a/src/superio/nsc/common/Kconfig +++ b/src/superio/nsc/common/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # Generic NSC romstage driver - Just enough UART initialisation code for # pre-ram. diff --git a/src/superio/nsc/common/early_serial.c b/src/superio/nsc/common/early_serial.c index 0ac146f0aa..d91492056e 100644 --- a/src/superio/nsc/common/early_serial.c +++ b/src/superio/nsc/common/early_serial.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nsc/common/nsc.h b/src/superio/nsc/common/nsc.h index bc123d4d69..a4e438e8e0 100644 --- a/src/superio/nsc/common/nsc.h +++ b/src/superio/nsc/common/nsc.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2014 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NSC_COMMON_PRE_RAM_H #define SUPERIO_NSC_COMMON_PRE_RAM_H diff --git a/src/superio/nsc/pc87382/Kconfig b/src/superio/nsc/pc87382/Kconfig index 9915fabece..cb519edfa6 100644 --- a/src/superio/nsc/pc87382/Kconfig +++ b/src/superio/nsc/pc87382/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NSC_PC87382 bool diff --git a/src/superio/nsc/pc87382/Makefile.inc b/src/superio/nsc/pc87382/Makefile.inc index d538c62731..1ed65b0562 100644 --- a/src/superio/nsc/pc87382/Makefile.inc +++ b/src/superio/nsc/pc87382/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Sven Schnelle -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NSC_PC87382) += superio.c diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h index 6826f4533b..9349b5e86f 100644 --- a/src/superio/nsc/pc87382/pc87382.h +++ b/src/superio/nsc/pc87382/pc87382.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NSC_PC87382_H #define SUPERIO_NSC_PC87382_H diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index c90ebd9b83..48968b166b 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nsc/pc87384/Kconfig b/src/superio/nsc/pc87384/Kconfig index f50e522621..cb344878c2 100644 --- a/src/superio/nsc/pc87384/Kconfig +++ b/src/superio/nsc/pc87384/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NSC_PC87384 bool diff --git a/src/superio/nsc/pc87384/Makefile.inc b/src/superio/nsc/pc87384/Makefile.inc index bd6a875509..eefef1c0c2 100644 --- a/src/superio/nsc/pc87384/Makefile.inc +++ b/src/superio/nsc/pc87384/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Sven Schnelle -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NSC_PC87384) += superio.c diff --git a/src/superio/nsc/pc87384/pc87384.h b/src/superio/nsc/pc87384/pc87384.h index 21845847f7..579def4dea 100644 --- a/src/superio/nsc/pc87384/pc87384.h +++ b/src/superio/nsc/pc87384/pc87384.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NSC_PC87384_H #define SUPERIO_NSC_PC87384_H diff --git a/src/superio/nsc/pc87384/superio.c b/src/superio/nsc/pc87384/superio.c index 87dd265182..14bd059d86 100644 --- a/src/superio/nsc/pc87384/superio.c +++ b/src/superio/nsc/pc87384/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nsc/pc87392/Kconfig b/src/superio/nsc/pc87392/Kconfig index adff8df4ed..b15310bd1a 100644 --- a/src/superio/nsc/pc87392/Kconfig +++ b/src/superio/nsc/pc87392/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NSC_PC87392 bool diff --git a/src/superio/nsc/pc87392/Makefile.inc b/src/superio/nsc/pc87392/Makefile.inc index 98f1ae17d0..02db8e931f 100644 --- a/src/superio/nsc/pc87392/Makefile.inc +++ b/src/superio/nsc/pc87392/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Sven Schnelle -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NSC_PC87392) += superio.c diff --git a/src/superio/nsc/pc87392/pc87392.h b/src/superio/nsc/pc87392/pc87392.h index 5832435ee8..30c85e3c78 100644 --- a/src/superio/nsc/pc87392/pc87392.h +++ b/src/superio/nsc/pc87392/pc87392.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NSC_PC87392_H #define SUPERIO_NSC_PC87392_H diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index 4a5bed29af..a60bab4e04 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nsc/pc87417/Kconfig b/src/superio/nsc/pc87417/Kconfig index 347bab27f2..aae06582eb 100644 --- a/src/superio/nsc/pc87417/Kconfig +++ b/src/superio/nsc/pc87417/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NSC_PC87417 bool diff --git a/src/superio/nsc/pc87417/Makefile.inc b/src/superio/nsc/pc87417/Makefile.inc index b9f0b10732..7addeaeba6 100644 --- a/src/superio/nsc/pc87417/Makefile.inc +++ b/src/superio/nsc/pc87417/Makefile.inc @@ -1,20 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan by yhlu -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index eab4126778..251e7a9bad 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index cb6515d8af..f544ad2c1c 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NSC_PC87417_H #define SUPERIO_NSC_PC87417_H diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index f98ba843ad..320a56394c 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc index d92b453753..55fed51b19 100644 --- a/src/superio/nuvoton/Makefile.inc +++ b/src/superio/nuvoton/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ## include generic nuvoton pre-ram stage driver bootblock-$(CONFIG_SUPERIO_NUVOTON_COMMON_PRE_RAM) += common/early_serial.c diff --git a/src/superio/nuvoton/common/Kconfig b/src/superio/nuvoton/common/Kconfig index 0af556caab..35052e9061 100644 --- a/src/superio/nuvoton/common/Kconfig +++ b/src/superio/nuvoton/common/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # Generic Nuvoton romstage driver - Just enough UART initialisation code for # pre-ram. diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 29418dbf9e..ed31b721fb 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2014 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * A generic romstage (pre-ram) driver for Nuvoton variant Super I/O chips. diff --git a/src/superio/nuvoton/common/hwm.c b/src/superio/nuvoton/common/hwm.c index bfc916fedc..d6c15af7ed 100644 --- a/src/superio/nuvoton/common/hwm.c +++ b/src/superio/nuvoton/common/hwm.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* Nuvoton is a Winbond spin-off, so this code is for both */ diff --git a/src/superio/nuvoton/common/hwm.h b/src/superio/nuvoton/common/hwm.h index 15dcf62448..be47a77727 100644 --- a/src/superio/nuvoton/common/hwm.h +++ b/src/superio/nuvoton/common/hwm.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_COMMON_HWM_H #define SUPERIO_NUVOTON_COMMON_HWM_H diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index 688364a0d2..f5b317671d 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2014 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_COMMON_PRE_RAM_H #define SUPERIO_NUVOTON_COMMON_PRE_RAM_H diff --git a/src/superio/nuvoton/nct5104d/Kconfig b/src/superio/nuvoton/nct5104d/Kconfig index 12ef644f7b..72978c54be 100644 --- a/src/superio/nuvoton/nct5104d/Kconfig +++ b/src/superio/nuvoton/nct5104d/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NCT5104D bool diff --git a/src/superio/nuvoton/nct5104d/Makefile.inc b/src/superio/nuvoton/nct5104d/Makefile.inc index 1c67660736..0a84d4fed4 100644 --- a/src/superio/nuvoton/nct5104d/Makefile.inc +++ b/src/superio/nuvoton/nct5104d/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += superio.c bootblock-$(CONFIG_SUPERIO_NUVOTON_NCT5104D) += early_init.c diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h index d351053cd5..5b790372ad 100644 --- a/src/superio/nuvoton/nct5104d/chip.h +++ b/src/superio/nuvoton/nct5104d/chip.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NCT5104D_CHIP_H #define SUPERIO_NUVOTON_NCT5104D_CHIP_H diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index 3559aba460..60250553a4 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index 3f78c1d0d4..b65e805ddf 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NCT5104D_H #define SUPERIO_NUVOTON_NCT5104D_H diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index 6836d695c0..e49a7cbda5 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/nct5539d/Kconfig b/src/superio/nuvoton/nct5539d/Kconfig index 0dd14022b6..cf2d950ee7 100644 --- a/src/superio/nuvoton/nct5539d/Kconfig +++ b/src/superio/nuvoton/nct5539d/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 Pavel Sayekat -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NCT5539D bool diff --git a/src/superio/nuvoton/nct5539d/Makefile.inc b/src/superio/nuvoton/nct5539d/Makefile.inc index a6f3a022fe..832c81f7cb 100644 --- a/src/superio/nuvoton/nct5539d/Makefile.inc +++ b/src/superio/nuvoton/nct5539d/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2019 Pavel Sayekat -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += superio.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5539D) += ../../common/ssdt.c diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl index ce43a77c54..70a84a28a7 100644 --- a/src/superio/nuvoton/nct5539d/acpi/superio.asl +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * Copyright (C) 2017 Tobias Diedrich - * Copyright (C) 2019 Pavel Sayekat - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/nuvoton/nct5539d/nct5539d.h b/src/superio/nuvoton/nct5539d/nct5539d.h index d4e8d083a9..9d290d3550 100644 --- a/src/superio/nuvoton/nct5539d/nct5539d.h +++ b/src/superio/nuvoton/nct5539d/nct5539d.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Pavel Sayekat - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NCT5539D_H #define SUPERIO_NUVOTON_NCT5539D_H diff --git a/src/superio/nuvoton/nct5539d/superio.c b/src/superio/nuvoton/nct5539d/superio.c index 04461b3abe..5402b2e0fd 100644 --- a/src/superio/nuvoton/nct5539d/superio.c +++ b/src/superio/nuvoton/nct5539d/superio.c @@ -1,23 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 Matt DeVillier - * Copyright (C) 2016 Omar Pakker -* Copyright (C) 2019 Pavel Sayekat - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/nct5572d/Kconfig b/src/superio/nuvoton/nct5572d/Kconfig index 60c886624e..f720f79c3a 100644 --- a/src/superio/nuvoton/nct5572d/Kconfig +++ b/src/superio/nuvoton/nct5572d/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NCT5572D bool diff --git a/src/superio/nuvoton/nct5572d/Makefile.inc b/src/superio/nuvoton/nct5572d/Makefile.inc index b4916f864b..77a9c7f0a5 100644 --- a/src/superio/nuvoton/nct5572d/Makefile.inc +++ b/src/superio/nuvoton/nct5572d/Makefile.inc @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -## Copyright (C) 2014 Felix Held -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT5572D) += superio.c diff --git a/src/superio/nuvoton/nct5572d/nct5572d.h b/src/superio/nuvoton/nct5572d/nct5572d.h index e04abf3cbc..1096b940af 100644 --- a/src/superio/nuvoton/nct5572d/nct5572d.h +++ b/src/superio/nuvoton/nct5572d/nct5572d.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NCT5572D #define SUPERIO_NUVOTON_NCT5572D diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 163d6b92d7..fe1da65db2 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 Timothy Pearson , Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/nct6776/Kconfig b/src/superio/nuvoton/nct6776/Kconfig index 441692bddd..a0a8184315 100644 --- a/src/superio/nuvoton/nct6776/Kconfig +++ b/src/superio/nuvoton/nct6776/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -## Copyright (C) 2014 Felix Held -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NCT6776 bool diff --git a/src/superio/nuvoton/nct6776/Makefile.inc b/src/superio/nuvoton/nct6776/Makefile.inc index 13fe527dd5..bf229c2c13 100644 --- a/src/superio/nuvoton/nct6776/Makefile.inc +++ b/src/superio/nuvoton/nct6776/Makefile.inc @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -## Copyright (C) 2014 Felix Held -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776) += superio.c diff --git a/src/superio/nuvoton/nct6776/acpi/superio.asl b/src/superio/nuvoton/nct6776/acpi/superio.asl index f6aed57dba..748693d771 100644 --- a/src/superio/nuvoton/nct6776/acpi/superio.asl +++ b/src/superio/nuvoton/nct6776/acpi/superio.asl @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * Copyright (C) 2017 Tobias Diedrich - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/nuvoton/nct6776/nct6776.h b/src/superio/nuvoton/nct6776/nct6776.h index 520401e5a0..eb4da5eec4 100644 --- a/src/superio/nuvoton/nct6776/nct6776.h +++ b/src/superio/nuvoton/nct6776/nct6776.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Felix Held - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* Both NCT6776D and NCT6776F package variants are supported. */ diff --git a/src/superio/nuvoton/nct6776/superio.c b/src/superio/nuvoton/nct6776/superio.c index 78e07b66d6..2050bd9092 100644 --- a/src/superio/nuvoton/nct6776/superio.c +++ b/src/superio/nuvoton/nct6776/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/nct6779d/Kconfig b/src/superio/nuvoton/nct6779d/Kconfig index aad9eb4d2a..5217102645 100644 --- a/src/superio/nuvoton/nct6779d/Kconfig +++ b/src/superio/nuvoton/nct6779d/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NCT6779D bool diff --git a/src/superio/nuvoton/nct6779d/Makefile.inc b/src/superio/nuvoton/nct6779d/Makefile.inc index b1ce17a8e1..4058d09580 100644 --- a/src/superio/nuvoton/nct6779d/Makefile.inc +++ b/src/superio/nuvoton/nct6779d/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2015 Matt DeVillier -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6779D) += superio.c diff --git a/src/superio/nuvoton/nct6779d/nct6779d.h b/src/superio/nuvoton/nct6779d/nct6779d.h index 9a1c445e4a..86f1a76582 100644 --- a/src/superio/nuvoton/nct6779d/nct6779d.h +++ b/src/superio/nuvoton/nct6779d/nct6779d.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Matt DeVillier - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NCT6779D_H #define SUPERIO_NUVOTON_NCT6779D_H diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 7ef3488b8c..9eff320477 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 Matt DeVillier - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/nct6791d/Kconfig b/src/superio/nuvoton/nct6791d/Kconfig index 55581fbcfe..5d8bcad871 100644 --- a/src/superio/nuvoton/nct6791d/Kconfig +++ b/src/superio/nuvoton/nct6791d/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Omar Pakker -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NCT6791D bool diff --git a/src/superio/nuvoton/nct6791d/Makefile.inc b/src/superio/nuvoton/nct6791d/Makefile.inc index a1299a4830..f7353652c6 100644 --- a/src/superio/nuvoton/nct6791d/Makefile.inc +++ b/src/superio/nuvoton/nct6791d/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2016 Omar Pakker -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += superio.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6791D) += ../../common/ssdt.c diff --git a/src/superio/nuvoton/nct6791d/nct6791d.h b/src/superio/nuvoton/nct6791d/nct6791d.h index 69855acc2b..aa47bd4815 100644 --- a/src/superio/nuvoton/nct6791d/nct6791d.h +++ b/src/superio/nuvoton/nct6791d/nct6791d.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Omar Pakker - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NCT6791D_H #define SUPERIO_NUVOTON_NCT6791D_H diff --git a/src/superio/nuvoton/nct6791d/superio.c b/src/superio/nuvoton/nct6791d/superio.c index ed8f5c3659..a8e267b912 100644 --- a/src/superio/nuvoton/nct6791d/superio.c +++ b/src/superio/nuvoton/nct6791d/superio.c @@ -1,22 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 Matt DeVillier - * Copyright (C) 2016 Omar Pakker - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/npcd378/Kconfig b/src/superio/nuvoton/npcd378/Kconfig index d72c751d61..f3eb932aa7 100644 --- a/src/superio/nuvoton/npcd378/Kconfig +++ b/src/superio/nuvoton/npcd378/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2018 Patrick Rudolph -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_NPCD378 bool diff --git a/src/superio/nuvoton/npcd378/Makefile.inc b/src/superio/nuvoton/npcd378/Makefile.inc index ca0c824cdd..6dc762605a 100644 --- a/src/superio/nuvoton/npcd378/Makefile.inc +++ b/src/superio/nuvoton/npcd378/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2018 Patrick Rudolph -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_NUVOTON_NPCD378) += superio.c diff --git a/src/superio/nuvoton/npcd378/acpi/superio.asl b/src/superio/nuvoton/npcd378/acpi/superio.asl index 231488053c..41efb50b67 100644 --- a/src/superio/nuvoton/npcd378/acpi/superio.asl +++ b/src/superio/nuvoton/npcd378/acpi/superio.asl @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013, 2016 secunet Security Networks AG - * Copyright (C) 2017 Tobias Diedrich - * Copyright (C) 2018 Patrick Rudolph - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h index cf0b804753..f2fd87b27e 100644 --- a/src/superio/nuvoton/npcd378/npcd378.h +++ b/src/superio/nuvoton/npcd378/npcd378.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Patrick Rudolph - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_NPCD378_H #define SUPERIO_NUVOTON_NPCD378_H diff --git a/src/superio/nuvoton/npcd378/superio.c b/src/superio/nuvoton/npcd378/superio.c index f11e75a550..624c1f0882 100644 --- a/src/superio/nuvoton/npcd378/superio.c +++ b/src/superio/nuvoton/npcd378/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2018 Patrick Rudolph - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/wpcm450/Kconfig b/src/superio/nuvoton/wpcm450/Kconfig index e94b4354e0..19f11a6d6d 100644 --- a/src/superio/nuvoton/wpcm450/Kconfig +++ b/src/superio/nuvoton/wpcm450/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_NUVOTON_WPCM450 bool diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc index 27dc253e80..04a0f07954 100644 --- a/src/superio/nuvoton/wpcm450/Makefile.inc +++ b/src/superio/nuvoton/wpcm450/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c romstage-$(CONFIG_SUPERIO_NUVOTON_WPCM450) += early_init.c diff --git a/src/superio/nuvoton/wpcm450/early_init.c b/src/superio/nuvoton/wpcm450/early_init.c index 0ed5ac338b..56f5b5e9e6 100644 --- a/src/superio/nuvoton/wpcm450/early_init.c +++ b/src/superio/nuvoton/wpcm450/early_init.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index aeb394acca..7bb8eb9375 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/nuvoton/wpcm450/wpcm450.h b/src/superio/nuvoton/wpcm450/wpcm450.h index 6efdb2a9e9..d0d96ad711 100644 --- a/src/superio/nuvoton/wpcm450/wpcm450.h +++ b/src/superio/nuvoton/wpcm450/wpcm450.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_NUVOTON_WPCM450_WPCM450_H #define SUPERIO_NUVOTON_WPCM450_WPCM450_H diff --git a/src/superio/renesas/Makefile.inc b/src/superio/renesas/Makefile.inc index b8df976e8d..b45c63e75d 100644 --- a/src/superio/renesas/Makefile.inc +++ b/src/superio/renesas/Makefile.inc @@ -1,16 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. subdirs-y += m3885x diff --git a/src/superio/renesas/m3885x/Kconfig b/src/superio/renesas/m3885x/Kconfig index 8f48abbf2e..edd2a06fce 100644 --- a/src/superio/renesas/m3885x/Kconfig +++ b/src/superio/renesas/m3885x/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_RENESAS_M3885X bool diff --git a/src/superio/renesas/m3885x/Makefile.inc b/src/superio/renesas/m3885x/Makefile.inc index 5a418d1954..4753f08506 100644 --- a/src/superio/renesas/m3885x/Makefile.inc +++ b/src/superio/renesas/m3885x/Makefile.inc @@ -1,16 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_RENESAS_M3885X) += superio.c diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 4bc590f79c..e860c4293f 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/serverengines/Makefile.inc b/src/superio/serverengines/Makefile.inc index d97009251a..13c881ec5a 100644 --- a/src/superio/serverengines/Makefile.inc +++ b/src/superio/serverengines/Makefile.inc @@ -1,16 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. subdirs-y += pilot diff --git a/src/superio/serverengines/pilot/Kconfig b/src/superio/serverengines/pilot/Kconfig index 53624a115d..962ddcdf62 100644 --- a/src/superio/serverengines/pilot/Kconfig +++ b/src/superio/serverengines/pilot/Kconfig @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SERVERENGINES_PILOT bool diff --git a/src/superio/serverengines/pilot/Makefile.inc b/src/superio/serverengines/pilot/Makefile.inc index 95c62f5eec..a7bac23618 100644 --- a/src/superio/serverengines/pilot/Makefile.inc +++ b/src/superio/serverengines/pilot/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_init.c bootblock-$(CONFIG_SUPERIO_SERVERENGINES_PILOT) += early_serial.c diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 3509fb47ec..f1fbe730a7 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Univ. Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* PILOT Super I/O is only based on LPC observation done on factory system. */ diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 3c140fb8c9..7ce3394d69 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Univ. Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* PILOT Super I/O is only based on LPC observation done on factory system. */ diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index a88f0e6066..6fc835b439 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 University of Heidelberg - * Written by Mondrian Nuessle for Univ. Heidelberg - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SERVERENGINES_PILOT_PILOT_H #define SUPERIO_SERVERENGINES_PILOT_PILOT_H diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 9b86745069..af43fefaaa 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. subdirs-y += dme1737 subdirs-y += fdc37n972 diff --git a/src/superio/smsc/fdc37n972/Kconfig b/src/superio/smsc/fdc37n972/Kconfig index 4a614f0f40..c93e2d5bc1 100644 --- a/src/superio/smsc/fdc37n972/Kconfig +++ b/src/superio/smsc/fdc37n972/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_FDC37N972 bool diff --git a/src/superio/smsc/fdc37n972/Makefile.inc b/src/superio/smsc/fdc37n972/Makefile.inc index 235d7ae0ab..b45496b536 100644 --- a/src/superio/smsc/fdc37n972/Makefile.inc +++ b/src/superio/smsc/fdc37n972/Makefile.inc @@ -1,16 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_SMSC_FDC37N972) += superio.c diff --git a/src/superio/smsc/fdc37n972/fdc37n972.h b/src/superio/smsc/fdc37n972/fdc37n972.h index 19225ae92a..eb8a89c380 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.h +++ b/src/superio/smsc/fdc37n972/fdc37n972.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_FDC37N972_H #define SUPERIO_SMSC_FDC37N972_H diff --git a/src/superio/smsc/fdc37n972/superio.c b/src/superio/smsc/fdc37n972/superio.c index 3706dec762..bf8e35fc8e 100644 --- a/src/superio/smsc/fdc37n972/superio.c +++ b/src/superio/smsc/fdc37n972/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/kbc1100/Kconfig b/src/superio/smsc/kbc1100/Kconfig index 8b8d45d4cd..5c5bd6f2ea 100644 --- a/src/superio/smsc/kbc1100/Kconfig +++ b/src/superio/smsc/kbc1100/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_KBC1100 bool diff --git a/src/superio/smsc/kbc1100/Makefile.inc b/src/superio/smsc/kbc1100/Makefile.inc index 5da94942a8..f51b3ff236 100644 --- a/src/superio/smsc/kbc1100/Makefile.inc +++ b/src/superio/smsc/kbc1100/Makefile.inc @@ -1,17 +1,5 @@ -# +# SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. -# -# Copyright (C) 2011 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# bootblock-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c romstage-$(CONFIG_SUPERIO_SMSC_KBC1100) += early_init.c diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c index fc3604372e..7d8426ce66 100644 --- a/src/superio/smsc/kbc1100/early_init.c +++ b/src/superio/smsc/kbc1100/early_init.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 8531643b33..ce560ac44e 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_KBC1100_H #define SUPERIO_SMSC_KBC1100_H diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 9de88e2733..5b1ee544a2 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* RAM driver for the SMSC KBC1100 Super I/O chip */ diff --git a/src/superio/smsc/lpc47m10x/Kconfig b/src/superio/smsc/lpc47m10x/Kconfig index a22965c8f9..a4f90cc18c 100644 --- a/src/superio/smsc/lpc47m10x/Kconfig +++ b/src/superio/smsc/lpc47m10x/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_LPC47M10X bool diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc index 278aa1eabb..9dd147fb6a 100644 --- a/src/superio/smsc/lpc47m10x/Makefile.inc +++ b/src/superio/smsc/lpc47m10x/Makefile.inc @@ -1,22 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan -## Copyright (C) 2005 Digital Design Corporation -## Copyright (C) 2006 Ron Minnich, LANL -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 719faf4bc3..892ef3d92c 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index 0c393c5344..d096b37848 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -1,20 +1,5 @@ -/* - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2006 Ron Minnich, LANL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_LPC47M10X_H #define SUPERIO_SMSC_LPC47M10X_H diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index a4e3799cd8..2a693d654e 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -1,22 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2006 Ron Minnich, LANL - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/lpc47m15x/Kconfig b/src/superio/smsc/lpc47m15x/Kconfig index d11c81a9a3..b716f88df5 100644 --- a/src/superio/smsc/lpc47m15x/Kconfig +++ b/src/superio/smsc/lpc47m15x/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_LPC47M15X bool diff --git a/src/superio/smsc/lpc47m15x/Makefile.inc b/src/superio/smsc/lpc47m15x/Makefile.inc index dc6b9ab3ba..78dbf2c91a 100644 --- a/src/superio/smsc/lpc47m15x/Makefile.inc +++ b/src/superio/smsc/lpc47m15x/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += early_serial.c diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index aab603bc9e..c924a728d0 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Pre-RAM driver for the SMSC LPC47M15X Super I/O chip */ diff --git a/src/superio/smsc/lpc47m15x/lpc47m15x.h b/src/superio/smsc/lpc47m15x/lpc47m15x.h index e905e9a843..44fce874ba 100644 --- a/src/superio/smsc/lpc47m15x/lpc47m15x.h +++ b/src/superio/smsc/lpc47m15x/lpc47m15x.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_LPC47M15X_H #define SUPERIO_SMSC_LPC47M15X_H diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 40eb7d25b1..21b9eb9326 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* RAM driver for the SMSC LPC47M15X Super I/O chip */ diff --git a/src/superio/smsc/lpc47n207/Kconfig b/src/superio/smsc/lpc47n207/Kconfig index f5bc5be12c..aa4be5ad9a 100644 --- a/src/superio/smsc/lpc47n207/Kconfig +++ b/src/superio/smsc/lpc47n207/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_LPC47N207 bool diff --git a/src/superio/smsc/lpc47n207/Makefile.inc b/src/superio/smsc/lpc47n207/Makefile.inc index 65a0939e9e..698999b2cf 100644 --- a/src/superio/smsc/lpc47n207/Makefile.inc +++ b/src/superio/smsc/lpc47n207/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_LPC47N207) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47N207) += early_serial.c diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index 9bda334b84..c091bc461e 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h index f8e06c89c6..fe18e5277f 100644 --- a/src/superio/smsc/lpc47n207/lpc47n207.h +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_LPC47N207_H #define SUPERIO_SMSC_LPC47N207_H diff --git a/src/superio/smsc/lpc47n217/Kconfig b/src/superio/smsc/lpc47n217/Kconfig index b52c360b31..6e8f09e489 100644 --- a/src/superio/smsc/lpc47n217/Kconfig +++ b/src/superio/smsc/lpc47n217/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_LPC47N217 bool diff --git a/src/superio/smsc/lpc47n217/Makefile.inc b/src/superio/smsc/lpc47n217/Makefile.inc index a643407fbf..eb3f3228df 100644 --- a/src/superio/smsc/lpc47n217/Makefile.inc +++ b/src/superio/smsc/lpc47n217/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2005 Digital Design Corporation -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += early_serial.c diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 8037ee890d..84416c5868 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* Pre-RAM driver for SMSC LPC47N217 Super I/O chip. */ diff --git a/src/superio/smsc/lpc47n217/lpc47n217.h b/src/superio/smsc/lpc47n217/lpc47n217.h index 13b9bf3697..6e2313b7ca 100644 --- a/src/superio/smsc/lpc47n217/lpc47n217.h +++ b/src/superio/smsc/lpc47n217/lpc47n217.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_LPC47N217_LPC47N217_H #define SUPERIO_SMSC_LPC47N217_LPC47N217_H diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c index 1b34bec27c..f7069445d9 100644 --- a/src/superio/smsc/lpc47n217/superio.c +++ b/src/superio/smsc/lpc47n217/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2005 Digital Design Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */ diff --git a/src/superio/smsc/lpc47n227/Kconfig b/src/superio/smsc/lpc47n227/Kconfig index 5c32829303..3c9be6787f 100644 --- a/src/superio/smsc/lpc47n227/Kconfig +++ b/src/superio/smsc/lpc47n227/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_LPC47N227 bool diff --git a/src/superio/smsc/lpc47n227/Makefile.inc b/src/superio/smsc/lpc47n227/Makefile.inc index 4bb0dac64a..3e01cb8ed7 100644 --- a/src/superio/smsc/lpc47n227/Makefile.inc +++ b/src/superio/smsc/lpc47n227/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_LPC47N227) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_LPC47N227) += early_serial.c diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 9e6ecd7d13..091a88f539 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Pre-RAM driver for SMSC LPC47N227 Super I/O chip. */ diff --git a/src/superio/smsc/lpc47n227/lpc47n227.h b/src/superio/smsc/lpc47n227/lpc47n227.h index 5e30f65f01..60418ef0bf 100644 --- a/src/superio/smsc/lpc47n227/lpc47n227.h +++ b/src/superio/smsc/lpc47n227/lpc47n227.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_LPC47N227_LPC47N227_H #define SUPERIO_SMSC_LPC47N227_LPC47N227_H diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 911343d890..923a7665d2 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* RAM-based driver for SMSC LPC47N227 Super I/O chip. */ diff --git a/src/superio/smsc/mec1308/Kconfig b/src/superio/smsc/mec1308/Kconfig index dc5061f60d..559be63cbe 100644 --- a/src/superio/smsc/mec1308/Kconfig +++ b/src/superio/smsc/mec1308/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_MEC1308 bool diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc index 4a60cf66c6..a4f8bed0f6 100644 --- a/src/superio/smsc/mec1308/Makefile.inc +++ b/src/superio/smsc/mec1308/Makefile.inc @@ -1,16 +1,4 @@ -# +# SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. -# -# Copyright (C) 2011 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl index cc174f96ae..2d99efe5bd 100644 --- a/src/superio/smsc/mec1308/acpi/superio.asl +++ b/src/superio/smsc/mec1308/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/superio/smsc/mec1308/mec1308.h b/src/superio/smsc/mec1308/mec1308.h index 77aac842f8..5450c53836 100644 --- a/src/superio/smsc/mec1308/mec1308.h +++ b/src/superio/smsc/mec1308/mec1308.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_MEC1308_H #define SUPERIO_SMSC_MEC1308_H diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 106b8ad500..fa2f851f78 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* RAM driver for the SMSC MEC1308 Super I/O chip */ diff --git a/src/superio/smsc/sch5147/acpi/superio.asl b/src/superio/smsc/sch5147/acpi/superio.asl index 6314d81cd4..15467b4c16 100644 --- a/src/superio/smsc/sch5147/acpi/superio.asl +++ b/src/superio/smsc/sch5147/acpi/superio.asl @@ -1,15 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/smsc/sio1007/Kconfig b/src/superio/smsc/sio1007/Kconfig index 87aa56d412..74ab4b15bd 100644 --- a/src/superio/smsc/sio1007/Kconfig +++ b/src/superio/smsc/sio1007/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_SIO1007 bool diff --git a/src/superio/smsc/sio1007/Makefile.inc b/src/superio/smsc/sio1007/Makefile.inc index 20a0b2a165..0a8a652769 100644 --- a/src/superio/smsc/sio1007/Makefile.inc +++ b/src/superio/smsc/sio1007/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Sage Electronic Engineering LLC. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_SIO1007) += early_serial.c diff --git a/src/superio/smsc/sio1007/acpi/superio.asl b/src/superio/smsc/sio1007/acpi/superio.asl index a8a0564173..c301a79806 100644 --- a/src/superio/smsc/sio1007/acpi/superio.asl +++ b/src/superio/smsc/sio1007/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ // Scope is \_SB.PCI0.LPCB diff --git a/src/superio/smsc/sio1007/early_serial.c b/src/superio/smsc/sio1007/early_serial.c index 2028e67fc3..bb22604b26 100644 --- a/src/superio/smsc/sio1007/early_serial.c +++ b/src/superio/smsc/sio1007/early_serial.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/sio1007/sio1007.h b/src/superio/smsc/sio1007/sio1007.h index a99ec5c273..d69d95c679 100644 --- a/src/superio/smsc/sio1007/sio1007.h +++ b/src/superio/smsc/sio1007/sio1007.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Sage Electronic Engineering LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_SIO1007_H #define SUPERIO_SMSC_SIO1007_H diff --git a/src/superio/smsc/sio1036/Kconfig b/src/superio/smsc/sio1036/Kconfig index df519de71b..e9b884f658 100644 --- a/src/superio/smsc/sio1036/Kconfig +++ b/src/superio/smsc/sio1036/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_SIO1036 bool diff --git a/src/superio/smsc/sio1036/Makefile.inc b/src/superio/smsc/sio1036/Makefile.inc index e9fdae2dc8..5d85d7caa3 100644 --- a/src/superio/smsc/sio1036/Makefile.inc +++ b/src/superio/smsc/sio1036/Makefile.inc @@ -1,17 +1,5 @@ -# +# SPDX-License-Identifier: GPL-2.0-only # This file is part of the coreboot project. -# -# Copyright (C) 2012 Advanced Micro Devices, Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# bootblock-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c romstage-$(CONFIG_SUPERIO_SMSC_SIO1036) += sio1036_early_init.c diff --git a/src/superio/smsc/sio1036/sio1036.h b/src/superio/smsc/sio1036/sio1036.h index 610beba59c..db00181723 100644 --- a/src/superio/smsc/sio1036/sio1036.h +++ b/src/superio/smsc/sio1036/sio1036.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_SIO1306_H #define SUPERIO_SMSC_SIO1306_H diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 26a2a3eb4b..b5e9ae818b 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* Pre-RAM driver for the SMSC KBC1100 Super I/O chip */ diff --git a/src/superio/smsc/sio1036/superio.c b/src/superio/smsc/sio1036/superio.c index c39d0970c6..c249df6c2f 100644 --- a/src/superio/smsc/sio1036/superio.c +++ b/src/superio/smsc/sio1036/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* RAM driver for the SMSC SIO1036 Super I/O chip */ diff --git a/src/superio/smsc/sio10n268/Kconfig b/src/superio/smsc/sio10n268/Kconfig index c3b282a572..9e3e9a38f8 100644 --- a/src/superio/smsc/sio10n268/Kconfig +++ b/src/superio/smsc/sio10n268/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_SMSC_SIO10N268 bool diff --git a/src/superio/smsc/sio10n268/Makefile.inc b/src/superio/smsc/sio10n268/Makefile.inc index 2241db3165..f56608a6cb 100644 --- a/src/superio/smsc/sio10n268/Makefile.inc +++ b/src/superio/smsc/sio10n268/Makefile.inc @@ -1,16 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 coresystems GmbH -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_SMSC_SIO10N268) += superio.c diff --git a/src/superio/smsc/sio10n268/sio10n268.h b/src/superio/smsc/sio10n268/sio10n268.h index afc9f05b9e..0709b92878 100644 --- a/src/superio/smsc/sio10n268/sio10n268.h +++ b/src/superio/smsc/sio10n268/sio10n268.h @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_SIO10N268_SIO10N268_H #define SUPERIO_SMSC_SIO10N268_SIO10N268_H diff --git a/src/superio/smsc/sio10n268/superio.c b/src/superio/smsc/sio10n268/superio.c index cf432a09b8..8765a6d978 100644 --- a/src/superio/smsc/sio10n268/superio.c +++ b/src/superio/smsc/sio10n268/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/smscsuperio/Kconfig b/src/superio/smsc/smscsuperio/Kconfig index 238d4f0cc7..0ae69e170c 100644 --- a/src/superio/smsc/smscsuperio/Kconfig +++ b/src/superio/smsc/smscsuperio/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WANTS_14MHZ_CLOCK bool diff --git a/src/superio/smsc/smscsuperio/Makefile.inc b/src/superio/smsc/smscsuperio/Makefile.inc index b9bf35ce80..bc87f2a097 100644 --- a/src/superio/smsc/smscsuperio/Makefile.inc +++ b/src/superio/smsc/smscsuperio/Makefile.inc @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 Uwe Hermann -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += early_serial.c romstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += early_serial.c diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index f058564ee6..38027d522e 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/smsc/smscsuperio/smscsuperio.h b/src/superio/smsc/smscsuperio/smscsuperio.h index c42328c09b..69d5a3fd49 100644 --- a/src/superio/smsc/smscsuperio/smscsuperio.h +++ b/src/superio/smsc/smscsuperio/smscsuperio.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_SMSC_SMSCSUPERIO_H #define SUPERIO_SMSC_SMSCSUPERIO_H diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 0e86683da3..6a51ab6fbb 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * Generic driver for pretty much all known Standard Microsystems Corporation diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index 49430815f1..d2915df89b 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -1,17 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. ## include generic winbond pre-ram stage driver bootblock-$(CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM) += common/early_init.c diff --git a/src/superio/winbond/common/Kconfig b/src/superio/winbond/common/Kconfig index a2f7724dd3..5adcc51b5a 100644 --- a/src/superio/winbond/common/Kconfig +++ b/src/superio/winbond/common/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. # Generic Winbond romstage driver - Just enough UART initialisation code for # romstage. diff --git a/src/superio/winbond/common/early_init.c b/src/superio/winbond/common/early_init.c index b1b8c27693..0e9e8626ba 100644 --- a/src/superio/winbond/common/early_init.c +++ b/src/superio/winbond/common/early_init.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ /* * A generic romstage (pre-ram) driver for various Winbond Super I/O chips. diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 29bfbf5ab3..58297e59d0 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_COMMON_PRE_RAM_H #define SUPERIO_WINBOND_COMMON_PRE_RAM_H diff --git a/src/superio/winbond/w83627dhg/Kconfig b/src/superio/winbond/w83627dhg/Kconfig index 9a51943ea9..f4437bd3de 100644 --- a/src/superio/winbond/w83627dhg/Kconfig +++ b/src/superio/winbond/w83627dhg/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83627DHG bool diff --git a/src/superio/winbond/w83627dhg/Makefile.inc b/src/superio/winbond/w83627dhg/Makefile.inc index 4075a41dc7..31cc36fbf9 100644 --- a/src/superio/winbond/w83627dhg/Makefile.inc +++ b/src/superio/winbond/w83627dhg/Makefile.inc @@ -1,19 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2008 Uwe Hermann -## Copyright (C) 2012 Advanced Micro Devices, Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. bootblock-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c romstage-$(CONFIG_SUPERIO_WINBOND_W83627DHG) += early_serial.c diff --git a/src/superio/winbond/w83627dhg/acpi/superio.asl b/src/superio/winbond/w83627dhg/acpi/superio.asl index e1f2e383d8..cb6a4a7386 100644 --- a/src/superio/winbond/w83627dhg/acpi/superio.asl +++ b/src/superio/winbond/w83627dhg/acpi/superio.asl @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013 secunet Security Networks AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 4bea6785fe..db72070311 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index bd9900ba14..8190815510 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 004d5e8abb..889c4f1bed 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Uwe Hermann - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83627DHG_H #define SUPERIO_WINBOND_W83627DHG_H diff --git a/src/superio/winbond/w83627ehg/Kconfig b/src/superio/winbond/w83627ehg/Kconfig index a00749164b..fcb8470b45 100644 --- a/src/superio/winbond/w83627ehg/Kconfig +++ b/src/superio/winbond/w83627ehg/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83627EHG bool diff --git a/src/superio/winbond/w83627ehg/Makefile.inc b/src/superio/winbond/w83627ehg/Makefile.inc index 88fb0f243f..2a43105fad 100644 --- a/src/superio/winbond/w83627ehg/Makefile.inc +++ b/src/superio/winbond/w83627ehg/Makefile.inc @@ -1,18 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007 AMD -## Written by Yinghai Lu for AMD. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_WINBOND_W83627EHG) += superio.c diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index 35fca01df5..ba817be78e 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index e74dbef41b..1dc7376c04 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83627EHG_H #define SUPERIO_WINBOND_W83627EHG_H diff --git a/src/superio/winbond/w83627hf/Kconfig b/src/superio/winbond/w83627hf/Kconfig index f0ebb82a63..866005a44e 100644 --- a/src/superio/winbond/w83627hf/Kconfig +++ b/src/superio/winbond/w83627hf/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83627HF bool diff --git a/src/superio/winbond/w83627hf/Makefile.inc b/src/superio/winbond/w83627hf/Makefile.inc index 09b9368dd7..7f8d1ce0b4 100644 --- a/src/superio/winbond/w83627hf/Makefile.inc +++ b/src/superio/winbond/w83627hf/Makefile.inc @@ -1,19 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan By LYH change from PC87360 -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_WINBOND_W83627HF) += superio.c diff --git a/src/superio/winbond/w83627hf/acpi/superio.asl b/src/superio/winbond/w83627hf/acpi/superio.asl index 87c13ac9a8..c1293ffc93 100644 --- a/src/superio/winbond/w83627hf/acpi/superio.asl +++ b/src/superio/winbond/w83627hf/acpi/superio.asl @@ -1,17 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * include this file into a mainboard's DSDT _SB device tree and it will expose the diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index 4d76052f7b..8cd2d919c5 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -1,21 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * Copyright (C) 2010 Win Enterprises (anishp@win-ent.com) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index ecbf050ba4..403eedeebb 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83627HF_H #define SUPERIO_WINBOND_W83627HF_H diff --git a/src/superio/winbond/w83627thg/Kconfig b/src/superio/winbond/w83627thg/Kconfig index af54fb8157..5feb8ce2d0 100644 --- a/src/superio/winbond/w83627thg/Kconfig +++ b/src/superio/winbond/w83627thg/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83627THG bool diff --git a/src/superio/winbond/w83627thg/Makefile.inc b/src/superio/winbond/w83627thg/Makefile.inc index 611db82d09..642294ea29 100644 --- a/src/superio/winbond/w83627thg/Makefile.inc +++ b/src/superio/winbond/w83627thg/Makefile.inc @@ -1,19 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan By LYH change from PC87360 -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_WINBOND_W83627THG) += superio.c diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index 875a4a89b5..d70ed0181e 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index d254e53c09..33a02938e8 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83627THG_W83627THG_H #define SUPERIO_WINBOND_W83627THG_W83627THG_H diff --git a/src/superio/winbond/w83627uhg/Kconfig b/src/superio/winbond/w83627uhg/Kconfig index d42987a299..175a61bc3b 100644 --- a/src/superio/winbond/w83627uhg/Kconfig +++ b/src/superio/winbond/w83627uhg/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83627UHG bool diff --git a/src/superio/winbond/w83627uhg/Makefile.inc b/src/superio/winbond/w83627uhg/Makefile.inc index caf9729dea..3dbd93edb9 100644 --- a/src/superio/winbond/w83627uhg/Makefile.inc +++ b/src/superio/winbond/w83627uhg/Makefile.inc @@ -1,17 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Dynon Avionics -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.c diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index e78374076e..a1fc6777ea 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Dynon Avionics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83627uhg/w83627uhg.h b/src/superio/winbond/w83627uhg/w83627uhg.h index 5ba4a1069f..c2b231d006 100644 --- a/src/superio/winbond/w83627uhg/w83627uhg.h +++ b/src/superio/winbond/w83627uhg/w83627uhg.h @@ -1,18 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 Dynon Avionics - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83627UHG_W83627UHG_H #define SUPERIO_WINBOND_W83627UHG_W83627UHG_H diff --git a/src/superio/winbond/w83667hg-a/Kconfig b/src/superio/winbond/w83667hg-a/Kconfig index dc14c5fa14..06f2eaf10c 100644 --- a/src/superio/winbond/w83667hg-a/Kconfig +++ b/src/superio/winbond/w83667hg-a/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83667HG_A bool diff --git a/src/superio/winbond/w83667hg-a/Makefile.inc b/src/superio/winbond/w83667hg-a/Makefile.inc index 7665046acd..4e47f91272 100644 --- a/src/superio/winbond/w83667hg-a/Makefile.inc +++ b/src/superio/winbond/w83667hg-a/Makefile.inc @@ -1,19 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. -## Copyright (C) 2014 Felix Held -## Copyright (C) 2015 Raptor Engineering -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_WINBOND_W83667HG_A) += superio.c diff --git a/src/superio/winbond/w83667hg-a/ps2_controller.asl b/src/superio/winbond/w83667hg-a/ps2_controller.asl index c3b5c758fa..e3dd1dc7a2 100644 --- a/src/superio/winbond/w83667hg-a/ps2_controller.asl +++ b/src/superio/winbond/w83667hg-a/ps2_controller.asl @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (c) 2013 Vladimir Serbinenko - * Copyright (c) 2015 Raptor Engineering - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* SuperIO control port */ Name (SPIO, 0x2E) diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index d0f4eef90d..bc7bd92d03 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Felix Held - * Copyright (C) 2014 Edward O'Callaghan - * Copyright (C) 2015 - 2016 Raptor Engineering - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83667hg-a/w83667hg-a.h b/src/superio/winbond/w83667hg-a/w83667hg-a.h index d4e711094d..7b666957b7 100644 --- a/src/superio/winbond/w83667hg-a/w83667hg-a.h +++ b/src/superio/winbond/w83667hg-a/w83667hg-a.h @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Felix Held - * Copyright (C) 2015 - 2016 Raptor Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83667HG_A #define SUPERIO_WINBOND_W83667HG_A diff --git a/src/superio/winbond/w83977tf/Kconfig b/src/superio/winbond/w83977tf/Kconfig index 92a24046cd..d656b67884 100644 --- a/src/superio/winbond/w83977tf/Kconfig +++ b/src/superio/winbond/w83977tf/Kconfig @@ -1,18 +1,5 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2009 Ronald G. Minnich -## Copyright (C) 2014 Edward O'Callaghan -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-only +# This file is part of the coreboot project. config SUPERIO_WINBOND_W83977TF bool diff --git a/src/superio/winbond/w83977tf/Makefile.inc b/src/superio/winbond/w83977tf/Makefile.inc index 5d5a4ea44b..c407bbf27e 100644 --- a/src/superio/winbond/w83977tf/Makefile.inc +++ b/src/superio/winbond/w83977tf/Makefile.inc @@ -1,19 +1,4 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2000 AG Electronics Ltd. -## Copyright (C) 2003-2004 Linux Networx -## Copyright (C) 2004 Tyan By LYH change from PC87360 -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## +# SPDX-License-Identifier: GPL-2.0-or-later +# This file is part of the coreboot project. ramstage-$(CONFIG_SUPERIO_WINBOND_W83977TF) += superio.c diff --git a/src/superio/winbond/w83977tf/acpi/superio.asl b/src/superio/winbond/w83977tf/acpi/superio.asl index a83cab79fb..e2ff2ef1d6 100644 --- a/src/superio/winbond/w83977tf/acpi/superio.asl +++ b/src/superio/winbond/w83977tf/acpi/superio.asl @@ -1,19 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Christoph Grenz - * Copyright (C) 2013 secunet Security Networks AG - * Copyright (C) 2017 Keith Hui - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a southbridge ASL block and it will diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index b11e5be577..b56bb9c325 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #include #include diff --git a/src/superio/winbond/w83977tf/w83977tf.h b/src/superio/winbond/w83977tf/w83977tf.h index 1106a1c61e..54f5bed59e 100644 --- a/src/superio/winbond/w83977tf/w83977tf.h +++ b/src/superio/winbond/w83977tf/w83977tf.h @@ -1,20 +1,5 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2000 AG Electronics Ltd. - * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* This file is part of the coreboot project. */ #ifndef SUPERIO_WINBOND_W83977TF_W83977TF_H #define SUPERIO_WINBOND_W83977TF_W83977TF_H From 805b29183086008b3934d9210de753a2ffe3d231 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 29 Jan 2020 12:40:56 +0100 Subject: [PATCH 028/151] util/lint: Update spelling.txt from lintian data set commit 1191c09201b43aab55333a70d056d0c355abe329 at https://salsa.debian.org/agx/lintian/tree/master/data/spelling provides a much more comprehensive collection of misspellings, so merge it in. While at it, also sort the file for future easier merging which is the main reason that some lines appear to be removed: they're merely moved. For sorting, I adapted their make rule: make -f - sort-spelling.txt <<'EOF' .RECIPEPREFIX=% sort-%: % %csplit --prefix $<- $< '/^$$/' %LC_ALL=en_US sort -u $<-01 | cat $<-00 - > $< %rm -f $<-0[01] EOF Change-Id: I939e3a8820c88d0e639bd29b46a86b72bce1a098 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38632 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/lint/spelling.txt | 8576 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 8410 insertions(+), 166 deletions(-) diff --git a/util/lint/spelling.txt b/util/lint/spelling.txt index 1f2752b2ee..1263144d9e 100644 --- a/util/lint/spelling.txt +++ b/util/lint/spelling.txt @@ -8,1467 +8,9711 @@ # mistake||correction # # Note that "sepc" and "acknowledgement" have been commented out. + +#acknowledgement||acknowledgment +#sepc||spec +ACII||ASCII +Debiab||Debian +FTBS||FTBFS +POSIX-complient||POSIX-compliant +READEME||README +aaccessibility||accessibility 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+weigth||weight +weired||weird +were'nt||wasn't +werent||weren't wether||whether whataver||whatever +whatepsaces||whitespaces +whatepsace||whitespace whcih||which +wheather||whether whenver||whenever +wheras||whereas +whereever||wherever wheter||whether whe||when +whiped||wiped +whishlist||wishlist +whish||wish +whitch||which +whitepsaces||whitespaces +whitepsace||whitespace +whithout||without +whith||with +wiat||wait +wich||which +widgit||widget +widht||width wierd||weird +wihich||which +wihout||without +wiht||with +wih||with wiil||will +wikpedia||wikipedia +wilcards||wildcards +wilcard||wildcard +willl||will +wipoing||wiping +wirtable||writable +wirters||writers +wirter||writer +wirtes||writes wirte||write +wirth||with +wirting||writing +wirtten||written +wirtual||virtual +witable||writeable +withe||with withing||within +withought||without +withough||without +withoug||without +withouth||without +withthe||with the +witht||with +witin||within +wnated||wanted +wnating||wanting +wnats||wants wnat||want +woithout||without +wont||won't workarould||workaround +workaroung||workaround +workarrounds||workarounds +workarround||workaround +workes||works +workpsaces||workspaces +workpsace||workspace +workspsaces||workspaces +workspsace||workspace +workstaiton||workstation +worthing||meriting +woudn't||wouldn't +woud||would +would'nt||wouldn't +would't||wouldn't +wraper||wrapper +wrappng||wrapping writeing||writing +writen||written writting||writing +wroked||worked +wroks||works +wrok||work wtih||with +xepectedly||expectedly +xepected||expected +xepecting||expecting +xepects||expects +xepect||expect +xgetttext||xgettext +xour||your +xwindows||X +yau||you +yeilded||yielded +yeilding||yielding +yeilds||yields +yeild||yield +yelded||yielded +yelding||yielding +yelds||yields +yeld||yield +yur||your +ziped||zipped zombe||zombie zomebie||zombie From 01cfecc8832580f5d28051de76b047a37d3fb46a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 29 Jan 2020 13:31:16 +0100 Subject: [PATCH 029/151] util/cbfstool: Fix typos Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/cbfstool/*.c Change-Id: I13a27407bf2bad4b9fadcec8cdbd5889068f13cf Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38633 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/cbfstool/cbfs-mkpayload.c | 2 +- util/cbfstool/cbfs_image.c | 2 +- util/cbfstool/elfheaders.c | 2 +- util/cbfstool/fit.c | 2 +- util/cbfstool/ifwitool.c | 6 +++--- util/cbfstool/rmodule.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index d6c10adc7e..830fe16fc1 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -115,7 +115,7 @@ int parse_elf_to_payload(const struct buffer *input, struct buffer *output, } /* Now, regular headers - we only care about PT_LOAD headers, - * because thats what we're actually going to load + * because that's what we're actually going to load */ for (i = 0; i < headers; i++) { diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 452c9d9a04..9bf3688304 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -576,7 +576,7 @@ int cbfs_compact_instance(struct cbfs_image *image) continue; /* At this point prev is an empty entry. Put the non-empty - * file in prev's location. Then add a new emptry entry. This + * file in prev's location. Then add a new empty entry. This * essentialy bubbles empty entries towards the end. */ prev_size = cbfs_file_entry_size(prev); diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c index 676a635b8a..53fe7a1fca 100644 --- a/util/cbfstool/elfheaders.c +++ b/util/cbfstool/elfheaders.c @@ -658,7 +658,7 @@ void elf_init_eheader(Elf64_Ehdr *ehdr, int machine, int nbits, int endian) } } -/* Arbitray maximum number of sections. */ +/* Arbitrary maximum number of sections. */ #define MAX_SECTIONS 16 struct elf_writer_section { Elf64_Shdr shdr; diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index ee12c96610..8ba50f7919 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -172,7 +172,7 @@ static inline size_t fit_free_space(struct fit_table *fit, * This one is critical, as mentioned in Chapter 1.2.1 "FIT Ordering Rules" * "Firmware Interface Table BIOS Specification". * - * We need to use a stable sorting algortihm, as the order of + * We need to use a stable sorting algorithm, as the order of * FIT_TYPE_BIOS_STARTUP matter for measurements. */ static void sort_fit_table(struct fit_table *fit) diff --git a/util/cbfstool/ifwitool.c b/util/cbfstool/ifwitool.c index 76b84e26df..b25db4f099 100644 --- a/util/cbfstool/ifwitool.c +++ b/util/cbfstool/ifwitool.c @@ -387,7 +387,7 @@ static void alloc_buffer(struct buffer *b, size_t s, const char *n) /* * Read header/entry members in little-endian format. - * Returns the offset upto which the read was performed. + * Returns the offset up to which the read was performed. */ static size_t read_member(void *src, size_t offset, size_t size_bytes, void *dst) @@ -415,7 +415,7 @@ static size_t read_member(void *src, size_t offset, size_t size_bytes, /* * Convert to little endian format. - * Returns the offset upto which the fixup was performed. + * Returns the offset up to which the fixup was performed. */ static size_t fix_member(void *data, size_t offset, size_t size_bytes) { @@ -677,7 +677,7 @@ static size_t read_subpart_buf(void *data, size_t size, struct bpdt_entry *e, /* * Sub-partitions in IFWI image are not in the same order as - * in BPDT entries. BPDT entires are in header_order whereas + * in BPDT entries. BPDT entries are in header_order whereas * sub-partition offsets in the image are in pack_order. */ if ((e[i].offset + e[i].size) > max_offset) diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 80e89118e5..1d087b1658 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -223,7 +223,7 @@ static int find_program_segment(struct rmod_context *ctx) } if (nsegments != 1) { - ERROR("Unexepcted number of loadable segments: %d.\n", + ERROR("Unexpected number of loadable segments: %d.\n", nsegments); return -1; } From fbbef02f068b02f82662cef19d92713248eb95bd Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 29 Jan 2020 13:31:16 +0100 Subject: [PATCH 030/151] util/msrtool: Fix typos The Intel docs also call it "Scalable Bus Speed", so the typo is on us. Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f util/msrtool/*.c Change-Id: I84bdba687060e695d29420b9dd8eeb5f4ec44610 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38634 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/msrtool/intel_atom.c | 4 ++-- util/msrtool/intel_core2_later.c | 6 +++--- util/msrtool/intel_nehalem.c | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 489e0a0421..3dc2bd69f4 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -39,7 +39,7 @@ const struct msrdef intel_atom_msrs[] = { {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { { BITS_EOT } }}, {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { @@ -148,7 +148,7 @@ const struct msrdef intel_atom_msrs[] = { /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED }, diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 95e8e913e2..287e241678 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -125,8 +125,8 @@ const struct msrdef intel_core2_later_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { 63, 61, RESERVED }, { 2, 3, "Speed", "R/O", PRESENT_BIN, { { MSR1(0), "267 MHz (FSB 1067)" }, @@ -790,7 +790,7 @@ const struct msrdef intel_core2_later_msrs[] = { }}, {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 56, RESERVED }, diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index 726ad0a36c..d3cb1425ff 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -42,8 +42,8 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* FIXME: This MSR not documented for Nehalem */ - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scaleable Bus Speed", { - /* This field indicates the intended scaleable bus clock speed */ + {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + /* This field indicates the intended scalable bus clock speed */ { BITS_EOT } }}, {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { @@ -1329,7 +1329,7 @@ const struct msrdef intel_nehalem_msrs[] = { /* if CPUID.01H: ECX[15] = 1 */ {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of - * Intel 64 and IA-32 Architecures Software Developer's + * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. */ { 63, 50, RESERVED }, From 5c65d00ef2e930abe0aabe9c0035a50b1b340827 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 29 Jan 2020 13:45:45 +0100 Subject: [PATCH 031/151] util/msrtool: Fix formatting issues reported by checkpatch Change-Id: I487a9e6a6416bbe874ddadeaf464f54c02cacb0a Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38635 Reviewed-by: Paul Menzel Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- util/msrtool/intel_atom.c | 308 ++++++------- util/msrtool/intel_core1.c | 128 +++--- util/msrtool/intel_core2_early.c | 138 +++--- util/msrtool/intel_core2_later.c | 350 +++++++-------- util/msrtool/intel_nehalem.c | 652 ++++++++++++++-------------- util/msrtool/intel_pentium3.c | 102 ++--- util/msrtool/intel_pentium3_early.c | 152 +++---- util/msrtool/intel_pentium4_early.c | 360 +++++++-------- util/msrtool/intel_pentium4_later.c | 434 +++++++++--------- util/msrtool/via_c7.c | 112 ++--- 10 files changed, 1377 insertions(+), 1359 deletions(-) diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c index 3dc2bd69f4..8a73d94966 100644 --- a/util/msrtool/intel_atom.c +++ b/util/msrtool/intel_atom.c @@ -22,33 +22,33 @@ int intel_atom_probe(const struct targetdef *target, const struct cpuid_t *id) { } const struct msrdef intel_atom_msrs[] = { - {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ - Machine-Check Exception Address", { + {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", + "Pentium Processor Machine-Check Exception Address", { { BITS_EOT } }}, - {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ - Machine-Check Exception Type", { + {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", + "Pentium Processor Machine-Check Exception Type", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", { { BITS_EOT } }}, - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", { { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { 63, 19, RESERVED }, { 44, 5, "Maximum Bus Ratio", "R/O", PRESENT_DEC, { { BITVAL_EOT } @@ -59,94 +59,94 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", { { BITS_EOT } }}, #if 0 - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", { { BITS_EOT } }}, #endif - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, /* if CPUID.01H: ECX[15] = 1 */ - {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + {0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. @@ -176,46 +176,46 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { { BITS_EOT } }}, - {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { { BITS_EOT } }}, - {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { { BITS_EOT } }}, - {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { { BITS_EOT } }}, - {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, @@ -224,13 +224,13 @@ const struct msrdef intel_atom_msrs[] = { * ========================================================================== */ - {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", { /* In Intel's manual there is MAXPHYWID, * which determine index of highest bit of * APIC Base itself, so marking it as @@ -253,7 +253,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ - {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", + {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "Control features in Intel 64Processor", { { 63, 48, RESERVED }, /* if CPUID.01H: ECX[6] = 1 */ @@ -303,82 +303,82 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + {0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", { { BITS_EOT } }}, - {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + {0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", { { BITS_EOT } }}, - {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + {0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", { { BITS_EOT } }}, - {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + {0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", { { BITS_EOT } }}, - {0x44, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", { + {0x44, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_FROM_IP", "", { { BITS_EOT } }}, - {0x45, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "", { + {0x45, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_FROM_IP", "", { { BITS_EOT } }}, - {0x46, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", { + {0x46, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_FROM_IP", "", { { BITS_EOT } }}, - {0x47, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "", { + {0x47, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_FROM_IP", "", { { BITS_EOT } }}, - {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + {0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", { { BITS_EOT } }}, - {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + {0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", { { BITS_EOT } }}, - {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + {0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", { { BITS_EOT } }}, - {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + {0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", { { BITS_EOT } }}, - {0x64, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "", { + {0x64, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_TO_LIP", "", { { BITS_EOT } }}, - {0x65, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "", { + {0x65, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_TO_LIP", "", { { BITS_EOT } }}, - {0x66, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "", { + {0x66, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_TO_LIP", "", { { BITS_EOT } }}, - {0x67, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "", { + {0x67, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_TO_LIP", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "BIOS Update Signature ID (RO)", { { BITS_EOT } }}, - {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", + {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0", "Performance counter register", { { BITS_EOT } }}, - {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", + {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1", "Performance counter register", { { BITS_EOT } }}, - {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", { { BITS_EOT } }}, - {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", { { BITS_EOT } }}, - {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { { BITS_EOT } }}, - {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { { BITS_EOT } }}, - {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { 63, 61, RESERVED }, { 2, 1, "MCIP", "R/W", PRESENT_BIN, { /* When set, bit indicates that a machine check has been @@ -414,7 +414,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0", "Performance Event Select Register 0", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -474,7 +474,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1", "Performance Event Select Register 1", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -533,10 +533,10 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "Clock Modulation", { { 63, 59, RESERVED }, { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { @@ -550,15 +550,15 @@ const struct msrdef intel_atom_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "Thermal Interrupt Control", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "Thermal Monitor Status", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "Enable miscellaneous processor features", { { 63, 25, RESERVED }, /* Note: [38] bit using for whole package, @@ -632,14 +632,14 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", + {0x1c9, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "Last Branch Record Stack TOS", { /* Contains an index (bits 0-3) that points to the MSR containing * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). */ { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "Debug/Trace/Profile Resource Control", { /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ { 63, 49, RESERVED }, @@ -651,15 +651,15 @@ const struct msrdef intel_atom_msrs[] = { }}, { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Logical processor can receive and generate PMI \ - on behalf of the uncore" }, + { MSR1(1), "Logical processor can receive and generate PMI " + "on behalf of the uncore" }, { BITVAL_EOT } }}, /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Each ENABLE bit of the global counter control MSR \ - are frozen (address 0x3bf) on PMI request" }, + { MSR1(1), "Each ENABLE bit of the global counter control MSR " + "are frozen (address 0x3bf) on PMI request" }, { BITVAL_EOT } }}, /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ @@ -680,15 +680,15 @@ const struct msrdef intel_atom_msrs[] = { }}, { 8, 1, "BTINT", "R/O", PRESENT_BIN, { { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, - { MSR1(1), "An interrupt is generated by the BTS facility \ - when the BTS buffer is full" }, + { MSR1(1), "An interrupt is generated by the BTS facility " + "when the BTS buffer is full" }, { BITVAL_EOT } }}, { 7, 1, "BTS", "R/O", PRESENT_BIN, { - { MSR1(0), "Logging of BTMs (branch trace messages) \ - in BTS buffer is disabled" }, - { MSR1(1), "Logging of BTMs (branch trace messages) \ - in BTS buffer is enabled" }, + { MSR1(0), "Logging of BTMs (branch trace messages) " + "in BTS buffer is disabled" }, + { MSR1(1), "Logging of BTMs (branch trace messages) " + "in BTS buffer is enabled" }, { BITVAL_EOT } }}, { 6, 1, "TR", "R/O", PRESENT_BIN, { @@ -699,19 +699,19 @@ const struct msrdef intel_atom_msrs[] = { { 5, 4, RESERVED }, { 1, 1, "BTF", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ - branches instead of single-step on instructions" }, + { MSR1(1), "Enabled treating EFLAGS.TF as single-step on " + "branches instead of single-step on instructions" }, { BITVAL_EOT } }}, { 0, 1, "LBR", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Enabled recording a running trace of the most \ - recent branches taken by the processor in the LBR stack" }, + { MSR1(1), "Enabled recording a running trace of the most " + "recent branches taken by the processor in the LBR stack" }, { BITVAL_EOT } }}, { BITS_EOT } }}, - {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", + {0x1dd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_FROM_LIP", "Last Exception Record From Linear IP", { /* Contains a pointer to the last branch instruction * that the processor executed prior to the last exception @@ -719,7 +719,7 @@ const struct msrdef intel_atom_msrs[] = { */ { BITS_EOT } }}, - {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", + {0x1de, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_TO_LIP", "Last Exception Record To Linear IP", { /* This area contains a pointer to the target of the * last branch instruction that the processor executed @@ -728,7 +728,7 @@ const struct msrdef intel_atom_msrs[] = { */ { BITS_EOT } }}, - {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { + {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", { { 63, 5, RESERVED }, { 58, 3, "PA7", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -764,25 +764,25 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 0 */ - {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ - Performance Counter Register 0: Counts Instr_Retired.Any", { + {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function " + "Performance Counter Register 0: Counts Instr_Retired.Any", { /* Also known as MSR_PERF_FIXED_CTR0 */ { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 1 */ - {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ - Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { + {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function " + "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { /* Also known as MSR_PERF_FIXED_CTR1 */ { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 2 */ - {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ - Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { + {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function " + "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { /* Also known as MSR_PERF_FIXED_CTR2 */ { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 1*/ - {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", + {0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL", "Fixed-Function-Counter Control Register", { /* Also known as MSR_PERF_FIXED_CTR_CTRL. * Counter increments while the results of ANDing respective enable bit @@ -796,10 +796,12 @@ const struct msrdef intel_atom_msrs[] = { }}, /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -819,10 +821,12 @@ const struct msrdef intel_atom_msrs[] = { }}, /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -842,10 +846,12 @@ const struct msrdef intel_atom_msrs[] = { }}, /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { @@ -861,7 +867,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", + {0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS", "Global Performance Counter Status", { /* Also known as MSR_PERF_GLOBAL_STATUS */ /* if CPUID.0AH: EAX[7:0] > 0 */ @@ -915,7 +921,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", + {0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL", "Global Performance Counter Control", { /* Counter increments while the result of ANDing respective * enable bit in this MSR with corresponding OS or USR bits @@ -946,7 +952,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", + {0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL", "Global Performance Counter Overflow Control", { /* if CPUID.0AH: EAX[7:0] > 0 */ { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { @@ -988,7 +994,7 @@ const struct msrdef intel_atom_msrs[] = { * Software Developer's Manual, Volume 3, * "Precise Event Based Sampling (PEBS)". */ - {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { + {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", { { 63, 28, RESERVED }, { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { { MSR1(0), "Disabled" }, @@ -1034,7 +1040,7 @@ const struct msrdef intel_atom_msrs[] = { { BITS_EOT } }}, #if 0 - {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", + {0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC", "Reporting Register of Basic VMX Capabilities", { /* Additional info available at * Appendix A.1, "Basic VMX Information" */ @@ -1058,77 +1064,77 @@ const struct msrdef intel_atom_msrs[] = { }}, { BITS_EOT } }}, - {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", - "Capability Reporting Register of \ - Pin-based VM-execution Controls", { + {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS", + "Capability Reporting Register of " + "Pin-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", - "Capability Reporting Register of \ - Primary Processor-based VM-execution Controls", { + {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS", + "Capability Reporting Register of " + "Primary Processor-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", + {0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS", "Capability Reporting Register of VM-exit Controls", { /* Additional info available at Appendix A.4, * "VM-Exit Controls" */ { BITS_EOT } }}, - {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", + {0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS", "Capability Reporting Register of VM-entry Controls", { /* Additional info available at Appendix A.5, * "VM-Entry Controls" */ { BITS_EOT } }}, - {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", + {0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC", "Reporting Register of Miscellaneous VMX Capabilities", { /* Additional info available at Appendix A.6, * "Miscellaneous Data" */ { BITS_EOT } }}, - {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", + {0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0", "Capability Reporting Register of CR0 Bits Fixed to 0", { /* Additional info available at Appendix A.7, * "VMX-Fixed Bits in CR0" */ { BITS_EOT } }}, - {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", + {0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1", "Capability Reporting Register of CR0 Bits Fixed to 1", { /* Additional info available at Appendix A.7, * "VMX-Fixed Bits in CR0" */ { BITS_EOT } }}, - {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", + {0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0", "Capability Reporting Register of CR4 Bits Fixed to 0", { /* Additional info available at Appendix A.8, * "VMX-Fixed Bits in CR4" */ { BITS_EOT } }}, - {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", + {0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1", "Capability Reporting Register of CR4 Bits Fixed to 1", { /* Additional info available at Appendix A.8, * "VMX-Fixed Bits in CR4" */ { BITS_EOT } }}, - {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", + {0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM", "Capability Reporting Register of VMCS Field Enumeration", { /* Additional info available at Appendix A.9, * "VMCS Enumeration" */ { BITS_EOT } }}, - {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", - "Capability Reporting Register of Secondary \ - Processor-based VM-execution Controls", { + {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", + "Capability Reporting Register of Secondary " + "Processor-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, #endif - {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { + {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", { /* Additional info available at Section 18.10.4 of Intel 64 * and IA-32 Architectures Software Developer's Manual, * "Debug Store (DS) Mechanism". diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c index 1848698d46..fdf4005cc8 100644 --- a/util/msrtool/intel_core1.c +++ b/util/msrtool/intel_core1.c @@ -22,196 +22,196 @@ int intel_core1_probe(const struct targetdef *target, const struct cpuid_t *id) } const struct msrdef intel_core1_msrs[] = { - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", { + {0xcd, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_STS", "", { { BITS_EOT } }}, - {0xce, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_VCC", "", { + {0xce, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_VCC", "", { { BITS_EOT } }}, - {0xe2, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_CST_CONFIG_CONTROL", "", { + {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_CST_CONFIG_CONTROL", "", { { BITS_EOT } }}, - {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", { + {0xe3, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_BASE_ADDR", "", { { BITS_EOT } }}, - {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", { + {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_CAPTURE_ADDR", "", { { BITS_EOT } }}, - {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", { + {0xee, MSRTYPE_RDWR, MSR2(0, 0), "EXT_CONFIG", "", { { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { { BITS_EOT } }}, - {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", { + {0x194, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_FLEX_MAX", "", { { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", { { BITS_EOT } }}, - {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", { + {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "PIC_SENS_CFG", "", { { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { { BITS_EOT } }}, - {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", { { BITS_EOT } }}, - {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", { + {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TEMPERATURE_OFFSET", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { { BITS_EOT } }}, - {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", { { BITS_EOT } }}, - {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x15f, MSRTYPE_RDWR, MSR2(0,0), "DTS_CAL_CTRL", "", { + {0x15f, MSRTYPE_RDWR, MSR2(0, 0), "DTS_CAL_CTRL", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "GV_THERM", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "GV_THERM", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c index 7c6895c7e9..a3c7ad26cc 100644 --- a/util/msrtool/intel_core2_early.c +++ b/util/msrtool/intel_core2_early.c @@ -22,211 +22,211 @@ int intel_core2_early_probe(const struct targetdef *target, const struct cpuid_t } const struct msrdef intel_core2_early_msrs[] = { - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0x3f, MSRTYPE_RDWR, MSR2(0,0), "IA32_TEMPERATURE_OFFSET", "", { + {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TEMPERATURE_OFFSET", "", { { BITS_EOT } }}, - {0xa8, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE0", "", { + {0xa8, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE0", "", { { BITS_EOT } }}, - {0xa9, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE1", "", { + {0xa9, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE1", "", { { BITS_EOT } }}, - {0xaa, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE2", "", { + {0xaa, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE2", "", { { BITS_EOT } }}, - {0xab, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE3", "", { + {0xab, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE3", "", { { BITS_EOT } }}, - {0xac, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE4", "", { + {0xac, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE4", "", { { BITS_EOT } }}, - {0xad, MSRTYPE_RDWR, MSR2(0,0), "EMTTM_CR_TABLE5", "", { + {0xad, MSRTYPE_RDWR, MSR2(0, 0), "EMTTM_CR_TABLE5", "", { { BITS_EOT } }}, - {0xcd, MSRTYPE_RDWR, MSR2(0,0), "FSB_CLOCK_STS", "", { + {0xcd, MSRTYPE_RDWR, MSR2(0, 0), "FSB_CLOCK_STS", "", { { BITS_EOT } }}, - {0xe2, MSRTYPE_RDWR, MSR2(0,0), "PMG_CST_CONFIG_CONTROL", "", { + {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "PMG_CST_CONFIG_CONTROL", "", { { BITS_EOT } }}, - {0xe3, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_BASE_ADDR", "", { + {0xe3, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_BASE_ADDR", "", { { BITS_EOT } }}, - {0xe4, MSRTYPE_RDWR, MSR2(0,0), "PMG_IO_CAPTURE_ADDR", "", { + {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "PMG_IO_CAPTURE_ADDR", "", { { BITS_EOT } }}, - {0xee, MSRTYPE_RDWR, MSR2(0,0), "EXT_CONFIG", "", { + {0xee, MSRTYPE_RDWR, MSR2(0, 0), "EXT_CONFIG", "", { { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { { BITS_EOT } }}, - {0x194, MSRTYPE_RDWR, MSR2(0,0), "CLOCK_FLEX_MAX", "", { + {0x194, MSRTYPE_RDWR, MSR2(0, 0), "CLOCK_FLEX_MAX", "", { { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", { { BITS_EOT } }}, - {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "PIC_SENS_CFG", "", { + {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "PIC_SENS_CFG", "", { { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { { BITS_EOT } }}, - {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { { BITS_EOT } }}, - {0xe1, MSRTYPE_RDWR, MSR2(0,0), "SMM_CST_MISC_INFO", "", { + {0xe1, MSRTYPE_RDWR, MSR2(0, 0), "SMM_CST_MISC_INFO", "", { { BITS_EOT } }}, - {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", { { BITS_EOT } }}, - {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_CTL", "", { + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_CTL", "", { { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c index 287e241678..fda85327bd 100644 --- a/util/msrtool/intel_core2_later.c +++ b/util/msrtool/intel_core2_later.c @@ -22,7 +22,7 @@ int intel_core2_later_probe(const struct targetdef *target, const struct cpuid_t } const struct msrdef intel_core2_later_msrs[] = { - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", { /* The OS can use this MSR to determine "slot" information for the * processor and the proper microcode update to load. */ @@ -46,7 +46,7 @@ const struct msrdef intel_core2_later_msrs[] = { { 7, 8, RESERVED }, { BITS_EOT } }}, - { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", + { 0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBL_CR_POWERON Register", "Processor Hard Power-On Configuration", { { 63, 41, RESERVED }, { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, { @@ -125,7 +125,7 @@ const struct msrdef intel_core2_later_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", { /* This field indicates the intended scalable bus clock speed */ { 63, 61, RESERVED }, { 2, 3, "Speed", "R/O", PRESENT_BIN, { @@ -140,7 +140,7 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", { { 63, 40, RESERVED }, { 23, 1, "L2 Present", "R/O", PRESENT_BIN, { { MSR1(0), "L2 Present" }, @@ -164,27 +164,27 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { BITS_EOT } }}, // Per core msrs - {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ - Machine-Check Exception Address", { + {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", + "Pentium Processor Machine-Check Exception Address", { { BITS_EOT } }}, - {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ - Machine-Check Exception Type", { + {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", + "Pentium Processor Machine-Check Exception Type", { { BITS_EOT } }}, - {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", { /* In Intel's manual there is MAXPHYWID, * which determine index of highest bit of * APIC Base itself, so marking it as @@ -202,7 +202,7 @@ const struct msrdef intel_core2_later_msrs[] = { { 7, 8, RESERVED }, { BITS_EOT } }}, - {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", + {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "Control features in Intel 64Processor", { { 63, 48, RESERVED }, /* if CPUID.01H: ECX[6] = 1 */ @@ -257,57 +257,57 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + {0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", { { BITS_EOT } }}, - {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + {0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", { { BITS_EOT } }}, - {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + {0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", { { BITS_EOT } }}, - {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + {0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", { { BITS_EOT } }}, - {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + {0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", { { BITS_EOT } }}, - {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + {0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", { { BITS_EOT } }}, - {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + {0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", { { BITS_EOT } }}, - {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + {0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", { { BITS_EOT } }}, - {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", + {0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG", "BIOS Update Trigger Register (W)", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "BIOS Update Signature ID (RO)", { { BITS_EOT } }}, - {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { + {0xa0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_BASE", "", { { BITS_EOT } }}, - {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { + {0xa1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_MASK", "", { { BITS_EOT } }}, - {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", { + {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0", "", { { BITS_EOT } }}, - {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", { + {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1", "", { { BITS_EOT } }}, - {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", { { BITS_EOT } }}, - {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { 63, 52, RESERVED }, { 11, 1, "SMRR Capability Using MSR 0xa0 and 0xa1", "R/O", PRESENT_BIN, { { BITVAL_EOT } @@ -315,19 +315,19 @@ const struct msrdef intel_core2_later_msrs[] = { { 10, 11, RESERVED }, { BITS_EOT } }}, - {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { { BITS_EOT } }}, - {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { { BITS_EOT } }}, - {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { 63, 61, RESERVED }, { 2, 1, "MCIP", "R/W", PRESENT_BIN, { /* When set, bit indicates that a machine check has been @@ -363,7 +363,7 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0", "Performance Event Select Register 0", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -423,7 +423,7 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1", "Performance Event Select Register 1", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -482,13 +482,13 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "Clock Modulation", { { 63, 59, RESERVED }, { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { @@ -502,18 +502,18 @@ const struct msrdef intel_core2_later_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "Thermal Interrupt Control", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "Thermal Monitor Status", { { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "Enable miscellaneous processor features", { { 63, 24, RESERVED }, { 39, 1, "IP Prefetcher Disable", "R/W", PRESENT_BIN, { @@ -562,18 +562,18 @@ const struct msrdef intel_core2_later_msrs[] = { { 21, 1, RESERVED }, { 20, 1, "Enhanced Intel SpeedStep Select Lock", "R/W", PRESENT_BIN, { - { MSR1(0), "Enhanced Intel SpeedStep Select\ - and Enable bits are writeable" }, - { MSR1(1), "Enhanced Intel SpeedStep Select\ - and Enable bits are locked and R/O" }, + { MSR1(0), "Enhanced Intel SpeedStep Select " + "and Enable bits are writeable" }, + { MSR1(1), "Enhanced Intel SpeedStep Select " + "and Enable bits are locked and R/O" }, { BITVAL_EOT } }}, { 19, 1, "Adjacent Cache Line Prefetch Disable", "R/W", PRESENT_BIN, { - { MSR1(0), "Fetching cache lines that comprise a cache\ - line pair (128 bytes)" }, - { MSR1(1), "Fetching cache line that contains data\ - currently required by the processor" }, + { MSR1(0), "Fetching cache lines that comprise a cache " + "line pair (128 bytes)" }, + { MSR1(1), "Fetching cache line that contains data " + "currently required by the processor" }, { BITVAL_EOT } }}, { 18, 1, "Enable Monitor FSM", "R/W", PRESENT_BIN, { @@ -603,8 +603,8 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { 10, 1, "FERR# Multiplexing Enable", "R/W", PRESENT_BIN, { { MSR1(0), "FERR# signaling compatible behaviour" }, - { MSR1(1), "FERR# asserted by the processor to indicate\ - a pending break event within the processor" }, + { MSR1(1), "FERR# asserted by the processor to indicate " + "a pending break event within the processor" }, { BITVAL_EOT } }}, { 9, 1, "Hardware Prefetcher Disable", "R/W", PRESENT_BIN, { @@ -627,100 +627,100 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { + {0x1c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", { { BITS_EOT } }}, - {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", { { BITS_EOT } }}, - {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { + {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", { { 63, 5, RESERVED }, { 58, 3, "PA7", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -755,7 +755,7 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "Default Memory Types", { { 63, 52, RESERVED }, { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, { @@ -771,24 +771,24 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 0 */ - {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ - Performance Counter Register 0: Counts Instr_Retired.Any", { + {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function " + "Performance Counter Register 0: Counts Instr_Retired.Any", { /* Also known as MSR_PERF_FIXED_CTR0 */ { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 1 */ - {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ - Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { + {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function " + "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { /* Also known as MSR_PERF_FIXED_CTR1 */ { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 2 */ - {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ - Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { + {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function " + "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { /* Also known as MSR_PERF_FIXED_CTR2 */ { BITS_EOT } }}, - {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + {0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. @@ -806,7 +806,7 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 1*/ - {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", + {0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL", "Fixed-Function-Counter Control Register", { /* Also known as MSR_PERF_FIXED_CTR_CTRL. * Counter increments while the results of ANDing respective enable bit @@ -820,10 +820,12 @@ const struct msrdef intel_core2_later_msrs[] = { }}, /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -843,10 +845,12 @@ const struct msrdef intel_core2_later_msrs[] = { }}, /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -866,10 +870,12 @@ const struct msrdef intel_core2_later_msrs[] = { }}, /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { @@ -885,7 +891,7 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", + {0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS", "Global Performance Counter Status", { /* Also known as MSR_PERF_GLOBAL_STATUS */ /* if CPUID.0AH: EAX[7:0] > 0 */ @@ -939,7 +945,7 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", + {0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL", "Global Performance Counter Control", { /* Counter increments while the result of ANDing respective * enable bit in this MSR with corresponding OS or USR bits @@ -970,7 +976,7 @@ const struct msrdef intel_core2_later_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", + {0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL", "Global Performance Counter Overflow Control", { /* if CPUID.0AH: EAX[7:0] > 0 */ { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { @@ -1012,7 +1018,7 @@ const struct msrdef intel_core2_later_msrs[] = { * Software Developer's Manual, Volume 3, * "Precise Event Based Sampling (PEBS)". */ - {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { + {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", { { 63, 28, RESERVED }, { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { { MSR1(0), "Disabled" }, @@ -1057,85 +1063,85 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + {0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", { { BITS_EOT } }}, - {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { { BITS_EOT } }}, - {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { { BITS_EOT } }}, - {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { { BITS_EOT } }}, - {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + {0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", { { BITS_EOT } }}, - {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { { BITS_EOT } }}, - {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { { BITS_EOT } }}, - {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { { BITS_EOT } }}, - {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, - {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", { { BITS_EOT } }}, - {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { + {0x414, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL", "", { { BITS_EOT } }}, - {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { + {0x415, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_STATUS", "", { { BITS_EOT } }}, - {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { + {0x416, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_ADDR", "", { { BITS_EOT } }}, - {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { + {0x417, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_MISC", "", { { BITS_EOT } }}, - {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { + {0x418, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL", "", { { BITS_EOT } }}, - {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { + {0x419, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_STATUS", "", { { BITS_EOT } }}, - {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", + {0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC", "Reporting Register of Basic VMX Capabilities", { /* Additional info available at * Appendix A.1, "Basic VMX Information" */ @@ -1159,76 +1165,76 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", - "Capability Reporting Register of \ - Pin-based VM-execution Controls", { + {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS", + "Capability Reporting Register of " + "Pin-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", - "Capability Reporting Register of \ - Primary Processor-based VM-execution Controls", { + {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS", + "Capability Reporting Register of " + "Primary Processor-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", + {0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS", "Capability Reporting Register of VM-exit Controls", { /* Additional info available at Appendix A.4, * "VM-Exit Controls" */ { BITS_EOT } }}, - {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", + {0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS", "Capability Reporting Register of VM-entry Controls", { /* Additional info available at Appendix A.5, * "VM-Entry Controls" */ { BITS_EOT } }}, - {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", + {0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC", "Reporting Register of Miscellaneous VMX Capabilities", { /* Additional info available at Appendix A.6, * "Miscellaneous Data" */ { BITS_EOT } }}, - {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", + {0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0", "Capability Reporting Register of CR0 Bits Fixed to 0", { /* Additional info available at Appendix A.7, * "VMX-Fixed Bits in CR0" */ { BITS_EOT } }}, - {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", + {0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1", "Capability Reporting Register of CR0 Bits Fixed to 1", { /* Additional info available at Appendix A.7, * "VMX-Fixed Bits in CR0" */ { BITS_EOT } }}, - {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", + {0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0", "Capability Reporting Register of CR4 Bits Fixed to 0", { /* Additional info available at Appendix A.8, * "VMX-Fixed Bits in CR4" */ { BITS_EOT } }}, - {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", + {0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1", "Capability Reporting Register of CR4 Bits Fixed to 1", { /* Additional info available at Appendix A.8, * "VMX-Fixed Bits in CR4" */ { BITS_EOT } }}, - {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", + {0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM", "Capability Reporting Register of VMCS Field Enumeration", { /* Additional info available at Appendix A.9, * "VMCS Enumeration" */ { BITS_EOT } }}, - {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", - "Capability Reporting Register of Secondary \ - Processor-based VM-execution Controls", { + {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", + "Capability Reporting Register of Secondary " + "Processor-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { + {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", { /* Additional info available at Section 18.10.4 of Intel 64 * and IA-32 Architectures Software Developer's Manual, * "Debug Store (DS) Mechanism". @@ -1240,52 +1246,52 @@ const struct msrdef intel_core2_later_msrs[] = { }}, { BITS_EOT } }}, - {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { + {0x107cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL0", "", { { BITS_EOT } }}, - {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { + {0x107cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL1", "", { { BITS_EOT } }}, - {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { + {0x107ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL2", "", { { BITS_EOT } }}, - {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { + {0x107cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL3", "", { { BITS_EOT } }}, - {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { + {0x107d0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL4", "", { { BITS_EOT } }}, - {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { + {0x107d1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL5", "", { { BITS_EOT } }}, - {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { + {0x107d2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL6", "", { { BITS_EOT } }}, - {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { + {0x107d3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL7", "", { { BITS_EOT } }}, - {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { + {0x107d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_GL_CTL", "", { { BITS_EOT } }}, - {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", { + {0xc0000080, MSRTYPE_RDWR, MSR2(0, 0), "IA32_EFER", "", { { BITS_EOT } }}, - {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", { + {0xc0000081, MSRTYPE_RDWR, MSR2(0, 0), "IA32_STAR", "", { { BITS_EOT } }}, - {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", { + {0xc0000082, MSRTYPE_RDWR, MSR2(0, 0), "IA32_LSTAR", "", { { BITS_EOT } }}, - {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", { + {0xc0000084, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FMASK", "", { { BITS_EOT } }}, - {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", { + {0xc0000100, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FS_BASE", "", { { BITS_EOT } }}, - {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", { + {0xc0000101, MSRTYPE_RDWR, MSR2(0, 0), "IA32_GS_BASE", "", { { BITS_EOT } }}, - {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", { + {0xc0000102, MSRTYPE_RDWR, MSR2(0, 0), "IA32_KERNEL_GS_BASE", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c index d3cb1425ff..c5c30826f1 100644 --- a/util/msrtool/intel_nehalem.c +++ b/util/msrtool/intel_nehalem.c @@ -29,7 +29,7 @@ int intel_nehalem_probe(const struct targetdef *target, const struct cpuid_t *id } const struct msrdef intel_nehalem_msrs[] = { - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", { { 63, 11, RESERVED }, { 52, 3, RESERVED }, @@ -42,11 +42,11 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* FIXME: This MSR not documented for Nehalem */ - {0xcd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_FSB_FREQ", "Scalable Bus Speed", { + {0xcd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_FSB_FREQ", "Scalable Bus Speed", { /* This field indicates the intended scalable bus clock speed */ { BITS_EOT } }}, - {0xce, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PLATFORM_INFO", "", { + {0xce, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PLATFORM_INFO", "", { { 63, 16, RESERVED }, { 47, 8, "Maximum Efficiency Ratio", "R/O", PRESENT_DEC, { { BITVAL_EOT } @@ -72,7 +72,7 @@ const struct msrdef intel_nehalem_msrs[] = { { 7, 8, RESERVED }, { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BBL_CR_CTL3", "", { { BITS_EOT } }}, /* FIXME: There is already two 0x1ad MSRs for Nehalem in the @@ -81,7 +81,7 @@ const struct msrdef intel_nehalem_msrs[] = { * we can conclude, that it was just typo, and this register * have address 0x1ac. */ - {0x1ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_TURBO_POWER_CURRENT_LIMIT", "", { + {0x1ac, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TURBO_POWER_CURRENT_LIMIT", "", { { 63, 32, RESERVED }, { 31, 1, "TDC Limit Override Enable", "R/W", PRESENT_BIN, { { MSR1(0), "TDC Limit Override is not active" }, @@ -103,7 +103,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x1ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_TURBO_RATIO_LIMIT", + {0x1ad, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TURBO_RATIO_LIMIT", "Maximum Ratio Limit of Turbo Mode", { // "RO" if MSR_PLATFORM_INFO.[28] = 0 // "RW" if MSR_PLATFORM_INFO.[23] = 1 @@ -126,7 +126,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x280, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL2", "", { + {0x280, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -137,7 +137,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x281, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL2", "", { + {0x281, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -148,7 +148,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x286, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL2", "", { + {0x286, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -159,7 +159,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x287, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_CTL2", "", { + {0x287, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -170,7 +170,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x288, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_CTL2", "", { + {0x288, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -181,7 +181,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x3f8, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C3_RESIDENCY", "", { + {0x3f8, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PKG_C3_RESIDENCY", "", { { 63, 64, "Package C3 Residency Counter", "R/O", PRESENT_DEC, { /* Value since last reset that this package is in C3 states. * Count at the same frequency as the TSC. @@ -190,46 +190,46 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x3f9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C6_RESIDENCY", "", { + {0x3f9, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PKG_C6_RESIDENCY", "", { { BITS_EOT } }}, - {0x3fa, MSRTYPE_RDONLY, MSR2(0,0), "MSR_PKG_C7_RESIDENCY", "", { + {0x3fa, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_PKG_C7_RESIDENCY", "", { { BITS_EOT } }}, - {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", { + {0x418, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_CTL", "", { { BITS_EOT } }}, - {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", { + {0x419, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_STATUS", "", { { BITS_EOT } }}, - {0x41a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_ADDR", "", { + {0x41a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_ADDR", "", { { BITS_EOT } }}, - {0x41b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_MISC", "", { + {0x41b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC6_MISC", "", { { BITS_EOT } }}, - {0x41c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_CTL", "", { + {0x41c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_CTL", "", { { BITS_EOT } }}, - {0x41d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_STATUS", "", { + {0x41d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_STATUS", "", { { BITS_EOT } }}, - {0x41e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_ADDR", "", { + {0x41e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_ADDR", "", { { BITS_EOT } }}, - {0x41f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC7_MISC", "", { + {0x41f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC7_MISC", "", { { BITS_EOT } }}, - {0x420, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_CTL", "", { + {0x420, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_CTL", "", { { BITS_EOT } }}, - {0x421, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_STATUS", "", { + {0x421, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_STATUS", "", { { BITS_EOT } }}, - {0x422, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_ADDR", "", { + {0x422, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_ADDR", "", { { BITS_EOT } }}, - {0x423, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC8_MISC", "", { + {0x423, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC8_MISC", "", { { BITS_EOT } }}, @@ -238,21 +238,21 @@ const struct msrdef intel_nehalem_msrs[] = { * ========================================================================== */ - {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "Pentium Processor\ - Machine-Check Exception Address", { + {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", + "Pentium Processor Machine-Check Exception Address", { { BITS_EOT } }}, - {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "Pentium Processor\ - Machine-Check Exception Type", { + {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", + "Pentium Processor Machine-Check Exception Type", { { BITS_EOT } }}, - {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", { + {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_SIZE", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "TSC", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STEP_COUNTER", "TSC", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "APIC BASE", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "APIC BASE", { /* In Intel's manual there is MAXPHYWID, * which determine index of highest bit of * APIC Base itself, so marking it as @@ -274,7 +274,7 @@ const struct msrdef intel_nehalem_msrs[] = { { 7, 8, RESERVED }, { BITS_EOT } }}, - {0x34, MSRTYPE_RDONLY, MSR2(0,0), "MSR_SMI_COUNT", "SMI Counter register", { + {0x34, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_SMI_COUNT", "SMI Counter register", { { 63, 32, RESERVED }, { 31, 32, "SMI Count", "R/O", PRESENT_HEX, { { BITVAL_EOT } @@ -282,7 +282,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.01H: ECX[bit 5 or bit 6] = 1 */ - {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", + {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "Control features in Intel 64Processor", { { 63, 48, RESERVED }, /* if CPUID.01H: ECX[6] = 1 */ @@ -332,61 +332,61 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + {0x40, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", { { BITS_EOT } }}, - {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", { + {0x41, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "", { { BITS_EOT } }}, - {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + {0x42, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", { { BITS_EOT } }}, - {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", { + {0x43, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "", { { BITS_EOT } }}, - {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", { + {0x60, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "", { { BITS_EOT } }}, - {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", { + {0x61, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "", { { BITS_EOT } }}, - {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", { + {0x62, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "", { { BITS_EOT } }}, - {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", { + {0x63, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "", { { BITS_EOT } }}, - {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", + {0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG", "BIOS Update Trigger Register (W)", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "BIOS Update Signature ID (RO)", { { BITS_EOT } }}, - {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", { + {0xa0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_BASE", "", { { BITS_EOT } }}, - {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", { + {0xa1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SMRR_PHYS_MASK", "", { { BITS_EOT } }}, - {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", + {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC0", "Performance counter register", { { BITS_EOT } }}, - {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", + {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC1", "Performance counter register", { { BITS_EOT } }}, - {0xc3, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC2", + {0xc3, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC2", "Performance counter register", { { BITS_EOT } }}, - {0xc4, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC3", + {0xc4, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PMC3", "Performance counter register", { { BITS_EOT } }}, - {0xe2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PKG_CST_CONFIG_CONTROL", + {0xe2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PKG_CST_CONFIG_CONTROL", "C-State Configuration Control", { { 63, 37, RESERVED }, { 26, 1, "C1 state auto demotion", "R/W", PRESENT_DEC, { @@ -400,26 +400,26 @@ const struct msrdef intel_nehalem_msrs[] = { { BITVAL_EOT } }}, { 24, 1, "Interrupt filtering enabled/disabled", "R/W", PRESENT_DEC, { - { MSR1(0), "All CPU cores in deep C-State will wake for an \ - event message" }, - { MSR1(1), "CPU in deep C-State will wake only when the event \ - message is destined for that core" }, + { MSR1(0), "All CPU cores in deep C-State will wake for an " + "event message" }, + { MSR1(1), "CPU in deep C-State will wake only when the event " + "message is destined for that core" }, { BITVAL_EOT } }}, { 23, 8, RESERVED }, { 15, 1, "CFG Lock", "R/WO", PRESENT_DEC, { - { MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ - are writeable" }, - { MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) \ - are locked until reset" }, + { MSR1(0), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) " + "are writeable" }, + { MSR1(1), "[15:0] bits of MSR_PKG_CST_CONFIG_CONTROL(0xe2) " + "are locked until reset" }, { BITVAL_EOT } }}, { 14, 4, RESERVED }, { 10, 1, "I/O MWAIT Redirection", "R/W", PRESENT_DEC, { { MSR1(0), "I/O MWAIT Redirection disabled" }, - { MSR1(1), "CPU will map IO_read instructions sent to \ - IO register specified by MSR_PMG_IO_CAPTURE_BASE \ - to MWAIT instructions" }, + { MSR1(1), "CPU will map IO_read instructions sent to " + "IO register specified by MSR_PMG_IO_CAPTURE_BASE " + "to MWAIT instructions" }, { BITVAL_EOT } }}, { 9, 7, RESERVED }, @@ -443,7 +443,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0xe4, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMG_IO_CAPTURE_BASE", + {0xe4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMG_IO_CAPTURE_BASE", "Power Management IO Redirection in C-state", { { 63, 45, RESERVED }, { 18, 3, "C-state Range", "R/W", PRESENT_BIN, { @@ -467,28 +467,28 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", { + {0xe7, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MPERF", "", { { BITS_EOT } }}, - {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", { + {0xe8, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APERF", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { { BITS_EOT } }}, - {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { { BITS_EOT } }}, - {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { 63, 61, RESERVED }, { 2, 1, "MCIP", "R/W", PRESENT_BIN, { /* When set, bit indicates that a machine check has been @@ -524,7 +524,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0", "Performance Event Select Register 0", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -584,7 +584,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1", "Performance Event Select Register 1", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -644,7 +644,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x188, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL2", + {0x188, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL2", "Performance Event Select Register 2", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -704,7 +704,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x189, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL3", + {0x189, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL3", "Performance Event Select Register 3", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -763,17 +763,17 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { 63, 48, RESERVED }, { 15, 16, "Current Performance State Value", "R/O", PRESENT_HEX, { { BITVAL_EOT } }}, { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "Clock Modulation", { { 63, 59, RESERVED }, { 4, 1, "On demand Clock Modulation", "R/W", PRESENT_BIN, { @@ -787,18 +787,18 @@ const struct msrdef intel_nehalem_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "Thermal Interrupt Control", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "Thermal Monitor Status", { { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "Enable miscellaneous processor features", { { 63, 25, RESERVED }, /* Note: [38] bit using for whole package, @@ -872,7 +872,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x1a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TEMPERATURE_TARGET", "", { + {0x1a2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TEMPERATURE_TARGET", "", { { 63, 40, RESERVED }, { 23, 8, "Temperature Target", "R", PRESENT_DEC, { /* The minimum temperature at which PROCHOT# will be @@ -883,32 +883,32 @@ const struct msrdef intel_nehalem_msrs[] = { { 15, 16, RESERVED }, { BITS_EOT } }}, - {0x1a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_OFFCORE_RSP_O", + {0x1a6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_OFFCORE_RSP_O", "Offcore Response Event Select Register", { { BITS_EOT } }}, - {0x1aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MISC_PWR_MGMT", "", { + {0x1aa, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MISC_PWR_MGMT", "", { { 63, 62, RESERVED }, { 1, 1, "Energy/Performance Bias Enable", "R/W", PRESENT_BIN, { /* This bit status is also reflected * by CPUID.(EAX=06h):ECX[3] */ - { MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible \ - for Ring 0 software" }, - { MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible \ - by Ring 0 software" }, + { MSR1(0), "IA32_ENERGY_PERF_BIAS (0x1b0) is invisible " + "for Ring 0 software" }, + { MSR1(1), "IA32_ENERGY_PERF_BIAS (0x1b0) accessible " + "by Ring 0 software" }, { BITVAL_EOT } }}, { 0, 1, "EIST Hardware Coordination Disable", "R/W", PRESENT_BIN, { - { MSR1(0), "Hardware Coordination of EIST request \ - from processor cores is enabled" }, - { MSR1(1), "Hardware Coordination of EIST request \ - from processor cores is disabled" }, + { MSR1(0), "Hardware Coordination of EIST request " + "from processor cores is enabled" }, + { MSR1(1), "Hardware Coordination of EIST request " + "from processor cores is disabled" }, { BITVAL_EOT } }}, { BITS_EOT } }}, - {0x1c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LBR_SELECT", + {0x1c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LBR_SELECT", "Last Branch Record Filtering Select Register", { /* "Nehalem support filtering of LBR based on combination of CPL * and branch type conditions. When LBR filtering is enabled, @@ -920,14 +920,14 @@ const struct msrdef intel_nehalem_msrs[] = { */ { BITS_EOT } }}, - {0x1c9, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LASTBRANCH_TOS", + {0x1c9, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "Last Branch Record Stack TOS", { /* Contains an index (bits 0-3) that points to the MSR containing * the most recent branch record. See also MSR_LASTBRANCH_0_FROM_IP (0x680). */ { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "Debug/Trace/Profile Resource Control", { /* (MSR_DEBUGCTTLA, MSR_DEBUGCTLB) */ { 63, 49, RESERVED }, @@ -939,15 +939,15 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { 13, 1, "ENABLE_UNCORE_PMI", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Logical processor can receive and generate PMI \ - on behalf of the uncore" }, + { MSR1(1), "Logical processor can receive and generate PMI " + "on behalf of the uncore" }, { BITVAL_EOT } }}, /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ { 12, 1, "FREEZE_PERFMON_ON_PMI", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Each ENABLE bit of the global counter control MSR \ - are frozen (address 0x3bf) on PMI request" }, + { MSR1(1), "Each ENABLE bit of the global counter control MSR " + "are frozen (address 0x3bf) on PMI request" }, { BITVAL_EOT } }}, /* Only if CPUID.01H: ECX[15] = 1 and CPUID.0AH: EAX[7:0]>1 */ @@ -968,15 +968,15 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { 8, 1, "BTINT", "R/O", PRESENT_BIN, { { MSR1(0), "BTMs are logged in a BTS buffer in circular fashion" }, - { MSR1(1), "An interrupt is generated by the BTS facility \ - when the BTS buffer is full" }, + { MSR1(1), "An interrupt is generated by the BTS facility " + "when the BTS buffer is full" }, { BITVAL_EOT } }}, { 7, 1, "BTS", "R/O", PRESENT_BIN, { - { MSR1(0), "Logging of BTMs (branch trace messages) \ - in BTS buffer is disabled" }, - { MSR1(1), "Logging of BTMs (branch trace messages) \ - in BTS buffer is enabled" }, + { MSR1(0), "Logging of BTMs (branch trace messages) " + "in BTS buffer is disabled" }, + { MSR1(1), "Logging of BTMs (branch trace messages) " + "in BTS buffer is enabled" }, { BITVAL_EOT } }}, { 6, 1, "TR", "R/O", PRESENT_BIN, { @@ -987,19 +987,19 @@ const struct msrdef intel_nehalem_msrs[] = { { 5, 4, RESERVED }, { 1, 1, "BTF", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Enabled treating EFLAGS.TF as single-step on \ - branches instead of single-step on instructions" }, + { MSR1(1), "Enabled treating EFLAGS.TF as single-step on " + "branches instead of single-step on instructions" }, { BITVAL_EOT } }}, { 0, 1, "LBR", "R/O", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "Enabled recording a running trace of the most \ - recent branches taken by the processor in the LBR stack" }, + { MSR1(1), "Enabled recording a running trace of the most " + "recent branches taken by the processor in the LBR stack" }, { BITVAL_EOT } }}, { BITS_EOT } }}, - {0x1dd, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_FROM_LIP", + {0x1dd, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_FROM_LIP", "Last Exception Record From Linear IP", { /* Contains a pointer to the last branch instruction * that the processor executed prior to the last exception @@ -1007,7 +1007,7 @@ const struct msrdef intel_nehalem_msrs[] = { */ { BITS_EOT } }}, - {0x1de, MSRTYPE_RDONLY, MSR2(0,0), "MSR_LER_TO_LIP", + {0x1de, MSRTYPE_RDONLY, MSR2(0, 0), "MSR_LER_TO_LIP", "Last Exception Record To Linear IP", { /* This area contains a pointer to the target of the * last branch instruction that the processor executed @@ -1016,7 +1016,7 @@ const struct msrdef intel_nehalem_msrs[] = { */ { BITS_EOT } }}, - {0x1f2, MSRTYPE_RDONLY, MSR2(0,0), "IA32_SMRR_PHYS_BASE", + {0x1f2, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_SMRR_PHYS_BASE", "SMRR Base Address", { /* Base address of SMM memory range. * Writeable only in SMM, so marking it as read-only */ @@ -1030,7 +1030,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x1f3, MSRTYPE_RDONLY, MSR2(0,0), "IA32_SMRR_PHYS_MASK", + {0x1f3, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_SMRR_PHYS_MASK", "SMRR Range Mask", { /* Range Mask of SMM memory range. * Writeable only in SMM, so marking it as read-only */ @@ -1046,11 +1046,11 @@ const struct msrdef intel_nehalem_msrs[] = { { 10, 11, RESERVED }, { BITS_EOT } }}, - {0x1f8, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PLATFORM_DCA_CAP", + {0x1f8, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PLATFORM_DCA_CAP", "DCA Capability", { { BITS_EOT } }}, - {0x1f9, MSRTYPE_RDONLY, MSR2(0,0), "IA32_CPU_DCA_CAP", + {0x1f9, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_CPU_DCA_CAP", "Support og Prefetch-Hint type", { /* If set, CPU supports Prefetch-Hint type. * TODO: As it is undocumented, which bit (or bits) @@ -1059,7 +1059,7 @@ const struct msrdef intel_nehalem_msrs[] = { */ { BITS_EOT } }}, - {0x1fa, MSRTYPE_RDWR, MSR2(0,0), "IA32_DCA_0_CAP", + {0x1fa, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DCA_0_CAP", "DCA type 0 Status and Control register", { /* This register defined as introduced only * in 06_2EH Nehalem model (latest), so be careful! @@ -1103,118 +1103,118 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x1fc, MSRTYPE_RDWR, MSR2(0,0), "MSR_POWER_CTL", + {0x1fc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_POWER_CTL", "Power Control Register", { { 63, 62, RESERVED }, /* Whole package bit */ { 1, 1, "C1E Enable", "R/W", PRESENT_BIN, { { MSR1(0), "Nothing" }, - { MSR1(1), "CPU switch to the Minimum Enhanced Intel \ - SpeedStep Technology operating point when all \ - execution cores enter MWAIT (C1)" }, + { MSR1(1), "CPU switch to the Minimum Enhanced Intel " + "SpeedStep Technology operating point when all " + "execution cores enter MWAIT (C1)" }, { BITVAL_EOT } }}, { 0, 1, RESERVED }, { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK7", "", { { BITS_EOT } }}, /* if IA32_MTRR_CAP[7:0] > 8 */ - {0x210, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE8", "", { + {0x210, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE8", "", { { BITS_EOT } }}, /* if IA32_MTRR_CAP[7:0] > 8 */ - {0x211, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK8", "", { + {0x211, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK8", "", { { BITS_EOT } }}, /* if IA32_MTRR_CAP[7:0] > 9 */ - {0x212, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE9", "", { + {0x212, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_BASE9", "", { { BITS_EOT } }}, /* if IA32_MTRR_CAP[7:0] > 9 */ - {0x213, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK9", "", { + {0x213, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYS_MASK9", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "IA32_PAT", { + {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "IA32_PAT", { { 63, 5, RESERVED }, { 58, 3, "PA7", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -1249,7 +1249,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x282, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL2", "", { + {0x282, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -1260,7 +1260,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x283, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL2", "", { + {0x283, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -1271,7 +1271,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x284, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL2", "", { + {0x284, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -1282,7 +1282,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x285, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL2", "", { + {0x285, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL2", "", { { 63, 33, RESERVED }, { 30, 1, "CMCI_EN", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -1293,7 +1293,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "Default Memory Types", { { 63, 52, RESERVED }, { 11, 1, "MTRR Enable", "R/W", PRESENT_BIN, { @@ -1309,25 +1309,25 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 0 */ - {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "Fixed-Function \ - Performance Counter Register 0: Counts Instr_Retired.Any", { + {0x309, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR0", "Fixed-Function " + "Performance Counter Register 0: Counts Instr_Retired.Any", { /* Also known as MSR_PERF_FIXED_CTR0 */ { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 1 */ - {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "Fixed-Function \ - Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { + {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR1", "Fixed-Function " + "Performance Counter Register 1: Counts CPU_CLK_Unhalted.Core ", { /* Also known as MSR_PERF_FIXED_CTR1 */ { BITS_EOT } }}, /* if CPUID.0AH: EDX[4:0] > 2 */ - {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "Fixed-Function \ - Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { + {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR2", "Fixed-Function " + "Performance Counter Register 2: Counts CPU_CLK_Unhalted.Ref", { /* Also known as MSR_PERF_FIXED_CTR2 */ { BITS_EOT } }}, /* if CPUID.01H: ECX[15] = 1 */ - {0x345, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", { + {0x345, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_CAPABILITIES", "", { /* Additional info available at Section 17.4.1 of * Intel 64 and IA-32 Architectures Software Developer's * Manual, Volume 3. @@ -1358,7 +1358,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 1*/ - {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", + {0x38d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FIXED_CTR_CTRL", "Fixed-Function-Counter Control Register", { /* Also known as MSR_PERF_FIXED_CTR_CTRL. * Counter increments while the results of ANDing respective enable bit @@ -1372,10 +1372,12 @@ const struct msrdef intel_nehalem_msrs[] = { }}, /* if CPUID.0AH EAX[7:0] > 2 */ { 10, 1, "AnyThread 2", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 9, 1, "EN2_Usr", "R/W", PRESENT_BIN, { @@ -1395,10 +1397,12 @@ const struct msrdef intel_nehalem_msrs[] = { }}, /* if CPUID.0AH: EAX[7:0] > 2 */ { 6, 1, "AnyThread 1", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 5, 1, "EN1_Usr", "R/W", PRESENT_BIN, { @@ -1418,10 +1422,12 @@ const struct msrdef intel_nehalem_msrs[] = { }}, /* if CPUID.0AH: EAX[7:0] > 2 */ { 2, 1, "AnyThread 0", "R/W", PRESENT_BIN, { - { MSR1(0), "Counter only increments the associated event \ - conditions occurring in the logical processor which programmed the MSR" }, - { MSR1(1), "Counting the associated event conditions \ - occurring across all logical processors sharing a processor core" }, + { MSR1(0), "Counter only increments the associated event " + "conditions occurring in the logical processor " + "which programmed the MSR" }, + { MSR1(1), "Counting the associated event conditions " + "occurring across all logical processors sharing " + "a processor core" }, { BITVAL_EOT } }}, { 1, 1, "EN0_Usr", "R/W", PRESENT_BIN, { @@ -1437,7 +1443,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x38e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", + {0x38e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PERF_GLOBAL_STATUS", "Global Performance Counter Status", { /* Also known as MSR_PERF_GLOBAL_STATUS */ /* if CPUID.0AH: EAX[7:0] > 0 */ @@ -1491,7 +1497,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", + {0x38f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_CTL", "Global Performance Counter Control", { /* Counter increments while the result of ANDing respective * enable bit in this MSR with corresponding OS or USR bits @@ -1522,7 +1528,7 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[7:0] > 0 */ - {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", + {0x390, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_GLOBAL_OVF_CTL", "Global Performance Counter Overflow Control", { /* if CPUID.0AH: EAX[7:0] > 0 */ { 63, 1, "Clear CondChg bit", "R/W", PRESENT_BIN, { @@ -1564,7 +1570,7 @@ const struct msrdef intel_nehalem_msrs[] = { * Software Developer's Manual, Volume 3, * "Precise Event Based Sampling (PEBS)". */ - {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "PEBS Control", { + {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PEBS_ENABLE", "PEBS Control", { { 63, 28, RESERVED }, { 35, 1, "Load Latency on IA32_PMC3", "R/W", PRESENT_BIN, { { MSR1(0), "Disabled" }, @@ -1609,91 +1615,91 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x3f6, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_LD_LAT", "", { + {0x3f6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_LD_LAT", "", { /* See Section 18.6.1.2 of Intel's manual * for additional information. */ { 63, 28, RESERVED }, { 35, 20, RESERVED }, - { 15, 16, "Minimum threshold latency value of tagged \ - load operation that will be counted", "R/W", PRESENT_DEC, { + { 15, 16, "Minimum threshold latency value of tagged " + "load operation that will be counted", "R/W", PRESENT_DEC, { { BITVAL_EOT } }}, { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + {0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", { { BITS_EOT } }}, - {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { { BITS_EOT } }}, - {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { { BITS_EOT } }}, - {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { { BITS_EOT } }}, - {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + {0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", { { BITS_EOT } }}, - {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { { BITS_EOT } }}, - {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { { BITS_EOT } }}, - {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { { BITS_EOT } }}, - {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, - {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", { { BITS_EOT } }}, - {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", { + {0x414, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_CTL", "", { { BITS_EOT } }}, - {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", { + {0x415, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_STATUS", "", { { BITS_EOT } }}, - {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", { + {0x416, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_ADDR", "", { { BITS_EOT } }}, - {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", { + {0x417, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC5_MISC", "", { { BITS_EOT } }}, - {0x480, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_BASIC", + {0x480, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_BASIC", "Reporting Register of Basic VMX Capabilities", { /* Additional info available at * Appendix A.1, "Basic VMX Information" */ @@ -1717,81 +1723,81 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x481, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PINBASED_CTLS", - "Capability Reporting Register of \ - Pin-based VM-execution Controls", { + {0x481, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PINBASED_CTLS", + "Capability Reporting Register of " + "Pin-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x482, MSRTYPE_RDONLY, MSR2(0,0), "IA32_PROCBASED_CTLS", - "Capability Reporting Register of \ - Primary Processor-based VM-execution Controls", { + {0x482, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_PROCBASED_CTLS", + "Capability Reporting Register of " + "Primary Processor-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, - {0x483, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_EXIT_CTLS", + {0x483, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_EXIT_CTLS", "Capability Reporting Register of VM-exit Controls", { /* Additional info available at Appendix A.4, * "VM-Exit Controls" */ { BITS_EOT } }}, - {0x484, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", + {0x484, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS", "Capability Reporting Register of VM-entry Controls", { /* Additional info available at Appendix A.5, * "VM-Entry Controls" */ { BITS_EOT } }}, - {0x485, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_MISC", + {0x485, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_MISC", "Reporting Register of Miscellaneous VMX Capabilities", { /* Additional info available at Appendix A.6, * "Miscellaneous Data" */ { BITS_EOT } }}, - {0x486, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED0", + {0x486, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED0", "Capability Reporting Register of CR0 Bits Fixed to 0", { /* Additional info available at Appendix A.7, * "VMX-Fixed Bits in CR0" */ { BITS_EOT } }}, - {0x487, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR0_FIXED1", + {0x487, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR0_FIXED1", "Capability Reporting Register of CR0 Bits Fixed to 1", { /* Additional info available at Appendix A.7, * "VMX-Fixed Bits in CR0" */ { BITS_EOT } }}, - {0x488, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED0", + {0x488, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED0", "Capability Reporting Register of CR4 Bits Fixed to 0", { /* Additional info available at Appendix A.8, * "VMX-Fixed Bits in CR4" */ { BITS_EOT } }}, - {0x489, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_CR4_FIXED1", + {0x489, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_CR4_FIXED1", "Capability Reporting Register of CR4 Bits Fixed to 1", { /* Additional info available at Appendix A.8, * "VMX-Fixed Bits in CR4" */ { BITS_EOT } }}, - {0x48a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_VMCS_ENUM", + {0x48a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_VMCS_ENUM", "Capability Reporting Register of VMCS Field Enumeration", { /* Additional info available at Appendix A.9, * "VMCS Enumeration" */ { BITS_EOT } }}, - {0x48b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", - "Capability Reporting Register of Secondary \ - Processor-based VM-execution Controls", { + {0x48b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", + "Capability Reporting Register of Secondary " + "Processor-based VM-execution Controls", { /* Additional info available at Appendix A.3, * "VM-Execution Controls" */ { BITS_EOT } }}, /* Undocumented PECI control register */ - {0x5a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_PECI_CTL", + {0x5a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PECI_CTL", "PECI Control Register", { { BITS_EOT } }}, - {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "DS Save Area", { + {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "DS Save Area", { /* Additional info available at Section 18.10.4 of Intel 64 * and IA-32 Architectures Software Developer's Manual, * "Debug Store (DS) Mechanism". @@ -1809,52 +1815,52 @@ const struct msrdef intel_nehalem_msrs[] = { * of last branch record registers * on the last branch record stack */ - {0x680, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "R/W", { + {0x680, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x681, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "R/W", { + {0x681, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x682, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "R/W", { + {0x682, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x683, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "R/W", { + {0x683, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x684, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "R/W", { + {0x684, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x685, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_FROM_IP", "R/W", { + {0x685, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x686, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "R/W", { + {0x686, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x687, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_FROM_IP", "R/W", { + {0x687, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x688, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_FROM_IP", "R/W", { + {0x688, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x689, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_9_FROM_IP", "R/W", { + {0x689, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_9_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x68a, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_FROM_IP", "R/W", { + {0x68a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x68b, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_11_FROM_IP", "R/W", { + {0x68b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_11_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x68c, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_FROM_IP", "R/W", { + {0x68c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x68d, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_13_FROM_IP", "R/W", { + {0x68d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_13_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x68e, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_FROM_IP", "R/W", { + {0x68e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_FROM_IP", "R/W", { { BITS_EOT } }}, - {0x68f, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_15_FROM_IP", "R/W", { + {0x68f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_15_FROM_IP", "R/W", { { BITS_EOT } }}, @@ -1863,62 +1869,62 @@ const struct msrdef intel_nehalem_msrs[] = { * of last branch record registers * on the last branch record stack */ - {0x6c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "R/W", { + {0x6c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "R/W", { + {0x6c1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_1_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "R/W", { + {0x6c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "R/W", { + {0x6c3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_LIP", "R/W", { + {0x6c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_5_TO_LIP", "R/W", { + {0x6c5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_5_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c6, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_LIP", "R/W", { + {0x6c6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_7_TO_LIP", "R/W", { + {0x6c7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_7_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_TO_LIP", "R/W", { + {0x6c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_9_TO_LIP", "R/W", { + {0x6c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_9_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_TO_LIP", "R/W", { + {0x6ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_11_TO_LIP", "R/W", { + {0x6cb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_11_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_TO_LIP", "R/W", { + {0x6cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_13_TO_LIP", "R/W", { + {0x6cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_13_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_TO_LIP", "R/W", { + {0x6ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_TO_LIP", "R/W", { { BITS_EOT } }}, - {0x6cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_15_TO_LIP", "R/W", { + {0x6cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_15_TO_LIP", "R/W", { { BITS_EOT } }}, /* x2APIC registers - see Intel 64 Architecture x2APIC Specification */ - {0x802, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_APICID", + {0x802, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_APICID", "x2APIC ID register", { { BITS_EOT } }}, - {0x803, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_VERSION", + {0x803, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_VERSION", /* Same version between extended and legacy modes. * Bit 24 is available only to an x2APIC unit. */ "x2APIC Version register", { @@ -1935,7 +1941,7 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x808, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_TPR", + {0x808, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_TPR", "x2APIC Task Priority register", { { 31, 24, RESERVED }, { 7, 8, "TPR", "R/W", PRESENT_HEX, { @@ -1943,22 +1949,22 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x80a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_PPR", + {0x80a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_PPR", "x2APIC Processor Priority register", { { BITS_EOT } }}, - {0x80b, MSRTYPE_WRONLY, MSR2(0,0), "IA32_X2APIC_EOI", + {0x80b, MSRTYPE_WRONLY, MSR2(0, 0), "IA32_X2APIC_EOI", /* 0 is the only valid value to write. GP fault * on non-zero write. */ "x2APIC EOI register", { { BITS_EOT } }}, - {0x80d, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_LDR", + {0x80d, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_LDR", /* Read Only in x2APIC mode, Read-Write in xAPIC mode. */ "x2APIC Logical Destination register", { { BITS_EOT } }}, - {0x80f, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_SIVR", + {0x80f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_SIVR", "x2APIC Spurious Interrupt Vector register", { { 31, 19, RESERVED }, { 12, 1, "EOI Broadcast Disable", "R/W", PRESENT_BIN, { @@ -1975,103 +1981,103 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x810, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_0", + {0x810, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_0", "x2APIC In-Service register bits [31:0]", { { BITS_EOT } }}, - {0x811, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_1", + {0x811, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_1", "x2APIC In-Service register bits [63:32]", { { BITS_EOT } }}, - {0x812, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_2", + {0x812, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_2", "x2APIC In-Service register bits [95:64]", { { BITS_EOT } }}, - {0x813, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_3", + {0x813, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_3", "x2APIC In-Service register bits [127:96]", { { BITS_EOT } }}, - {0x814, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_4", + {0x814, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_4", "x2APIC In-Service register bits [159:128]", { { BITS_EOT } }}, - {0x815, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_5", + {0x815, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_5", "x2APIC In-Service register bits [191:160]", { { BITS_EOT } }}, - {0x816, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_6", + {0x816, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_6", "x2APIC In-Service register bits [223:192]", { { BITS_EOT } }}, - {0x817, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_ISR_7", + {0x817, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_ISR_7", "x2APIC In-Service register bits [255:224]", { { BITS_EOT } }}, - {0x818, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR0", + {0x818, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR0", "x2APIC Trigger Mode register bits [31:0]", { { BITS_EOT } }}, - {0x819, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR1", + {0x819, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR1", "x2APIC Trigger Mode register bits [63:32]", { { BITS_EOT } }}, - {0x81a, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR2", + {0x81a, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR2", "x2APIC Trigger Mode register bits [95:64]", { { BITS_EOT } }}, - {0x81b, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR3", + {0x81b, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR3", "x2APIC Trigger Mode register bits [127:96]", { { BITS_EOT } }}, - {0x81c, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR4", + {0x81c, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR4", "x2APIC Trigger Mode register bits [159:128]", { { BITS_EOT } }}, - {0x81d, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR5", + {0x81d, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR5", "x2APIC Trigger Mode register bits [191:160]", { { BITS_EOT } }}, - {0x81e, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR6", + {0x81e, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR6", "x2APIC Trigger Mode register bits [223:192]", { { BITS_EOT } }}, - {0x81f, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_TMR7", + {0x81f, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_TMR7", "x2APIC Trigger Mode register bits [255:224]", { { BITS_EOT } }}, - {0x820, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR0", + {0x820, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR0", "x2APIC Interrupt Request register bits [31:0]", { { BITS_EOT } }}, - {0x821, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR1", + {0x821, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR1", "x2APIC Trigger Mode register bits [63:32]", { { BITS_EOT } }}, - {0x822, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR2", + {0x822, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR2", "x2APIC Trigger Mode register bits [95:64]", { { BITS_EOT } }}, - {0x823, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR3", + {0x823, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR3", "x2APIC Trigger Mode register bits [127:96]", { { BITS_EOT } }}, - {0x824, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR4", + {0x824, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR4", "x2APIC Trigger Mode register bits [159:128]", { { BITS_EOT } }}, - {0x825, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR5", + {0x825, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR5", "x2APIC Trigger Mode register bits [191:160]", { { BITS_EOT } }}, - {0x826, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR6", + {0x826, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR6", "x2APIC Trigger Mode register bits [223:192]", { { BITS_EOT } }}, - {0x827, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_IRR7", + {0x827, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_IRR7", "x2APIC Trigger Mode register bits [255:224]", { { BITS_EOT } }}, - {0x828, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_ESR", + {0x828, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_ESR", /* GP fault on non-zero writes. */ "x2APIC Error Status register", { { 31, 24, RESERVED }, @@ -2090,11 +2096,11 @@ const struct msrdef intel_nehalem_msrs[] = { { 3, 4, RESERVED }, { BITS_EOT } }}, - {0x82f, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_CMCI", + {0x82f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_CMCI", "x2APIC LVT Corrected Machine Check Interrupt register", { { BITS_EOT } }}, - {0x830, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_ICR", + {0x830, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_ICR", "x2APIC Interrupt Command register", { { 63, 32, "Destination field", "R/W", PRESENT_HEX, { { BITVAL_EOT } @@ -2140,43 +2146,43 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x832, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_TIMER", + {0x832, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_TIMER", "x2APIC LVT Timer Interrupt register", { { BITS_EOT } }}, - {0x833, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_THERMAL", + {0x833, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_THERMAL", "x2APIC LVT Thermal Sensor Interrupt register", { { BITS_EOT } }}, - {0x834, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_PMI", + {0x834, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_PMI", "x2APIC LVT Performance Monitor register", { { BITS_EOT } }}, - {0x835, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_LINT0", + {0x835, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_LINT0", "x2APIC LVT LINT0 register", { { BITS_EOT } }}, - {0x836, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_LINT1", + {0x836, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_LINT1", "x2APIC LVT LINT1 register", { { BITS_EOT } }}, - {0x837, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_LVT_ERROR", + {0x837, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_LVT_ERROR", "x2APIC LVT Error register", { { BITS_EOT } }}, - {0x838, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_INIT_COUNT", + {0x838, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_INIT_COUNT", "x2APIC Initial Count register", { { BITS_EOT } }}, - {0x839, MSRTYPE_RDONLY, MSR2(0,0), "IA32_X2APIC_CUR_COUNT", + {0x839, MSRTYPE_RDONLY, MSR2(0, 0), "IA32_X2APIC_CUR_COUNT", "x2APIC Current Count register", { { BITS_EOT } }}, - {0x83e, MSRTYPE_RDWR, MSR2(0,0), "IA32_X2APIC_DIV_CONF", + {0x83e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_X2APIC_DIV_CONF", "x2APIC Divide Configuration register", { { BITS_EOT } }}, - {0x83f, MSRTYPE_WRONLY, MSR2(0,0), "IA32_X2APIC_SELF_IPI", + {0x83f, MSRTYPE_WRONLY, MSR2(0, 0), "IA32_X2APIC_SELF_IPI", "x2APIC Self IPI register", { /* Only in x2APIC mode. */ { 31, 24, RESERVED }, @@ -2185,35 +2191,35 @@ const struct msrdef intel_nehalem_msrs[] = { }}, { BITS_EOT } }}, - {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", { + {0x107cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL0", "", { { BITS_EOT } }}, - {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", { + {0x107cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL1", "", { { BITS_EOT } }}, - {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", { + {0x107ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL2", "", { { BITS_EOT } }}, - {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", { + {0x107cf, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL3", "", { { BITS_EOT } }}, - {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", { + {0x107d0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL4", "", { { BITS_EOT } }}, - {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", { + {0x107d1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL5", "", { { BITS_EOT } }}, - {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", { + {0x107d2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL6", "", { { BITS_EOT } }}, - {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", { + {0x107d3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_CTR_CTL7", "", { { BITS_EOT } }}, - {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", { + {0x107d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EMON_L3_GL_CTL", "", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 or CPUID.80000001H: EDX[27] = 1 */ - {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", + {0xc0000080, MSRTYPE_RDWR, MSR2(0, 0), "IA32_EFER", "Extended Feature Enables", { { 63, 52, RESERVED }, { 11, 1, "Execute Disable Bit", "R/O", PRESENT_BIN, { @@ -2240,37 +2246,37 @@ const struct msrdef intel_nehalem_msrs[] = { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 */ - {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", + {0xc0000081, MSRTYPE_RDWR, MSR2(0, 0), "IA32_STAR", "System Call Target Address", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 */ - {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", + {0xc0000082, MSRTYPE_RDWR, MSR2(0, 0), "IA32_LSTAR", "IA32e Mode System Call Target Address", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 */ - {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", + {0xc0000084, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FMASK", "System Call Flag Mask", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 */ - {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", + {0xc0000100, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FS_BASE", "Map of BASE Address of FS", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 */ - {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", + {0xc0000101, MSRTYPE_RDWR, MSR2(0, 0), "IA32_GS_BASE", "Map of BASE Address of GS", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[29] = 1 */ - {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", + {0xc0000102, MSRTYPE_RDWR, MSR2(0, 0), "IA32_KERNEL_GS_BASE", "Swap Target of BASE Address of GS", { { BITS_EOT } }}, /* if CPUID.80000001H: EDX[27] = 1 */ - {0xc0000103, MSRTYPE_RDWR, MSR2(0,0), "IA32_TSC_AUX", + {0xc0000103, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TSC_AUX", "AUXILIARY TSC Signature", { { BITS_EOT } }}, diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c index 34d38a8870..e541e00e95 100644 --- a/util/msrtool/intel_pentium3.c +++ b/util/msrtool/intel_pentium3.c @@ -24,157 +24,157 @@ int intel_pentium3_probe(const struct targetdef *target, const struct cpuid_t *i } const struct msrdef intel_pentium3_msrs[] = { - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", { + {0x33, MSRTYPE_RDWR, MSR2(0, 0), "TEST_CTL", "", { { BITS_EOT } }}, - {0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", { + {0x3f, MSRTYPE_RDWR, MSR2(0, 0), "THERM_DIODE_OFFSET", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { { BITS_EOT } }}, - {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", { { BITS_EOT } }}, - {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", { { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CONTROL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c index f62439de68..dbbc985b4d 100644 --- a/util/msrtool/intel_pentium3_early.c +++ b/util/msrtool/intel_pentium3_early.c @@ -24,232 +24,232 @@ int intel_pentium3_early_probe(const struct targetdef *target, const struct cpui } const struct msrdef intel_pentium3_early_msrs[] = { - {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", { { BITS_EOT } }}, - {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", { + {0x33, MSRTYPE_RDWR, MSR2(0, 0), "TEST_CTL", "", { { BITS_EOT } }}, - {0x88, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D0", "", { + {0x88, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_D0", "", { { BITS_EOT } }}, - {0x89, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D1", "", { + {0x89, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_D1", "", { { BITS_EOT } }}, - {0x8a, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_D2", "", { + {0x8a, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_D2", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { { BITS_EOT } }}, - {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", { { BITS_EOT } }}, - {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x116, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_ADDR", "", { + {0x116, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_ADDR", "", { { BITS_EOT } }}, - {0x118, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_DECC", "", { + {0x118, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_DECC", "", { { BITS_EOT } }}, - {0x119, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL", "", { + {0x119, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL", "", { { BITS_EOT } }}, - {0x11b, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_BUSY", "", { + {0x11b, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_BUSY", "", { { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { { BITS_EOT } }}, - {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { { BITS_EOT } }}, - {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { { BITS_EOT } }}, - {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { BITS_EOT } }}, - {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { + {0x17b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CTL", "", { { BITS_EOT } }}, - {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL0", "", { + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL0", "", { { BITS_EOT } }}, - {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_EVNTSEL1", "", { + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_EVNTSEL1", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DEBUGCTL", "", { { BITS_EOT } }}, - {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHFROMIP", "", { + {0x1db, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCHFROMIP", "", { { BITS_EOT } }}, - {0x1dc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCHTOIP", "", { + {0x1dc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCHTOIP", "", { { BITS_EOT } }}, - {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTFROMIP", "", { + {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTINTFROMIP", "", { { BITS_EOT } }}, - {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTINTTOIP", "", { + {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTINTTOIP", "", { { BITS_EOT } }}, - {0x1e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_ROB_CR_BKUPTMPDR6", "", { + {0x1e0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ROB_CR_BKUPTMPDR6", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { { BITS_EOT } }}, - {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { { BITS_EOT } }}, - {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { { BITS_EOT } }}, - {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { { BITS_EOT } }}, - {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { { BITS_EOT } }}, - {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/intel_pentium4_early.c b/util/msrtool/intel_pentium4_early.c index 649be04349..088a68ddcc 100644 --- a/util/msrtool/intel_pentium4_early.c +++ b/util/msrtool/intel_pentium4_early.c @@ -22,544 +22,544 @@ int intel_pentium4_early_probe(const struct targetdef *target, const struct cpui } const struct msrdef intel_pentium4_early_msrs[] = { - {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", { { BITS_EOT } }}, - {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", { { BITS_EOT } }}, - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", { { BITS_EOT } }}, - {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWRON", "", { + {0x2b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWRON", "", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, - {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", { + {0x300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", { { BITS_EOT } }}, - {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", { + {0x301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", { { BITS_EOT } }}, - {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", { + {0x302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", { { BITS_EOT } }}, - {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", { + {0x303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", { { BITS_EOT } }}, - {0x304, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER0", "", { + {0x304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", { { BITS_EOT } }}, - {0x305, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER1", "", { + {0x305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", { { BITS_EOT } }}, - {0x306, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER2", "", { + {0x306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", { { BITS_EOT } }}, - {0x307, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER3", "", { + {0x307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", { { BITS_EOT } }}, - {0x308, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER0", "", { + {0x308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", { { BITS_EOT } }}, - {0x309, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER1", "", { + {0x309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", { { BITS_EOT } }}, - {0x30a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER2", "", { + {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER2", "", { { BITS_EOT } }}, - {0x30b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER3", "", { + {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", { { BITS_EOT } }}, - {0x30c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER0", "", { + {0x30c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", { { BITS_EOT } }}, - {0x30d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER1", "", { + {0x30d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", { { BITS_EOT } }}, - {0x30e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER2", "", { + {0x30e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", { { BITS_EOT } }}, - {0x30f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER3", "", { + {0x30f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", { { BITS_EOT } }}, - {0x310, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER4", "", { + {0x310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", { { BITS_EOT } }}, - {0x311, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER5", "", { + {0x311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", { { BITS_EOT } }}, - {0x360, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR0", "", { + {0x360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", { { BITS_EOT } }}, - {0x361, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR1", "", { + {0x361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", { { BITS_EOT } }}, - {0x362, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR2", "", { + {0x362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", { { BITS_EOT } }}, - {0x363, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR3", "", { + {0x363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", { { BITS_EOT } }}, - {0x364, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR0", "", { + {0x364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", { { BITS_EOT } }}, - {0x365, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR1", "", { + {0x365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", { { BITS_EOT } }}, - {0x366, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR2", "", { + {0x366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", { { BITS_EOT } }}, - {0x367, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR3", "", { + {0x367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", { { BITS_EOT } }}, - {0x368, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR0", "", { + {0x368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", { { BITS_EOT } }}, - {0x369, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR1", "", { + {0x369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", { { BITS_EOT } }}, - {0x36a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR2", "", { + {0x36a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", { { BITS_EOT } }}, - {0x36b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR3", "", { + {0x36b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", { { BITS_EOT } }}, - {0x36c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR0", "", { + {0x36c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", { { BITS_EOT } }}, - {0x36d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR1", "", { + {0x36d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", { { BITS_EOT } }}, - {0x36e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR2", "", { + {0x36e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", { { BITS_EOT } }}, - {0x36f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR3", "", { + {0x36f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", { { BITS_EOT } }}, - {0x370, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR4", "", { + {0x370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", { { BITS_EOT } }}, - {0x371, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR5", "", { + {0x371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", { { BITS_EOT } }}, - {0x3a0, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR0", "", { + {0x3a0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", { { BITS_EOT } }}, - {0x3a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR1", "", { + {0x3a1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", { { BITS_EOT } }}, - {0x3a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR0", "", { + {0x3a2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", { { BITS_EOT } }}, - {0x3a3, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR1", "", { + {0x3a3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", { { BITS_EOT } }}, - {0x3a4, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR0", "", { + {0x3a4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", { { BITS_EOT } }}, - {0x3a5, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR1", "", { + {0x3a5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", { { BITS_EOT } }}, - {0x3a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR0", "", { + {0x3a6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", { { BITS_EOT } }}, - {0x3a7, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR1", "", { + {0x3a7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", { { BITS_EOT } }}, - {0x3a8, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR0", "", { + {0x3a8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", { { BITS_EOT } }}, - {0x3a9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR1", "", { + {0x3a9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", { { BITS_EOT } }}, - {0x3aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR0", "", { + {0x3aa, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", { { BITS_EOT } }}, - {0x3ab, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR1", "", { + {0x3ab, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", { { BITS_EOT } }}, - {0x3ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR0", "", { + {0x3ac, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", { { BITS_EOT } }}, - {0x3ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR1", "", { + {0x3ad, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", { { BITS_EOT } }}, - {0x3ae, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR0", "", { + {0x3ae, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", { { BITS_EOT } }}, - {0x3af, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR1", "", { + {0x3af, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", { { BITS_EOT } }}, - {0x3b0, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR0", "", { + {0x3b0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", { { BITS_EOT } }}, - {0x3b1, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR1", "", { + {0x3b1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", { { BITS_EOT } }}, - {0x3b2, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR0", "", { + {0x3b2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", { { BITS_EOT } }}, - {0x3b3, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { + {0x3b3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", { { BITS_EOT } }}, - {0x3b4, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR0", "", { + {0x3b4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", { { BITS_EOT } }}, - {0x3b5, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { + {0x3b5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", { { BITS_EOT } }}, - {0x3b6, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR0", "", { + {0x3b6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", { { BITS_EOT } }}, - {0x3b7, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR1", "", { + {0x3b7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", { { BITS_EOT } }}, - {0x3b8, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR0", "", { + {0x3b8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", { { BITS_EOT } }}, - {0x3b9, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR1", "", { + {0x3b9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", { { BITS_EOT } }}, - {0x3ba, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR0", "", { + {0x3ba, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", { { BITS_EOT } }}, - {0x3bb, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR1", "", { + {0x3bb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", { { BITS_EOT } }}, - {0x3bc, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR0", "", { + {0x3bc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", { { BITS_EOT } }}, - {0x3bd, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR1", "", { + {0x3bd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", { { BITS_EOT } }}, - {0x3be, MSRTYPE_RDWR, MSR2(0,0), "MSR_SSU_ESCR0", "", { + {0x3be, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", { { BITS_EOT } }}, - {0x3c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR0", "", { + {0x3c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", { { BITS_EOT } }}, - {0x3c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR1", "", { + {0x3c1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", { { BITS_EOT } }}, - {0x3c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR0", "", { + {0x3c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", { { BITS_EOT } }}, - {0x3c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR1", "", { + {0x3c3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", { { BITS_EOT } }}, - {0x3c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR0", "", { + {0x3c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", { { BITS_EOT } }}, - {0x3c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR1", "", { + {0x3c5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", { { BITS_EOT } }}, - {0x3c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", { + {0x3c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", { { BITS_EOT } }}, - {0x3c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR1", "", { + {0x3c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR1", "", { { BITS_EOT } }}, - {0x3ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR0", "", { + {0x3ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", { { BITS_EOT } }}, - {0x3cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR1", "", { + {0x3cb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", { { BITS_EOT } }}, - {0x3cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR2", "", { + {0x3cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", { { BITS_EOT } }}, - {0x3cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR3", "", { + {0x3cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", { { BITS_EOT } }}, - {0x3e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR4", "", { + {0x3e0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", { { BITS_EOT } }}, - {0x3e1, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR5", "", { + {0x3e1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", { { BITS_EOT } }}, - {0x3f0, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_PRECISE_EVENT", "", { + {0x3f0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", { { BITS_EOT } }}, - {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_ENABLE", "", { + {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", { { BITS_EOT } }}, - {0x3f2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_MATRIX_VERT", "", { + {0x3f2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", { { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, - {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + {0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", { { BITS_EOT } }}, - {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { { BITS_EOT } }}, - {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { { BITS_EOT } }}, - {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { { BITS_EOT } }}, - {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + {0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", { { BITS_EOT } }}, - {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { { BITS_EOT } }}, - {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { { BITS_EOT } }}, - {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { { BITS_EOT } }}, - {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, - {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { { BITS_EOT } }}, - {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { { BITS_EOT } }}, - {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { BITS_EOT } }}, - {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { + {0x17b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CTL", "", { { BITS_EOT } }}, - {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", { + {0x180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", { { BITS_EOT } }}, - {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", { + {0x181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", { { BITS_EOT } }}, - {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", { + {0x182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", { { BITS_EOT } }}, - {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", { + {0x183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", { { BITS_EOT } }}, - {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", { + {0x184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", { { BITS_EOT } }}, - {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", { + {0x185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", { { BITS_EOT } }}, - {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", { + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBP", "", { { BITS_EOT } }}, - {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", { + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSP", "", { { BITS_EOT } }}, - {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", { + {0x188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", { { BITS_EOT } }}, - {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", { + {0x189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", { { BITS_EOT } }}, - {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", { + {0x18a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", { { BITS_EOT } }}, - {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", { + {0x190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", { { BITS_EOT } }}, - {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", { + {0x191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", { { BITS_EOT } }}, - {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", { + {0x192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", { { BITS_EOT } }}, - {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", { + {0x193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", { { BITS_EOT } }}, - {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", { + {0x194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", { { BITS_EOT } }}, - {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", { + {0x195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", { { BITS_EOT } }}, - {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", { + {0x196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", { { BITS_EOT } }}, - {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", { + {0x197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "", { { BITS_EOT } }}, - {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + {0x1d7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", { { BITS_EOT } }}, - {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + {0x1d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DEBUGCTLA", "", { { BITS_EOT } }}, - {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", { + {0x1da, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_TOS", "", { { BITS_EOT } }}, - {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0", "", { + {0x1db, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0", "", { { BITS_EOT } }}, - {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2", "", { + {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2", "", { { BITS_EOT } }}, - {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3", "", { + {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3", "", { { BITS_EOT } }}, - {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { + {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", { { BITS_EOT } }}, - {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { + {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/intel_pentium4_later.c b/util/msrtool/intel_pentium4_later.c index 54441612fa..a23a99e606 100644 --- a/util/msrtool/intel_pentium4_later.c +++ b/util/msrtool/intel_pentium4_later.c @@ -24,531 +24,531 @@ int intel_pentium4_later_probe(const struct targetdef *target, const struct cpui } const struct msrdef intel_pentium4_later_msrs[] = { - {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", { + {0x0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_ADDR", "", { { BITS_EOT } }}, - {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", { + {0x1, MSRTYPE_RDWR, MSR2(0, 0), "IA32_P5_MC_TYPE", "", { { BITS_EOT } }}, - {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_LINE_SIZE", "", { + {0x6, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MONITOR_FILTER_LINE_SIZE", "", { { BITS_EOT } }}, - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { + {0x17, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PLATFORM_ID", "", { { BITS_EOT } }}, - {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { + {0x1b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_APIC_BASE", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_HARD_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_HARD_POWERON", "", { { BITS_EOT } }}, - {0x2b, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_SOFT_POWERON", "", { + {0x2b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_SOFT_POWERON", "", { { BITS_EOT } }}, - {0x2c, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBC_FREQUENCY_ID", "", { + {0x2c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_EBC_FREQUENCY_ID", "", { { BITS_EOT } }}, - {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", { + {0x3a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_FEATURE_CONTROL", "", { { BITS_EOT } }}, - {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", { + {0x79, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_UPDT_TRIG", "", { { BITS_EOT } }}, - {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { + {0x8b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_BIOS_SIGN_ID", "", { { BITS_EOT } }}, - {0x9b, MSRTYPE_RDWR, MSR2(0,0), "IA32_SMM_MONITOR_CTL", "", { + {0x9b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SMM_MONITOR_CTL", "", { { BITS_EOT } }}, - {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", { + {0xfe, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRRCAP", "", { { BITS_EOT } }}, - {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", { + {0x174, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_CS", "", { { BITS_EOT } }}, - {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", { + {0x175, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_ESP", "", { { BITS_EOT } }}, - {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", { + {0x176, MSRTYPE_RDWR, MSR2(0, 0), "IA32_SYSENTER_EIP", "", { { BITS_EOT } }}, - {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { + {0x179, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CAP", "", { { BITS_EOT } }}, - {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { + {0x17a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_STATUS", "", { { BITS_EOT } }}, - {0x17b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CTL", "", { + {0x17b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MCG_CTL", "", { { BITS_EOT } }}, - {0x180, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RAX", "", { + {0x180, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RAX", "", { { BITS_EOT } }}, - {0x181, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBX", "", { + {0x181, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBX", "", { { BITS_EOT } }}, - {0x182, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RCX", "", { + {0x182, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RCX", "", { { BITS_EOT } }}, - {0x183, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDX", "", { + {0x183, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDX", "", { { BITS_EOT } }}, - {0x184, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSI", "", { + {0x184, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSI", "", { { BITS_EOT } }}, - {0x185, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RDI", "", { + {0x185, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RDI", "", { { BITS_EOT } }}, - {0x186, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RBP", "", { + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RBP", "", { { BITS_EOT } }}, - {0x187, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RSP", "", { + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RSP", "", { { BITS_EOT } }}, - {0x188, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RFLAGS", "", { + {0x188, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RFLAGS", "", { { BITS_EOT } }}, - {0x189, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RIP", "", { + {0x189, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RIP", "", { { BITS_EOT } }}, - {0x18a, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_MISC", "", { + {0x18a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_MISC", "", { { BITS_EOT } }}, - {0x18b, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED1", "", { + {0x18b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED1", "", { { BITS_EOT } }}, - {0x18c, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED2", "", { + {0x18c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED2", "", { { BITS_EOT } }}, - {0x18d, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED3", "", { + {0x18d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED3", "", { { BITS_EOT } }}, - {0x18e, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED4", "", { + {0x18e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED4", "", { { BITS_EOT } }}, - {0x18f, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_RESERVED5", "", { + {0x18f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_RESERVED5", "", { { BITS_EOT } }}, - {0x190, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R8", "", { + {0x190, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R8", "", { { BITS_EOT } }}, - {0x191, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R9", "", { + {0x191, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R9", "", { { BITS_EOT } }}, - {0x192, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R10", "", { + {0x192, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R10", "", { { BITS_EOT } }}, - {0x193, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R11", "", { + {0x193, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R11", "", { { BITS_EOT } }}, - {0x194, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R12", "", { + {0x194, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R12", "", { { BITS_EOT } }}, - {0x195, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R13", "", { + {0x195, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R13", "", { { BITS_EOT } }}, - {0x196, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R14", "", { + {0x196, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R14", "", { { BITS_EOT } }}, - {0x197, MSRTYPE_RDWR, MSR2(0,0), "MSR_MCG_R15", "", { + {0x197, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MCG_R15", "", { { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLE", "", { { BITS_EOT } }}, - {0x1a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PLATFORM_BRV", "", { + {0x1a1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PLATFORM_BRV", "", { { BITS_EOT } }}, - {0x1d7, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", { + {0x1d7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_FROM_LIP", "", { { BITS_EOT } }}, - {0x1d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", { + {0x1d8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LER_TO_LIP", "", { { BITS_EOT } }}, - {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DEBUGCTLA", "", { + {0x1d9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DEBUGCTLA", "", { { BITS_EOT } }}, - {0x1da, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH", "", { + {0x1da, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH", "", { { BITS_EOT } }}, - {0x1db, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0", "", { + {0x1db, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0", "", { { BITS_EOT } }}, - {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2", "", { + {0x1dd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2", "", { { BITS_EOT } }}, - {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3", "", { + {0x1de, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_3", "", { { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", { + {0x277, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PAT", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, - {0x300, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER0", "", { + {0x300, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER0", "", { { BITS_EOT } }}, - {0x301, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER1", "", { + {0x301, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER1", "", { { BITS_EOT } }}, - {0x302, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER2", "", { + {0x302, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER2", "", { { BITS_EOT } }}, - {0x303, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_COUNTER3", "", { + {0x303, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_COUNTER3", "", { { BITS_EOT } }}, - {0x304, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER0", "", { + {0x304, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER0", "", { { BITS_EOT } }}, - {0x305, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER1", "", { + {0x305, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER1", "", { { BITS_EOT } }}, - {0x306, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER2", "", { + {0x306, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER2", "", { { BITS_EOT } }}, - {0x307, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_COUNTER3", "", { + {0x307, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_COUNTER3", "", { { BITS_EOT } }}, - {0x308, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER0", "", { + {0x308, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER0", "", { { BITS_EOT } }}, - {0x309, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER1", "", { + {0x309, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER1", "", { { BITS_EOT } }}, - {0x30a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER2", "", { + {0x30a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER2", "", { { BITS_EOT } }}, - {0x30b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_COUNTER3", "", { + {0x30b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_COUNTER3", "", { { BITS_EOT } }}, - {0x30c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER0", "", { + {0x30c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER0", "", { { BITS_EOT } }}, - {0x30d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER1", "", { + {0x30d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER1", "", { { BITS_EOT } }}, - {0x30e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER2", "", { + {0x30e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER2", "", { { BITS_EOT } }}, - {0x30f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER3", "", { + {0x30f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER3", "", { { BITS_EOT } }}, - {0x310, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER4", "", { + {0x310, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER4", "", { { BITS_EOT } }}, - {0x311, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_COUNTER5", "", { + {0x311, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_COUNTER5", "", { { BITS_EOT } }}, - {0x360, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR0", "", { + {0x360, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR0", "", { { BITS_EOT } }}, - {0x361, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR1", "", { + {0x361, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR1", "", { { BITS_EOT } }}, - {0x362, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR2", "", { + {0x362, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR2", "", { { BITS_EOT } }}, - {0x363, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_CCCR3", "", { + {0x363, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_CCCR3", "", { { BITS_EOT } }}, - {0x364, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR0", "", { + {0x364, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR0", "", { { BITS_EOT } }}, - {0x365, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR1", "", { + {0x365, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR1", "", { { BITS_EOT } }}, - {0x366, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR2", "", { + {0x366, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR2", "", { { BITS_EOT } }}, - {0x367, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_CCCR3", "", { + {0x367, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_CCCR3", "", { { BITS_EOT } }}, - {0x368, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR0", "", { + {0x368, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR0", "", { { BITS_EOT } }}, - {0x369, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR1", "", { + {0x369, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR1", "", { { BITS_EOT } }}, - {0x36a, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR2", "", { + {0x36a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR2", "", { { BITS_EOT } }}, - {0x36b, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_CCCR3", "", { + {0x36b, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_CCCR3", "", { { BITS_EOT } }}, - {0x36c, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR0", "", { + {0x36c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR0", "", { { BITS_EOT } }}, - {0x36d, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR1", "", { + {0x36d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR1", "", { { BITS_EOT } }}, - {0x36e, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR2", "", { + {0x36e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR2", "", { { BITS_EOT } }}, - {0x36f, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR3", "", { + {0x36f, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR3", "", { { BITS_EOT } }}, - {0x370, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR4", "", { + {0x370, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR4", "", { { BITS_EOT } }}, - {0x371, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_CCCR5", "", { + {0x371, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_CCCR5", "", { { BITS_EOT } }}, - {0x3a0, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR0", "", { + {0x3a0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR0", "", { { BITS_EOT } }}, - {0x3a1, MSRTYPE_RDWR, MSR2(0,0), "MSR_BSU_ESCR1", "", { + {0x3a1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BSU_ESCR1", "", { { BITS_EOT } }}, - {0x3a2, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR0", "", { + {0x3a2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR0", "", { { BITS_EOT } }}, - {0x3a3, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_ESCR1", "", { + {0x3a3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FSB_ESCR1", "", { { BITS_EOT } }}, - {0x3a4, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR0", "", { + {0x3a4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR0", "", { { BITS_EOT } }}, - {0x3a5, MSRTYPE_RDWR, MSR2(0,0), "MSR_FIRM_ESCR1", "", { + {0x3a5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FIRM_ESCR1", "", { { BITS_EOT } }}, - {0x3a6, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR0", "", { + {0x3a6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR0", "", { { BITS_EOT } }}, - {0x3a7, MSRTYPE_RDWR, MSR2(0,0), "MSR_FLAME_ESCR1", "", { + {0x3a7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_FLAME_ESCR1", "", { { BITS_EOT } }}, - {0x3a8, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR0", "", { + {0x3a8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR0", "", { { BITS_EOT } }}, - {0x3a9, MSRTYPE_RDWR, MSR2(0,0), "MSR_DAC_ESCR1", "", { + {0x3a9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_DAC_ESCR1", "", { { BITS_EOT } }}, - {0x3aa, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR0", "", { + {0x3aa, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR0", "", { { BITS_EOT } }}, - {0x3ab, MSRTYPE_RDWR, MSR2(0,0), "MSR_MOB_ESCR1", "", { + {0x3ab, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MOB_ESCR1", "", { { BITS_EOT } }}, - {0x3ac, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR0", "", { + {0x3ac, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR0", "", { { BITS_EOT } }}, - {0x3ad, MSRTYPE_RDWR, MSR2(0,0), "MSR_PMH_ESCR1", "", { + {0x3ad, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PMH_ESCR1", "", { { BITS_EOT } }}, - {0x3ae, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR0", "", { + {0x3ae, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR0", "", { { BITS_EOT } }}, - {0x3af, MSRTYPE_RDWR, MSR2(0,0), "MSR_SAAT_ESCR1", "", { + {0x3af, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SAAT_ESCR1", "", { { BITS_EOT } }}, - {0x3b0, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR0", "", { + {0x3b0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR0", "", { { BITS_EOT } }}, - {0x3b1, MSRTYPE_RDWR, MSR2(0,0), "MSR_U2L_ESCR1", "", { + {0x3b1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_U2L_ESCR1", "", { { BITS_EOT } }}, - {0x3b2, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR0", "", { + {0x3b2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR0", "", { { BITS_EOT } }}, - {0x3b3, MSRTYPE_RDWR, MSR2(0,0), "MSR_BPU_ESCR1", "", { + {0x3b3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_BPU_ESCR1", "", { { BITS_EOT } }}, - {0x3b4, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR0", "", { + {0x3b4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR0", "", { { BITS_EOT } }}, - {0x3b5, MSRTYPE_RDWR, MSR2(0,0), "MSR_IS_ESCR1", "", { + {0x3b5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IS_ESCR1", "", { { BITS_EOT } }}, - {0x3b6, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR0", "", { + {0x3b6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR0", "", { { BITS_EOT } }}, - {0x3b7, MSRTYPE_RDWR, MSR2(0,0), "MSR_ITLB_ESCR1", "", { + {0x3b7, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ITLB_ESCR1", "", { { BITS_EOT } }}, - {0x3b8, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR0", "", { + {0x3b8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR0", "", { { BITS_EOT } }}, - {0x3b9, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR1", "", { + {0x3b9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR1", "", { { BITS_EOT } }}, - {0x3ba, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR0", "", { + {0x3ba, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR0", "", { { BITS_EOT } }}, /* MSR_IQ_ESCR1 MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H */ - //{0x3bb, MSRTYPE_RDWR, MSR2(0,0), "MSR_IQ_ESCR1", "", { + //{0x3bb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IQ_ESCR1", "", { // { BITS_EOT } //}}, - {0x3bc, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR0", "", { + {0x3bc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR0", "", { { BITS_EOT } }}, - {0x3bd, MSRTYPE_RDWR, MSR2(0,0), "MSR_RAT_ESCR1", "", { + {0x3bd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_RAT_ESCR1", "", { { BITS_EOT } }}, - {0x3be, MSRTYPE_RDWR, MSR2(0,0), "MSR_SSU_ESCR0", "", { + {0x3be, MSRTYPE_RDWR, MSR2(0, 0), "MSR_SSU_ESCR0", "", { { BITS_EOT } }}, - {0x3c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR0", "", { + {0x3c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR0", "", { { BITS_EOT } }}, - {0x3c1, MSRTYPE_RDWR, MSR2(0,0), "MSR_MS_ESCR1", "", { + {0x3c1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_MS_ESCR1", "", { { BITS_EOT } }}, - {0x3c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR0", "", { + {0x3c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR0", "", { { BITS_EOT } }}, - {0x3c3, MSRTYPE_RDWR, MSR2(0,0), "MSR_TBPU_ESCR1", "", { + {0x3c3, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TBPU_ESCR1", "", { { BITS_EOT } }}, - {0x3c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR0", "", { + {0x3c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR0", "", { { BITS_EOT } }}, - {0x3c5, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_ESCR1", "", { + {0x3c5, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_ESCR1", "", { { BITS_EOT } }}, - {0x3c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", { + {0x3c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", { { BITS_EOT } }}, - {0x3c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_IX_ESCR0", "", { + {0x3c9, MSRTYPE_RDWR, MSR2(0, 0), "MSR_IX_ESCR0", "", { { BITS_EOT } }}, - {0x3ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR0", "", { + {0x3ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR0", "", { { BITS_EOT } }}, - {0x3cb, MSRTYPE_RDWR, MSR2(0,0), "MSR_ALF_ESCR1", "", { + {0x3cb, MSRTYPE_RDWR, MSR2(0, 0), "MSR_ALF_ESCR1", "", { { BITS_EOT } }}, - {0x3cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR2", "", { + {0x3cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR2", "", { { BITS_EOT } }}, - {0x3cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR3", "", { + {0x3cd, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR3", "", { { BITS_EOT } }}, - {0x3e0, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR4", "", { + {0x3e0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR4", "", { { BITS_EOT } }}, - {0x3e1, MSRTYPE_RDWR, MSR2(0,0), "MSR_CRU_ESCR5", "", { + {0x3e1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_CRU_ESCR5", "", { { BITS_EOT } }}, - {0x3f0, MSRTYPE_RDWR, MSR2(0,0), "MSR_TC_PRECISE_EVENT", "", { + {0x3f0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_TC_PRECISE_EVENT", "", { { BITS_EOT } }}, - {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_ENABLE", "", { + {0x3f1, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_ENABLE", "", { { BITS_EOT } }}, - {0x3f2, MSRTYPE_RDWR, MSR2(0,0), "MSR_PEBS_MATRIX_VERT", "", { + {0x3f2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_PEBS_MATRIX_VERT", "", { { BITS_EOT } }}, - {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { + {0x400, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_CTL", "", { { BITS_EOT } }}, - {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { + {0x401, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_STATUS", "", { { BITS_EOT } }}, - {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { + {0x402, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_ADDR", "", { { BITS_EOT } }}, /* The IA32_MC0_MISC MSR is either not implemented or does @@ -556,16 +556,16 @@ const struct msrdef intel_pentium4_later_msrs[] = { the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a generalprotection exception. */ - //{0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", { + //{0x403, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC0_MISC", "", { // { BITS_EOT } //}}, - {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", { + {0x404, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_CTL", "", { { BITS_EOT } }}, - {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", { + {0x405, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_STATUS", "", { { BITS_EOT } }}, - {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", { + {0x406, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_ADDR", "", { { BITS_EOT } }}, /* The IA32_MC1_MISC MSR is either not implemented or does @@ -573,118 +573,118 @@ const struct msrdef intel_pentium4_later_msrs[] = { the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a generalprotection exception.*/ - //{0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", { + //{0x407, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC1_MISC", "", { // { BITS_EOT } //}}, - {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", { + {0x408, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_CTL", "", { { BITS_EOT } }}, - {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", { + {0x409, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_STATUS", "", { { BITS_EOT } }}, - {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", { + {0x40a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_ADDR", "", { { BITS_EOT } }}, - {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", { + {0x40b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC2_MISC", "", { { BITS_EOT } }}, - {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", { + {0x40c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_CTL", "", { { BITS_EOT } }}, - {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", { + {0x40d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_STATUS", "", { { BITS_EOT } }}, - {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", { + {0x40e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_ADDR", "", { { BITS_EOT } }}, - {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", { + {0x40f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC3_MISC", "", { { BITS_EOT } }}, - {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { + {0x410, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_CTL", "", { { BITS_EOT } }}, - {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { + {0x411, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_STATUS", "", { { BITS_EOT } }}, - {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { + {0x412, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_ADDR", "", { { BITS_EOT } }}, - {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", { + {0x413, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MC4_MISC", "", { { BITS_EOT } }}, - {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PINBASED_CTLS", "", { + {0x481, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_PINBASED_CTLS", "", { { BITS_EOT } }}, - {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS", "", { + {0x482, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS", "", { { BITS_EOT } }}, - {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", { + {0x483, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_EXIT_CTLS", "", { { BITS_EOT } }}, - {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", { + {0x484, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_ENTRY_CTLS", "", { { BITS_EOT } }}, - {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", { + {0x485, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_MISC", "", { { BITS_EOT } }}, - {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", { + {0x487, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_CR0_FIXED1", "", { { BITS_EOT } }}, - {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", { + {0x489, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_CR4_FIXED1", "", { { BITS_EOT } }}, - {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", { + {0x48b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_VMX_PROCBASED_CTLS2", "", { { BITS_EOT } }}, - {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", { + {0x600, MSRTYPE_RDWR, MSR2(0, 0), "IA32_DS_AREA", "", { { BITS_EOT } }}, - {0x680, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", { + {0x680, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_FROM_IP", "", { { BITS_EOT } }}, - {0x682, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", { + {0x682, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_FROM_IP", "", { { BITS_EOT } }}, - {0x684, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_FROM_IP", "", { + {0x684, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_FROM_IP", "", { { BITS_EOT } }}, - {0x686, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_FROM_IP", "", { + {0x686, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_FROM_IP", "", { { BITS_EOT } }}, - {0x688, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_FROM_IP", "", { + {0x688, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_FROM_IP", "", { { BITS_EOT } }}, - {0x68a, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_FROM_IP", "", { + {0x68a, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_FROM_IP", "", { { BITS_EOT } }}, - {0x68c, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_FROM_IP", "", { + {0x68c, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_FROM_IP", "", { { BITS_EOT } }}, - {0x68e, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_FROM_IP", "", { + {0x68e, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_FROM_IP", "", { { BITS_EOT } }}, - {0x6c0, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_IP", "", { + {0x6c0, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_0_TO_IP", "", { { BITS_EOT } }}, - {0x6c2, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_IP", "", { + {0x6c2, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_2_TO_IP", "", { { BITS_EOT } }}, - {0x6c4, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_4_TO_IP", "", { + {0x6c4, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_4_TO_IP", "", { { BITS_EOT } }}, - {0x6c6, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_6_TO_IP", "", { + {0x6c6, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_6_TO_IP", "", { { BITS_EOT } }}, - {0x6c8, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_8_TO_IP", "", { + {0x6c8, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_8_TO_IP", "", { { BITS_EOT } }}, - {0x6ca, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_10_TO_IP", "", { + {0x6ca, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_10_TO_IP", "", { { BITS_EOT } }}, - {0x6cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_12_TO_IP", "", { + {0x6cc, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_12_TO_IP", "", { { BITS_EOT } }}, - {0x6ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_14_TO_IP", "", { + {0x6ce, MSRTYPE_RDWR, MSR2(0, 0), "MSR_LASTBRANCH_14_TO_IP", "", { { BITS_EOT } }}, { MSR_EOT } diff --git a/util/msrtool/via_c7.c b/util/msrtool/via_c7.c index 323c1d2be8..07ed1756e7 100644 --- a/util/msrtool/via_c7.c +++ b/util/msrtool/via_c7.c @@ -26,23 +26,23 @@ int via_c7_probe(const struct targetdef *target, const struct cpuid_t *id) { } const struct msrdef via_c7_msrs[] = { - {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { + {0x10, MSRTYPE_RDWR, MSR2(0, 0), "IA32_TIME_STAMP_COUNTER", "", { { BITS_EOT } }}, - {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { + {0x2a, MSRTYPE_RDWR, MSR2(0, 0), "EBL_CR_POWERON", "", { { BITS_EOT } }}, - {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { + {0xc1, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR0", "", { { BITS_EOT } }}, - {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { + {0xc2, MSRTYPE_RDWR, MSR2(0, 0), "PERFCTR1", "", { { BITS_EOT } }}, - {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { + {0x11e, MSRTYPE_RDWR, MSR2(0, 0), "BBL_CR_CTL3", "", { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", + {0x186, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL0", "Performance Event Select Register 0", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -102,7 +102,7 @@ const struct msrdef via_c7_msrs[] = { { BITS_EOT } }}, /* if CPUID.0AH: EAX[15:8] > 0 */ - {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", + {0x187, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERFEVTSEL1", "Performance Event Select Register 1", { { 63, 32, RESERVED }, { 31, 8, "CMASK", "R/W", PRESENT_HEX, { @@ -161,7 +161,7 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { + {0x198, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_STATUS", "", { { 63, 8, "Lowest Supported Clock Ratio", "R/O", PRESENT_HEX, { { BITVAL_EOT } }}, @@ -201,7 +201,7 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", { + {0x199, MSRTYPE_RDWR, MSR2(0, 0), "IA32_PERF_CTL", "", { { 63, 48, RESERVED }, { 15, 8, "Desired Clock Ratio", "R/W", PRESENT_HEX, { { BITVAL_EOT } @@ -211,7 +211,7 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { + {0x19a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_CLOCK_MODULATION", "", { { 63, 59, RESERVED }, { 15, 8, "allows selection of the on-demand clock modulation duty cycle", "R/W", PRESENT_BIN, { { MSR1(0), "Reserved" }, @@ -227,7 +227,7 @@ const struct msrdef via_c7_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", { + {0x19b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_INTERRUPT", "", { { 63, 62, RESERVED }, { 1, 1, "Enables APIC LVT interrupt on a low-to-high temp transition", "R/W", PRESENT_BIN, { { BITVAL_EOT } @@ -237,7 +237,7 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", { + {0x19c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_THERM_STATUS", "", { { 63, 62, RESERVED }, { 1, 1, "TCC assert detect", "R/O", PRESENT_BIN, { { MSR1(0), "TCC not asserted" }, @@ -251,7 +251,7 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", { + {0x19d, MSRTYPE_RDWR, MSR2(0, 0), "MSR_THERM2_CTL", "", { { 63, 47, RESERVED }, { 16, 1, "Thermal Monitor enable", "R/W", PRESENT_HEX, { { MSR1(0), "Thermal Monitor 1 enabled" }, @@ -266,7 +266,7 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { + {0x1a0, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MISC_ENABLES", "", { { 63, 43, RESERVED }, { 20, 1, "PowerSaver lock", "R/W", PRESENT_BIN, { { MSR1(0), "Bit 16 can be set and cleared." }, @@ -294,91 +294,91 @@ const struct msrdef via_c7_msrs[] = { { 2, 3, RESERVED }, { BITS_EOT } }}, - {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { + {0x200, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE0", "", { { BITS_EOT } }}, - {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { + {0x201, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK0", "", { { BITS_EOT } }}, - {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { + {0x202, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE1", "", { { BITS_EOT } }}, - {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { + {0x203, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK1", "", { { BITS_EOT } }}, - {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { + {0x204, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE2", "", { { BITS_EOT } }}, - {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { + {0x205, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK2", "", { { BITS_EOT } }}, - {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { + {0x206, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE3", "", { { BITS_EOT } }}, - {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { + {0x207, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK3", "", { { BITS_EOT } }}, - {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { + {0x208, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE4", "", { { BITS_EOT } }}, - {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { + {0x209, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK4", "", { { BITS_EOT } }}, - {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { + {0x20a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE5", "", { { BITS_EOT } }}, - {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { + {0x20b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK5", "", { { BITS_EOT } }}, - {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { + {0x20c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE6", "", { { BITS_EOT } }}, - {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { + {0x20d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK6", "", { { BITS_EOT } }}, - {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { + {0x20e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSBASE7", "", { { BITS_EOT } }}, - {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { + {0x20f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_PHYSMASK7", "", { { BITS_EOT } }}, - {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { + {0x250, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX64K_00000", "", { { BITS_EOT } }}, - {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { + {0x258, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_80000", "", { { BITS_EOT } }}, - {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { + {0x259, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX16K_A0000", "", { { BITS_EOT } }}, - {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { + {0x268, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C0000", "", { { BITS_EOT } }}, - {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { + {0x269, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_C8000", "", { { BITS_EOT } }}, - {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { + {0x26a, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D0000", "", { { BITS_EOT } }}, - {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { + {0x26b, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_D8000", "", { { BITS_EOT } }}, - {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { + {0x26c, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E0000", "", { { BITS_EOT } }}, - {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { + {0x26d, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_E8000", "", { { BITS_EOT } }}, - {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { + {0x26e, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F0000", "", { { BITS_EOT } }}, - {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { + {0x26f, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_FIX4K_F8000", "", { { BITS_EOT } }}, - {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { + {0x2ff, MSRTYPE_RDWR, MSR2(0, 0), "IA32_MTRR_DEF_TYPE", "", { { BITS_EOT } }}, - {0x1107, MSRTYPE_RDWR, MSR2(0,0), "FCR", + {0x1107, MSRTYPE_RDWR, MSR2(0, 0), "FCR", "Feature Control Register", { { 63, 55, RESERVED }, { 8, 1, "Disables L2 Cache", "R/W", PRESENT_BIN, { @@ -395,7 +395,7 @@ const struct msrdef via_c7_msrs[] = { { 0, 1, RESERVED }, { BITS_EOT } }}, - {0x1108, MSRTYPE_RDWR, MSR2(0,0), "FCR2", + {0x1108, MSRTYPE_RDWR, MSR2(0, 0), "FCR2", "Feature Control Register 2", { { 63, 32, "Last 4 characters of Alternate Vendor ID string", "R/W", PRESENT_STR, { { BITVAL_EOT } @@ -416,7 +416,7 @@ const struct msrdef via_c7_msrs[] = { { 3, 4, RESERVED }, { BITS_EOT } }}, - {0x1109, MSRTYPE_WRONLY, MSR2(0,0), "FCR3", + {0x1109, MSRTYPE_WRONLY, MSR2(0, 0), "FCR3", "Feature Control Register 3", { { 63, 32, "First 4 characters of Alternate Vendor ID string", "W/O", PRESENT_STR, { { BITVAL_EOT } @@ -426,10 +426,10 @@ const struct msrdef via_c7_msrs[] = { }}, { BITS_EOT } }}, - {0x1152, MSRTYPE_RDONLY, MSR2(0,0), "FUSES", "Fuses", { + {0x1152, MSRTYPE_RDONLY, MSR2(0, 0), "FUSES", "Fuses", { { BITS_EOT } }}, - {0x1153, MSRTYPE_RDONLY, MSR2(0,0), "BRAND", + {0x1153, MSRTYPE_RDONLY, MSR2(0, 0), "BRAND", "BRAND_1 XOR BRAND_2, (00b = C7-M, 01b = C7, 10b = Eden, 11b = Reserved)", { { 63, 42, RESERVED }, { 21, 2, "BRAND_1", "R/O", PRESENT_BIN, { @@ -441,31 +441,31 @@ const struct msrdef via_c7_msrs[] = { { 17, 18, RESERVED }, { BITS_EOT } }}, - {0x1160, MSRTYPE_RDWR, MSR2(0,0), "UNK0", "", { + {0x1160, MSRTYPE_RDWR, MSR2(0, 0), "UNK0", "", { { BITS_EOT } }}, - {0x1161, MSRTYPE_RDWR, MSR2(0,0), "UNK1", "", { + {0x1161, MSRTYPE_RDWR, MSR2(0, 0), "UNK1", "", { { BITS_EOT } }}, - {0x1164, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_LOW", "(FUSES[6:4] * 5 + 65)", { + {0x1164, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_LOW", "(FUSES[6:4] * 5 + 65)", { { BITS_EOT } }}, - {0x1165, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_HI", "(FUSES[6:4] * 5 + 65) + 5", { + {0x1165, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_HI", "(FUSES[6:4] * 5 + 65) + 5", { { BITS_EOT } }}, - {0x1166, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_OVERSTRESS", "", { + {0x1166, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_OVERSTRESS", "", { { BITS_EOT } }}, - {0x1167, MSRTYPE_RDWR, MSR2(0,0), "THERM_THRESH_USER_TRIP", "", { + {0x1167, MSRTYPE_RDWR, MSR2(0, 0), "THERM_THRESH_USER_TRIP", "", { { BITS_EOT } }}, - {0x1168, MSRTYPE_RDWR, MSR2(0,0), "UNK2", "", { + {0x1168, MSRTYPE_RDWR, MSR2(0, 0), "UNK2", "", { { BITS_EOT } }}, - {0x116a, MSRTYPE_RDWR, MSR2(0,0), "UNK3", "", { + {0x116a, MSRTYPE_RDWR, MSR2(0, 0), "UNK3", "", { { BITS_EOT } }}, - {0x116b, MSRTYPE_RDWR, MSR2(0,0), "UNK4", "", { + {0x116b, MSRTYPE_RDWR, MSR2(0, 0), "UNK4", "", { { BITS_EOT } }}, { MSR_EOT } From 94545910e63bf23707e31b9812c632a217b8898d Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 27 Jan 2020 15:57:46 +0100 Subject: [PATCH 032/151] Documentation/vendorcode/eltan: Update security document Update the security document to reflect the current state of the coreboot implementation. Add more detail and document the change to the public vboot API. BUG=N/A TEST=build Change-Id: I228d0faae0efde70039680a981fea9a436d2384f Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38591 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/vendorcode/eltan/security.md | 119 +++++++++++++++++---- 1 file changed, 96 insertions(+), 23 deletions(-) diff --git a/Documentation/vendorcode/eltan/security.md b/Documentation/vendorcode/eltan/security.md index 04537df23c..9dd47c03f9 100644 --- a/Documentation/vendorcode/eltan/security.md +++ b/Documentation/vendorcode/eltan/security.md @@ -1,38 +1,111 @@ # Eltan Security -## Security This code enables measured boot and verified boot support. -Verified boot is available in coreboot, but based on ChromeOS. This vendorcode -uses a small encryption library and leave much more space in flash for the -payload. +Verified boot is available in coreboot, but based on ChromeOS. This vendorcode security +solution is intended to be used for system without ChromeOS support. + +This solution allows implementing verified boot support for systems that do not contain a TPM. ## Hashing Library -The library suppports SHA-1, SHA-256 and SHA-512. The required routines of -`3rdparty/vboot/firmware/2lib` are used. +The API functions of `3rdparty/vboot/firmware` are used. ## Measured boot -measured boot support will use TPM2 device if available. The items specified -in `mb_log_list[]` will be measured. +Measured boot support requires a TPM2 device. + +The items specified in `mb_log_list[]` and `*_verify_list[]` will be measured. + +The `mb_log_list[]` should only contain items that are not contained in one of the verify_lists +below (except for the `bootblock_verify_list[]`). + +The list can contain the following items: `config`, `revision`, `cmos_layout.bin`. +`oemmanifest.bin` should be added to the list when Verified boot is enabled. ## Verified boot -verified boot support will use TPM2 device if available. The items specified -in the next table will be verified: -* `bootblock_verify_list[]` -* `verify_item_t romstage_verify_list[]` -* `ram_stage_additional_list[]` -* `ramstage_verify_list[]` -* `payload_verify_list[]` -* `oprom_verify_list[]` +Verified boot support will use the OEM manifest to verify the items. + +The verification process is controlled using the following verify lists: +* `bootblock_verify_list[]` (will not be measured, verified in bootblock) +* `romstage_verify_list[]` (verified in early romstage) +* `postcar_verify_list[]` (verified in just before postcar loading) +* `ramstage_verify_list[]` (verified in just before ramstage loading) +* `payload_verify_list[]` (verified in just before payload loading) +* `oprom_verify_list[]` (verified before option rom execution) + +A verify_list entry contains a `related_items` member. This can point to an additional `verify_list` +which will be verified before the specified item is verified. As an example the `grub` entry in +`payload_verify_list[]` can point to the `grub_additional_list[]` that contains the items used by +the grub payload and the `seabios` entry in `payload_verify_list[]` can point to the +`seabios_additional_list[]` that contains the items used by the seabios payload. By doing this the +entries that are verified (and measured) depend on the payload selected at runtime. + +## Creating private and public keys +Create private key in RSA2048 format: `openssl genrsa -F4 -out 2048` + +Create public key using private key: +`futility --vb1 create ` + +The public key will be included into coreboot and used for verified boot only. ## Enabling support +To enable measured boot support: +* Enabled *VENDORCODE_ELTAN_MBOOT* +* Create `mb_log_list` table with list of items to measure -* Measured boot can be enabled using **CONFIG_MBOOT** -* Create mb_log_list table with list of item to measure -* Create tables bootblock_verify_list[], verify_item_t romstage_verify_list[], - ram_stage_additional_list[], ramstage_verify_list[], payload_verify_list[], - oprom_verify_list[] -* Verified boot can be enabled using **CONFIG_VERIFIED_BOOT** -* Added Kconfig values for verbose console output +To enable verified boot support: +* Enable *VENDORCODE_ELTAN_VBOOT* +* Create the verify lists `*_verify_list[]` +* *VENDORCODE_ELTAN_VBOOT_KEY_FILE* must point to location of the public key file created with `futility` + +## Creating signed binary + +During build of coreboot binary an empty `oemmanifest.bin` is added to the binary. + +This binary must be replaced by a correct (signed) binary when *VENDORCODE_ELTAN_VBOOT* is enabled + +The `oemmanifest.bin` file contains the SHA-256 (or SHA-512) hashes of all the different parts +contained in verify_lists. + +When *VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST* is enabled the manifest should be signed and the +signature should appended to the manifest. + +Please make sure the public key is in the RO part of the coreboot image. The `oemmanifest.bin` file +should be in the RW part of the coreboot image. + +### Hashing + +The `oemmanifest.bin` file contains the hashes of different binaries parts of the binary e.g.: +bootblock, romstage, postcar, ramstage, fsp etc. + +The total number of items must match `VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS`. + +For every part the SHA (SHA-256) must be calculated. First extract the binary from the coreboot +image using: `cbfstool extract -n -f ` +followed by: `openssl dgst -sha256 -binary -out ` + +Replace -sha256 with -sha512 when `VENDORCODE_ELTAN_VBOOT_USE_SHA512` is enabled. + +All the hashes must be combined to a hash binary. The hashes need to be placed in the same order as +defined by the `HASH_IDX_XXX` values. + +### Signing + +The oemmanifest needs to be signed when `VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST` is enabled. + +This can be done with the following command: +`openssl dgst -sign -sha256 -out ` + +The signed manifest can be created by adding the signature to the manifest: +`cat >hash_table.bin` + +## Create binary +The `oemmanifest.bin` file must be replaced in the coreboot binary by the generated +`hash_table.bin`. + +To replace the binary: Remove using: +`cbfstool remove -n oemmanifest.bin` +Then add the new image using: +`cbfstool coreboot.bin add -f -n oemmanifest.bin -t raw \` +`-b ` ## Debugging From 34ca460af3237c8eb7699e2336b346a2da9718fe Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 30 Jan 2020 13:10:33 +0100 Subject: [PATCH 033/151] src/superio/*: Fix typos Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find src/superio -name '*.[ch]') Change-Id: I36fd8cfeffdaf81d7ac646bab7ffac3e36c77879 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38652 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/superio/fintek/f81866d/f81866d_hwm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/fintek/f81866d/f81866d_hwm.c b/src/superio/fintek/f81866d/f81866d_hwm.c index 515bc41200..e6333f5818 100644 --- a/src/superio/fintek/f81866d/f81866d_hwm.c +++ b/src/superio/fintek/f81866d/f81866d_hwm.c @@ -26,7 +26,7 @@ #define HWM_FAN_MODE 0x96 #define HWM_FAN2_TEMP_MAP_SEL 0xBF -// Fan 2 - 4 Boundries +// Fan 2 - 4 Boundaries #define HWM_FAN2_BOUND1 0xB6 #define HWM_FAN2_BOUND2 0xB7 #define HWM_FAN2_BOUND3 0xB8 @@ -66,7 +66,7 @@ void f81866d_hwm_init(struct device *dev) /* Select FAN Mode*/ pnp_write_index(port, HWM_FAN_MODE, reg->hwm_fan_mode); - /* Set Boundries */ + /* Set Boundaries */ pnp_write_index(port, HWM_FAN2_BOUND1, reg->hwm_fan2_bound1); pnp_write_index(port, HWM_FAN2_BOUND2, reg->hwm_fan2_bound2); pnp_write_index(port, HWM_FAN2_BOUND3, reg->hwm_fan2_bound3); From 220c2092ae12935a101746a8e42f48dae5ecf0cc Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 30 Jan 2020 12:58:08 +0100 Subject: [PATCH 034/151] util/*: more typo fixes Found by: util/lint/checkpatch.pl --types TYPO_SPELLING --fix-inplace --strict --terse -f $(find util -name '*.[ch]') Change-Id: I059071fd3a2edb41c72fc57fccbb520bd2ebb757 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38651 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- util/cbfstool/elf.h | 6 +++--- util/cbfstool/flashmap/fmap.h | 2 +- util/cbmem/cbmem.c | 2 +- util/marvell/doimage_mv/doimage.c | 2 +- util/nvramtool/accessors/layout-text.c | 2 +- util/nvramtool/cbfs.h | 2 +- util/pgtblgen/pgtblgen.c | 2 +- util/superiotool/ite.c | 4 ++-- 8 files changed, 11 insertions(+), 11 deletions(-) diff --git a/util/cbfstool/elf.h b/util/cbfstool/elf.h index 43fd7f33eb..11cee4f6f8 100644 --- a/util/cbfstool/elf.h +++ b/util/cbfstool/elf.h @@ -318,7 +318,7 @@ typedef struct #define SHT_FINI_ARRAY 15 /* Array of destructors */ #define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ #define SHT_GROUP 17 /* Section group */ -#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ +#define SHT_SYMTAB_SHNDX 18 /* Extended section indices */ #define SHT_NUM 19 /* Number of defined types. */ #define SHT_LOOS 0x60000000 /* Start OS-specific. */ #define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ @@ -1697,9 +1697,9 @@ typedef Elf32_Addr Elf32_Conflict; #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -/* Additional section indeces. */ +/* Additional section indices. */ -#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared +#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tentatively declared symbols in ANSI C. */ #define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ diff --git a/util/cbfstool/flashmap/fmap.h b/util/cbfstool/flashmap/fmap.h index e360011328..7f147ce3e9 100644 --- a/util/cbfstool/flashmap/fmap.h +++ b/util/cbfstool/flashmap/fmap.h @@ -91,7 +91,7 @@ extern long int fmap_find(const uint8_t *image, unsigned int len); * * @map: raw map data * - * returns 0 to indiciate success + * returns 0 to indicate success * returns <0 to indicate failure */ extern int fmap_print(const struct fmap *map); diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index ca6a2f4a48..f8da7daa7e 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -258,7 +258,7 @@ static int find_cbmem_entry(uint32_t id, uint64_t *addr, size_t *size) * passed in memory offset. Could be called recursively in case a forwarding * entry is found. * - * Returns pointer to a memory buffer containg the timestamp table or zero if + * Returns pointer to a memory buffer containing the timestamp table or zero if * none found. */ diff --git a/util/marvell/doimage_mv/doimage.c b/util/marvell/doimage_mv/doimage.c index 18675aa56d..5ead1f8950 100644 --- a/util/marvell/doimage_mv/doimage.c +++ b/util/marvell/doimage_mv/doimage.c @@ -589,7 +589,7 @@ int build_headers(USER_OPTIONS *opt, char *buf_in) For NAND it should be aligned to 512 bytes boundary (for ECC) The image immediately follows the header block, - so if the source addess is undefined, it should be + so if the source address is undefined, it should be derived from the header size. The headers size is always alighed to 4 byte boundary */ diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index 9567b7f53d..7bcfb93d91 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -536,7 +536,7 @@ static int process_enum(FILE * f, int skip_add) /**************************************************************************** * process_checksum_info * - * Get line conatining CMOS checksum information. + * Get line containing CMOS checksum information. ****************************************************************************/ static void process_checksum_info(FILE * f) { diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h index b384ae9eac..47c9ad8d3d 100644 --- a/util/nvramtool/cbfs.h +++ b/util/nvramtool/cbfs.h @@ -53,7 +53,7 @@ typedef uint16_t u16; typedef uint8_t u8; /** These are standard values for the known compression - alogrithms that coreboot knows about for stages and + algorithms that coreboot knows about for stages and payloads. Of course, other CBFS users can use whatever values they want, as long as they understand them. */ diff --git a/util/pgtblgen/pgtblgen.c b/util/pgtblgen/pgtblgen.c index 3a41a90793..234fd72a0e 100644 --- a/util/pgtblgen/pgtblgen.c +++ b/util/pgtblgen/pgtblgen.c @@ -26,7 +26,7 @@ static void usage(char *argv[]) { printf("usage: %s -b -a -o \n", argv[0]); - printf(" -a\t architecure. Supported: x86_64\n"); + printf(" -a\t architecture. Supported: x86_64\n"); printf(" -b\t base address\n"); printf(" -o\t the file to write to\n"); printf(" -h\t show this help text\n"); diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 4e82845b39..81ab024d59 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -99,7 +99,7 @@ static const struct superio_registers reg_table[] = { {NOLDN, "Chip Version", {0x22,EOT}, {0x21,EOT}}, - {NOLDN, "Super I/O Control Reigster (SIOCTRL)", + {NOLDN, "Super I/O Control Register (SIOCTRL)", {0x23,EOT}, {0x01,EOT}}, {NOLDN, "Super I/O Configuration Register (SIOIRQ)", @@ -227,7 +227,7 @@ static const struct superio_registers reg_table[] = { {NOLDN, "Chip Version", {0x22,EOT}, {0x63,EOT}}, - {NOLDN, "Super I/O Control Reigster (SIOCTRL)", + {NOLDN, "Super I/O Control Register (SIOCTRL)", {0x23,EOT}, {0x01,EOT}}, {NOLDN, "Super I/O Configuration Register (SIOIRQ)", From b729d8b6e3e3773a2d2b848a5008ad531a066504 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 23 Jan 2020 18:59:20 +0100 Subject: [PATCH 035/151] util/lint: enforce SPDX license headers in src/superio Change-Id: Iae8d4f0470f75b47e53c50790f06902acb9a24cc Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- util/lint/lint-stable-000-license-headers | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/lint/lint-stable-000-license-headers b/util/lint/lint-stable-000-license-headers index fcaf32ced2..99622cc267 100755 --- a/util/lint/lint-stable-000-license-headers +++ b/util/lint/lint-stable-000-license-headers @@ -6,11 +6,12 @@ # Directories requiring SPDX Identifiers only util/lint/lint-000-license-headers "src/acpi" SPDX_ONLY +util/lint/lint-000-license-headers "src/superio" SPDX_ONLY # Top level util/lint/lint-000-license-headers "src/arch src/commonlib src/console \ src/cpu src/device src/ec src/mainboard src/northbridge src/soc \ - src/southbridge src/superio" + src/southbridge" # src/drivers util/lint/lint-000-license-headers "src/drivers/ams src/drivers/aspeed src/drivers/dec src/drivers/elog \ From dafd514d306d226e7157ac633f97f7c50923814a Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Mon, 30 Dec 2019 09:58:47 -0800 Subject: [PATCH 036/151] soc/intel/common/systemagent: Add Kconfig guard Looks like selecting SOC_INTEL_COMMON force-sets MMCONF_BASE_ADDR to some value which can't be overriden outside of soc/intel/common. So adding a non-SoC platform thats uses code from soc/intel/common is not possible. TEST=build test on wip platform Change-Id: Ia160444e8ac7cac55153f659f4d98f4f77f0d467 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/38639 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: David Guckian --- src/soc/intel/common/block/systemagent/Kconfig | 4 ++++ src/soc/intel/denverton_ns/Kconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index 1222573201..6dd1f3b363 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -3,6 +3,8 @@ config SOC_INTEL_COMMON_BLOCK_SA help Intel Processor common System Agent support +if SOC_INTEL_COMMON_BLOCK_SA + config MMCONF_BASE_ADDRESS hex default 0xe0000000 @@ -36,3 +38,5 @@ config SA_ENABLE_DPR default n help This option allows you to add the DMA Protected Range (DPR). + +endif diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index fa49eb0d9a..aed2beb3fd 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -54,6 +54,10 @@ config CPU_SPECIFIC_OPTIONS select UDK_2015_BINDING select CPU_INTEL_FIRMWARE_INTERFACE_TABLE +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + config FSP_T_ADDR hex "Intel FSP-T (temp ram init) binary location" depends on ADD_FSP_BINARIES && FSP_CAR From 5c0ef702445520e6df74f4c940163dfb8035b64b Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 10:56:46 -0700 Subject: [PATCH 037/151] soc/amd/stoneyridge: use SMBus speed in compilation unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I426fe078909a9b725c1747380d69af31292b6d1e Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38611 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/include/soc/smbus.h | 2 -- src/soc/amd/stoneyridge/southbridge.c | 5 ++++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index 391084d807..4638fcdd83 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -19,8 +19,6 @@ #include #include -#define SMB_SPEED_400KHZ (66000000 / (400000 * 4)) - /* * Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 1b2afec3f1..b0aaf241cd 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -378,8 +378,11 @@ static void setup_misc(int *reboot) static void fch_smbus_init(void) { + /* 400 kHz smbus speed. */ + const uint8_t smbus_speed = (66000000 / (400000 * 4)); + pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); + smbus_write8(SMBTIMING, smbus_speed); /* Clear all SMBUS status bits */ smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); From 1278728fbcee7849bf646e396611426679030c60 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 11:00:09 -0700 Subject: [PATCH 038/151] soc/amd/stoneyridge: use SMBus timeout in compilation unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I7537549da90d0bc158e638c533e8e8b0f1e28a7d Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38612 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/include/soc/smbus.h | 6 ------ src/soc/amd/stoneyridge/smbus.c | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h index 4638fcdd83..ada7cfb9a4 100644 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ b/src/soc/amd/stoneyridge/include/soc/smbus.h @@ -19,12 +19,6 @@ #include #include -/* - * Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - int do_smbus_read_byte(u32 mmio, u8 device, u8 address); int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); int do_smbus_recv_byte(u32 mmio, u8 device); diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index 79f09d6b88..f5a9d604ea 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -19,6 +19,12 @@ #include #include +/* + * Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100 * 1000 * 10) + static u8 controller_read8(u32 base, u8 reg) { switch (base) { From 178d644d62866728dcce6ec8c4b8552e61dc4647 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 11:10:23 -0700 Subject: [PATCH 039/151] soc/amd/stoneyridge: move to using smbus_host.h definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ic912b91daf79ecd2c276a383edcda563891cf643 Signed-off-by: Kyösti Mälkki Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38222 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/stoneyridge/include/soc/smbus.h | 27 --------------------- src/soc/amd/stoneyridge/sm.c | 2 +- src/soc/amd/stoneyridge/smbus.c | 22 ++++++++--------- src/soc/amd/stoneyridge/smbus_spd.c | 2 +- src/soc/amd/stoneyridge/southbridge.c | 1 - 5 files changed, 13 insertions(+), 41 deletions(-) delete mode 100644 src/soc/amd/stoneyridge/include/soc/smbus.h diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h deleted file mode 100644 index ada7cfb9a4..0000000000 --- a/src/soc/amd/stoneyridge/include/soc/smbus.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __STONEYRIDGE_SMBUS_H__ -#define __STONEYRIDGE_SMBUS_H__ - -#include -#include - -int do_smbus_read_byte(u32 mmio, u8 device, u8 address); -int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); -int do_smbus_recv_byte(u32 mmio, u8 device); -int do_smbus_send_byte(u32 mmio, u8 device, u8 val); - -#endif /* __STONEYRIDGE_SMBUS_H__ */ diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 2dba0d78df..6ecf1cd998 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -17,10 +17,10 @@ #include #include #include +#include #include #include #include -#include /* * The southbridge enables all USB controllers by default in SMBUS Control. diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c index f5a9d604ea..5474c5cd45 100644 --- a/src/soc/amd/stoneyridge/smbus.c +++ b/src/soc/amd/stoneyridge/smbus.c @@ -15,8 +15,8 @@ #include #include +#include #include -#include #include /* @@ -25,7 +25,7 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -static u8 controller_read8(u32 base, u8 reg) +static u8 controller_read8(uintptr_t base, u8 reg) { switch (base) { case ACPIMMIO_SMBUS_BASE: @@ -33,13 +33,13 @@ static u8 controller_read8(u32 base, u8 reg) case ACPIMMIO_ASF_BASE: return asf_read8(reg); default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", base); } return 0xff; } -static void controller_write8(u32 base, u8 reg, u8 val) +static void controller_write8(uintptr_t base, u8 reg, u8 val) { switch (base) { case ACPIMMIO_SMBUS_BASE: @@ -49,12 +49,12 @@ static void controller_write8(u32 base, u8 reg, u8 val) asf_write8(reg, val); break; default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", base); } } -static int smbus_wait_until_ready(u32 mmio) +static int smbus_wait_until_ready(uintptr_t mmio) { u32 loops; loops = SMBUS_TIMEOUT; @@ -70,7 +70,7 @@ static int smbus_wait_until_ready(u32 mmio) return -2; /* time out */ } -static int smbus_wait_until_done(u32 mmio) +static int smbus_wait_until_done(uintptr_t mmio) { u32 loops; loops = SMBUS_TIMEOUT; @@ -89,7 +89,7 @@ static int smbus_wait_until_done(u32 mmio) return -3; /* timeout */ } -int do_smbus_recv_byte(u32 mmio, u8 device) +int do_smbus_recv_byte(uintptr_t mmio, u8 device) { u8 byte; @@ -114,7 +114,7 @@ int do_smbus_recv_byte(u32 mmio, u8 device) return byte; } -int do_smbus_send_byte(u32 mmio, u8 device, u8 val) +int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val) { u8 byte; @@ -139,7 +139,7 @@ int do_smbus_send_byte(u32 mmio, u8 device, u8 val) return 0; } -int do_smbus_read_byte(u32 mmio, u8 device, u8 address) +int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address) { u8 byte; @@ -167,7 +167,7 @@ int do_smbus_read_byte(u32 mmio, u8 device, u8 address) return byte; } -int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) +int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val) { u8 byte; diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c index e57ecde578..b588579e52 100644 --- a/src/soc/amd/stoneyridge/smbus_spd.c +++ b/src/soc/amd/stoneyridge/smbus_spd.c @@ -17,8 +17,8 @@ #include #include #include +#include #include -#include #include /* diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index b0aaf241cd..7732fc937a 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -28,7 +28,6 @@ #include #include #include -#include #include #include #include From 3bee7df954fd4285f8445c54de90b8a12fdbc9fd Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 10:58:13 -0700 Subject: [PATCH 040/151] soc/amd/picasso: use SMBus speed in compilation unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The fixed bus speed of 400 kHz doesn't need to reside in a header file. Just move the assumption into the code itself. Change-Id: I8bb68607070d0daeae2ad3bcd79f49d5c20048fd Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38613 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/soc/amd/picasso/include/soc/smbus.h | 2 -- src/soc/amd/picasso/southbridge.c | 5 ++++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h index c4bc28fdf2..60b8bfa055 100644 --- a/src/soc/amd/picasso/include/soc/smbus.h +++ b/src/soc/amd/picasso/include/soc/smbus.h @@ -19,8 +19,6 @@ #include #include -#define SMB_SPEED_400KHZ (66000000 / (400000 * 4)) - /* * Between 1-10 seconds, We should never timeout normally * Longer than this is just painful when a timeout condition occurs. diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0dff4bcae3..310d9a2962 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -253,8 +253,11 @@ void sb_read_mode(u32 mode) static void fch_smbus_init(void) { + /* 400 kHz smbus speed. */ + const uint8_t smbus_speed = (66000000 / (400000 * 4)); + pm_write8(SMB_ASF_IO_BASE, SMB_BASE_ADDR >> 8); - smbus_write8(SMBTIMING, SMB_SPEED_400KHZ); + smbus_write8(SMBTIMING, smbus_speed); /* Clear all SMBUS status bits */ smbus_write8(SMBHSTSTAT, SMBHST_STAT_CLEAR); smbus_write8(SMBSLVSTAT, SMBSLV_STAT_CLEAR); From c3488988b8813dd934e4e29c664283a335affc6d Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 11:00:51 -0700 Subject: [PATCH 041/151] soc/amd/picasso: use SMBus timeout in compilation unit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The timeout is fixed and only used in one place. Put the assumption in the compliation unit utilizing the defintion. Change-Id: I93c061e74df6b4265fd1c61fc4669410ebc9554f Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38614 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons --- src/soc/amd/picasso/include/soc/smbus.h | 6 ------ src/soc/amd/picasso/smbus.c | 6 ++++++ 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h index 60b8bfa055..524be7791d 100644 --- a/src/soc/amd/picasso/include/soc/smbus.h +++ b/src/soc/amd/picasso/include/soc/smbus.h @@ -19,12 +19,6 @@ #include #include -/* - * Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - int do_smbus_read_byte(u32 mmio, u8 device, u8 address); int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); int do_smbus_recv_byte(u32 mmio, u8 device); diff --git a/src/soc/amd/picasso/smbus.c b/src/soc/amd/picasso/smbus.c index 79f09d6b88..f5a9d604ea 100644 --- a/src/soc/amd/picasso/smbus.c +++ b/src/soc/amd/picasso/smbus.c @@ -19,6 +19,12 @@ #include #include +/* + * Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100 * 1000 * 10) + static u8 controller_read8(u32 base, u8 reg) { switch (base) { From 7cd39d27700a4ca82179978fa459161a4e61773a Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 11:12:34 -0700 Subject: [PATCH 042/151] soc/amd/picasso: move to using smbus_host.h definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMBus function declarations were duplicated. Use the common ones provided by smbus_host.h. Change-Id: Ia8fec8f58d72690d73f2241e69b3ff05f74943a4 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38615 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/include/soc/smbus.h | 27 ------------------------- src/soc/amd/picasso/sm.c | 2 +- src/soc/amd/picasso/smbus.c | 22 ++++++++++---------- src/soc/amd/picasso/southbridge.c | 1 - 4 files changed, 12 insertions(+), 40 deletions(-) delete mode 100644 src/soc/amd/picasso/include/soc/smbus.h diff --git a/src/soc/amd/picasso/include/soc/smbus.h b/src/soc/amd/picasso/include/soc/smbus.h deleted file mode 100644 index 524be7791d..0000000000 --- a/src/soc/amd/picasso/include/soc/smbus.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __PICASSO_SMBUS_H__ -#define __PICASSO_SMBUS_H__ - -#include -#include - -int do_smbus_read_byte(u32 mmio, u8 device, u8 address); -int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val); -int do_smbus_recv_byte(u32 mmio, u8 device); -int do_smbus_send_byte(u32 mmio, u8 device, u8 val); - -#endif /* __PICASSO_SMBUS_H__ */ diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c index 438909d7cb..f0ba559f3b 100644 --- a/src/soc/amd/picasso/sm.c +++ b/src/soc/amd/picasso/sm.c @@ -18,10 +18,10 @@ #include #include #include +#include #include #include #include -#include /* * The southbridge enables all USB controllers by default in SMBUS Control. diff --git a/src/soc/amd/picasso/smbus.c b/src/soc/amd/picasso/smbus.c index f5a9d604ea..5474c5cd45 100644 --- a/src/soc/amd/picasso/smbus.c +++ b/src/soc/amd/picasso/smbus.c @@ -15,8 +15,8 @@ #include #include +#include #include -#include #include /* @@ -25,7 +25,7 @@ */ #define SMBUS_TIMEOUT (100 * 1000 * 10) -static u8 controller_read8(u32 base, u8 reg) +static u8 controller_read8(uintptr_t base, u8 reg) { switch (base) { case ACPIMMIO_SMBUS_BASE: @@ -33,13 +33,13 @@ static u8 controller_read8(u32 base, u8 reg) case ACPIMMIO_ASF_BASE: return asf_read8(reg); default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%x\n", + printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", base); } return 0xff; } -static void controller_write8(u32 base, u8 reg, u8 val) +static void controller_write8(uintptr_t base, u8 reg, u8 val) { switch (base) { case ACPIMMIO_SMBUS_BASE: @@ -49,12 +49,12 @@ static void controller_write8(u32 base, u8 reg, u8 val) asf_write8(reg, val); break; default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%x\n", + printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", base); } } -static int smbus_wait_until_ready(u32 mmio) +static int smbus_wait_until_ready(uintptr_t mmio) { u32 loops; loops = SMBUS_TIMEOUT; @@ -70,7 +70,7 @@ static int smbus_wait_until_ready(u32 mmio) return -2; /* time out */ } -static int smbus_wait_until_done(u32 mmio) +static int smbus_wait_until_done(uintptr_t mmio) { u32 loops; loops = SMBUS_TIMEOUT; @@ -89,7 +89,7 @@ static int smbus_wait_until_done(u32 mmio) return -3; /* timeout */ } -int do_smbus_recv_byte(u32 mmio, u8 device) +int do_smbus_recv_byte(uintptr_t mmio, u8 device) { u8 byte; @@ -114,7 +114,7 @@ int do_smbus_recv_byte(u32 mmio, u8 device) return byte; } -int do_smbus_send_byte(u32 mmio, u8 device, u8 val) +int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val) { u8 byte; @@ -139,7 +139,7 @@ int do_smbus_send_byte(u32 mmio, u8 device, u8 val) return 0; } -int do_smbus_read_byte(u32 mmio, u8 device, u8 address) +int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address) { u8 byte; @@ -167,7 +167,7 @@ int do_smbus_read_byte(u32 mmio, u8 device, u8 address) return byte; } -int do_smbus_write_byte(u32 mmio, u8 device, u8 address, u8 val) +int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val) { u8 byte; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 310d9a2962..56fe88de3c 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include #include From d6900a96e09726246e1747762241216e28ba5f16 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 29 Jan 2020 11:34:44 -0800 Subject: [PATCH 043/151] cbfstool: Set deprecated _BSD_SOURCE and _SVID_SOURCE macros In glibc feature control macros, _DEFAULT_SOURCE is the shorthand to tell glibc to enable "all the default stuff", meaning POSIX, BSD and System V interfaces. However, this macro is somewhat recent and older glibc versions (e.g. 2.12) are still occasionally in use that don't recognize it yet. For the benefits of users with these versions, let's also enable the deprecated _BSD_SOURCE and _SVID_SOURCE macros which essentially achieve the same thing. We must continue to define _DEFAULT_SOURCE so that newer glibc versions don't throw a deprecation warning. This patch should make BSD-style byteswap macros like le32toh() available on these older glibc versions. Change-Id: I019bbcf738a1bcdccd7b299bdde29cd4d4ded134 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38638 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- util/cbfstool/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index d8ad959f0d..356b295f4a 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -109,6 +109,7 @@ TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings TOOLCFLAGS += -O2 TOOLCPPFLAGS ?= -D_DEFAULT_SOURCE # memccpy() from string.h +TOOLCPPFLAGS += -D_BSD_SOURCE -D_SVID_SOURCE # _DEFAULT_SOURCE for older glibc TOOLCPPFLAGS += -D_XOPEN_SOURCE=700 # strdup() from string.h TOOLCPPFLAGS += -I$(top)/util/cbfstool/flashmap TOOLCPPFLAGS += -I$(top)/util/cbfstool From 24d0ed79785c07fcea7bb55b8e1cf1ca08f54cfe Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 30 Jan 2020 19:52:23 +0100 Subject: [PATCH 044/151] device/pnp_device: improve warning/error messages Explicitly state that the assignment is missing in the devicetree. In the case of the warnings, the missing assignments might not be an issue. Change-Id: Ic0b2f19496c8b4cd6340b0b8a8d0155f8ad05a43 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38655 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/device/pnp_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 81aa8890b2..dc921e777e 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -129,12 +129,12 @@ static void pnp_set_resource(struct device *dev, struct resource *resource) (resource->index != PNP_IDX_IRQ0) && (resource->index != PNP_IDX_IRQ1)) printk(BIOS_WARNING, "WARNING: %s %02lx %s size: " - "0x%010llx not assigned\n", dev_path(dev), + "0x%010llx not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); else printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010llx " - "not assigned\n", dev_path(dev), resource->index, + "not assigned in devicetree\n", dev_path(dev), resource->index, resource_type(resource), resource->size); return; } From a017e5fb3dda5ea6bbc94ee15b2e981eeaa2d918 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 18 Nov 2019 14:10:35 +0530 Subject: [PATCH 045/151] mb/google/hatch: Override CPU flex ratio This patch overrides CPU flex ratio on hatch in order to get better boot time numbers in vboot_reference. BUG=b:142264107 TEST=Able to save ~100ms of platform boot time while running with lower cpu flex ratio (i.e. freq ~1500MHz) Without this CL 1100:finished vboot kernel verification 802,443 (148,108) With this CL 1100:finished vboot kernel verification 685,382 (46,496) Change-Id: Idd1d1c0c04b1f742f17227a1335f27a956ee940d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/36865 Reviewed-by: V Sowmya Reviewed-by: Tim Wawrzynczak Reviewed-by: Pratikkumar V Prajapati Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index b4d7afd42d..e0291bbd3f 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -194,6 +194,9 @@ chip soc/intel/cannonlake register "gpio_pm[COMM_3]" = "0" register "gpio_pm[COMM_4]" = "0" + # CPU Ratio Override + register "cpu_ratio_override" = "15" + # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required # format: From 99035650aaf4efe579cab0a6dd4aac2b0288f874 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sun, 26 Jan 2020 01:02:00 +0100 Subject: [PATCH 046/151] nb/intel/sandybridge: improve indexed register helper macros Replace the multiplications with corresponding shifts, so that it's easier to see at which bit offsets the values get assigned. Change-Id: I0b0d5172394ff65edfe57bdad474631938e58872 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/38577 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/northbridge/intel/sandybridge/sandybridge.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index f5c1e415c7..ffc1d9f7fa 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -128,11 +128,11 @@ enum platform_type { #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* Indexed register helper macros */ -#define Gz(r, z) ((r) + ((z) * 0x100)) -#define Ly(r, y) ((r) + ((y) * 4)) -#define Cx(r, x) ((r) + ((x) * 0x400)) -#define CxLy(r, x, y) ((r) + ((x) * 0x400) + ((y) * 4)) -#define GzLy(r, z, y) ((r) + ((z) * 0x100) + ((y) * 4)) +#define Gz(r, z) ((r) + ((z) << 8)) +#define Ly(r, y) ((r) + ((y) << 2)) +#define Cx(r, x) ((r) + ((x) << 10)) +#define CxLy(r, x, y) ((r) + ((x) << 10) + ((y) << 2)) +#define GzLy(r, z, y) ((r) + ((z) << 8) + ((y) << 2)) /* byte lane training register base addresses */ #define LANEBASE_B0 0x0000 From 02b29b9d01629a87cde707b6c9b6e8eaec0ed93f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Wed, 27 Nov 2019 15:33:21 +0100 Subject: [PATCH 047/151] mb/lenovo/t520: Switch to overridetree Change-Id: If6be9cffe97dcd8f733e3bd5a67a408dd817005a Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37295 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/t520/Kconfig | 4 +- .../t520/{variants/w520 => }/devicetree.cb | 2 +- .../lenovo/t520/variants/t520/devicetree.cb | 180 ------------------ .../lenovo/t520/variants/t520/overridetree.cb | 16 ++ .../lenovo/t520/variants/w520/overridetree.cb | 7 + 5 files changed, 26 insertions(+), 183 deletions(-) rename src/mainboard/lenovo/t520/{variants/w520 => }/devicetree.cb (98%) delete mode 100644 src/mainboard/lenovo/t520/variants/t520/devicetree.cb create mode 100644 src/mainboard/lenovo/t520/variants/t520/overridetree.cb create mode 100644 src/mainboard/lenovo/t520/variants/w520/overridetree.cb diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index a6183d9f08..6d31be2e6c 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -51,9 +51,9 @@ config MAINBOARD_DIR string default "lenovo/t520" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" config FMDFILE string diff --git a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb similarity index 98% rename from src/mainboard/lenovo/t520/variants/w520/devicetree.cb rename to src/mainboard/lenovo/t520/devicetree.cb index 8b2cbe78e4..e28f6cc552 100644 --- a/src/mainboard/lenovo/t520/variants/w520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -90,7 +90,7 @@ chip northbridge/intel/sandybridge end # PCIe Port #4 Express Card device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 on end # PCIe Port #7 USB 3.0 only W520 + device pci 1c.6 off end # PCIe Port #7 device pci 1c.7 off end # PCIe Port #8 device pci 1d.0 on end # USB2 EHCI #1 diff --git a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb b/src/mainboard/lenovo/t520/variants/t520/devicetree.cb deleted file mode 100644 index 0bfa18f4a6..0000000000 --- a/src/mainboard/lenovo/t520/variants/t520/devicetree.cb +++ /dev/null @@ -1,180 +0,0 @@ -chip northbridge/intel/sandybridge - # IGD Displays - register "gfx.ndid" = "3" - register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" - - # Enable DisplayPort Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable Panel as LVDS and configure power delays - register "gpu_panel_port_select" = "0" # LVDS - register "gpu_panel_power_cycle_delay" = "5" - register "gpu_panel_power_up_delay" = "300" # T1+T2: 30ms - register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms - register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms - register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" - register "gpu_cpu_backlight" = "0x1155" - register "gpu_pch_backlight" = "0x06100610" - - device cpu_cluster 0 on - chip cpu/intel/model_206ax - # Magic APIC ID to locate this chip - device lapic 0x0 on end - device lapic 0xacac off end - - register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) - - register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) - register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) - register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) - end - end - - register "pci_mmio_size" = "2048" - - device domain 0 on - subsystemid 0x17aa 0x21cf inherit - - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on - subsystemid 0x17aa 0x21d1 - end # vga controller - - chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - # GPI routing - # 0 No effect (default) - # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) - # 2 SCI (if corresponding GPIO_EN bit is also set) - register "alt_gp_smi_en" = "0x0000" - register "gpi1_routing" = "2" - register "gpi13_routing" = "2" - - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) - register "sata_port_map" = "0x1f" - # Set max SATA speed to 6.0 Gb/s - register "sata_interface_speed_support" = "0x3" - - register "gen1_dec" = "0x7c1601" - register "gen2_dec" = "0x0c15e1" - register "gen4_dec" = "0x0c06a1" - - # Enable zero-based linear PCIe root port functions - register "pcie_port_coalesce" = "1" - - register "c2_latency" = "101" # c2 not supported - - register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" - - register "spi_uvscc" = "0x2005" - register "spi_lvscc" = "0x2005" - - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end - device pci 16.2 off end - device pci 16.3 off end - device pci 19.0 on # Intel Gigabit Ethernet - subsystemid 0x17aa 0x21ce - end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on - smbios_slot_desc "7" "3" "ExpressCard Slot" "8" - end # PCIe Port #4 Express Card - device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 off end # PCIe Port #7 USB 3.0 only W520 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI-2-PCI bridge - - device pci 1f.0 on #LPC bridge - chip ec/lenovo/pmh7 - device pnp ff.1 on end # dummy - register "backlight_enable" = "0x01" - register "dock_event_enable" = "0x01" - end - - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - - chip ec/lenovo/h8 - device pnp ff.2 on # dummy - io 0x60 = 0x62 - io 0x62 = 0x66 - io 0x64 = 0x1600 - io 0x66 = 0x1604 - end - - register "config0" = "0xa7" - register "config1" = "0x09" - register "config2" = "0xa0" - register "config3" = "0xc2" - - register "beepmask0" = "0x00" - register "beepmask1" = "0x86" - register "has_power_management_beeps" = "0" - register "event2_enable" = "0xff" - register "event3_enable" = "0xff" - register "event4_enable" = "0xd0" - register "event5_enable" = "0xfc" - register "event6_enable" = "0x00" - register "event7_enable" = "0x01" - register "event8_enable" = "0x7b" - register "event9_enable" = "0xff" - register "eventa_enable" = "0x01" - register "eventb_enable" = "0x00" - register "eventc_enable" = "0xff" - register "eventd_enable" = "0xff" - register "evente_enable" = "0x0d" - - register "has_bdc_detection" = "1" - register "bdc_gpio_num" = "54" - register "bdc_gpio_lvl" = "0" - - register "has_wwan_detection" = "1" - register "wwan_gpio_num" = "70" - register "wwan_gpio_lvl" = "0" - end - chip drivers/lenovo/hybrid_graphics - device pnp ff.f on end # dummy - - register "detect_gpio" = "21" - - register "has_panel_hybrid_gpio" = "1" - register "panel_hybrid_gpio" = "52" - register "panel_integrated_lvl" = "1" - - register "has_backlight_gpio" = "0" - register "has_dgpu_power_gpio" = "0" - - register "has_thinker1" = "1" - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBUS controller - # eeprom, 8 virtual devices, same chip - chip drivers/i2c/at24rf08c - device i2c 54 on end - device i2c 55 on end - device i2c 56 on end - device i2c 57 on end - device i2c 5c on end - device i2c 5d on end - device i2c 5e on end - device i2c 5f on end - end - end # SMBus - device pci 1f.5 off end # IDE controller - device pci 1f.6 off end # Thermal controller - end - end -end diff --git a/src/mainboard/lenovo/t520/variants/t520/overridetree.cb b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb new file mode 100644 index 0000000000..8016d10991 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/t520/overridetree.cb @@ -0,0 +1,16 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1e.0 off end # PCI-2-PCI bridge + device pci 1f.0 on # LPC bridge + chip ec/lenovo/h8 + register "has_wwan_detection" = "1" + register "wwan_gpio_num" = "70" + register "wwan_gpio_lvl" = "0" + end + end # LPC bridge + device pci 1f.5 off end # IDE controller + device pci 1f.6 off end # Thermal controller + end + end +end diff --git a/src/mainboard/lenovo/t520/variants/w520/overridetree.cb b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb new file mode 100644 index 0000000000..3e1c90ee63 --- /dev/null +++ b/src/mainboard/lenovo/t520/variants/w520/overridetree.cb @@ -0,0 +1,7 @@ +chip northbridge/intel/sandybridge + device domain 0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + device pci 1c.6 on end # PCIe Port #7 USB 3.0 + end + end +end From 60510733ae9c1b08bda51c3d97d42c63c00212b6 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 30 Jan 2020 11:43:14 +0100 Subject: [PATCH 048/151] util/docker/Makefile: Correct help output The help output suggests clean-docker should be used to remove the docker coreboot containers and images. The Makefile actually supports the docker-clean target. Corrected the help output to reflect the actual Makefile target. BUG=N/A TEST=build Change-Id: Ib24f8e1ecdf3bdc31b3f8b484ce7ca0c19b645ee Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38649 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- util/docker/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index 619de854c0..808a1d7ae5 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -193,7 +193,7 @@ help: @echo " doc.coreboot.org - Build doc.coreboot.org container" @echo " clean-coreboot-containers - Remove all docker coreboot containers" @echo " clean-coreboot-images - Remove all docker coreboot images" - @echo " clean-docker - Remove docker coreboot containers & images" + @echo " docker-clean - Remove docker coreboot containers & images" @echo @echo "Commands for using docker images" @echo " docker-build-coreboot - Build coreboot under coreboot-sdk" From 87afa907316faa46250e38d3969139d4fed18d8a Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 22 Jan 2020 15:02:48 -0700 Subject: [PATCH 049/151] ec/google/chromeec: Add new host command, EC_CMD_GET_PD_PORT_CAPS The new host command provides these static capabilities of each USB-PD port: 1) Port number 2) Power role: source, sink, dual 3) Try-power role: none, sink, source 4) Data role: dfp, ufp, dual 5) Port location: these come from power_manager BUG=b:146506369 BRANCH=none TEST=compiles Change-Id: I923e4b637a2f41ce173d378ba5030f1ae8c22222 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/38539 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec_commands.h | 68 ++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h index 86bd4f69ad..7b5a067114 100644 --- a/src/ec/google/chromeec/ec_commands.h +++ b/src/ec/google/chromeec/ec_commands.h @@ -5852,6 +5852,74 @@ struct ec_response_locate_chip { */ #define EC_CMD_REBOOT_AP_ON_G3 0x0127 +/*****************************************************************************/ +/* Get PD port capabilities + * + * Returns the following static *capabilities* of the given port: + * 1) Power role: source, sink, or dual. It is not anticipated that + * future CrOS devices would ever be only a source, so the options are + * sink or dual. + * 2) Try-power role: source, sink, or none (practically speaking, I don't + * believe any CrOS device would support Try.SNK, so this would be source + * or none). + * 3) Data role: dfp, ufp, or dual. This will probably only be DFP or dual + * for CrOS devices. + */ +#define EC_CMD_GET_PD_PORT_CAPS 0x0128 + +enum ec_pd_power_role_caps { + EC_PD_POWER_ROLE_SOURCE = 0, + EC_PD_POWER_ROLE_SINK = 1, + EC_PD_POWER_ROLE_DUAL = 2, +}; + +enum ec_pd_try_power_role_caps { + EC_PD_TRY_POWER_ROLE_NONE = 0, + EC_PD_TRY_POWER_ROLE_SINK = 1, + EC_PD_TRY_POWER_ROLE_SOURCE = 2, +}; + +enum ec_pd_data_role_caps { + EC_PD_DATA_ROLE_DFP = 0, + EC_PD_DATA_ROLE_UFP = 1, + EC_PD_DATA_ROLE_DUAL = 2, +}; + +/* From: power_manager/power_supply_properties.proto */ +enum ec_pd_port_location { + /* The location of the port is unknown, or there's only one port. */ + EC_PD_PORT_LOCATION_UNKNOWN = 0, + + /* + * Various positions on the device. The first word describes the side of + * the device where the port is located while the second clarifies the + * position. For example, LEFT_BACK means the farthest-back port on the + * left side, while BACK_LEFT means the leftmost port on the back of the + * device. + */ + EC_PD_PORT_LOCATION_LEFT = 1, + EC_PD_PORT_LOCATION_RIGHT = 2, + EC_PD_PORT_LOCATION_BACK = 3, + EC_PD_PORT_LOCATION_FRONT = 4, + EC_PD_PORT_LOCATION_LEFT_FRONT = 5, + EC_PD_PORT_LOCATION_LEFT_BACK = 6, + EC_PD_PORT_LOCATION_RIGHT_FRONT = 7, + EC_PD_PORT_LOCATION_RIGHT_BACK = 8, + EC_PD_PORT_LOCATION_BACK_LEFT = 9, + EC_PD_PORT_LOCATION_BACK_RIGHT = 10, +}; + +struct ec_params_get_pd_port_caps { + uint8_t port; /* Which port to interrogate */ +} __ec_align1; + +struct ec_response_get_pd_port_caps { + uint8_t pd_power_role_cap; /* enum ec_pd_power_role_caps */ + uint8_t pd_try_power_role_cap; /* enum ec_pd_try_power_role_caps */ + uint8_t pd_data_role_cap; /* enum ec_pd_data_role_caps */ + uint8_t pd_port_location; /* enum ec_pd_port_location */ +} __ec_align1; + /*****************************************************************************/ /* The command range 0x200-0x2FF is reserved for Rotor. */ From e6078290c5c3fd5a89f548abc5d67b5264745d73 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Wed, 22 Jan 2020 15:22:18 -0700 Subject: [PATCH 050/151] ec/google/chromeec: Add new wrappers for host commands Add new functions to get (from the EC): 1) The number of USB-PD ports 2) The capabilities of each port (EC_CMD_GET_PD_PORT_CAPS) BUG=b:146506369 BRANCH=none TEST=Instrumented calls to these and verified the data Change-Id: I57edbe1592cd28b005f01679ef8a8b5de3e1f586 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/38540 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/ec/google/chromeec/ec.c | 59 +++++++++++++++++++++++++++++++++++-- src/ec/google/chromeec/ec.h | 30 +++++++++++++++++++ 2 files changed, 86 insertions(+), 3 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 0b23034101..4bf41ac119 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -15,16 +15,18 @@ #include #include -#include -#include #include #include #include +#include +#include #include +#include +#include #include #include -#include #include +#include #include #include "chip.h" @@ -1419,6 +1421,57 @@ enum ec_current_image google_chromeec_get_current_image(void) return ec_image_type; } +int google_chromeec_get_num_pd_ports(int *num_ports) +{ + struct ec_response_charge_port_count resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_CHARGE_PORT_COUNT, + .cmd_version = 0, + .cmd_data_out = &resp, + .cmd_size_in = 0, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + *num_ports = resp.port_count; + return 0; +} + +int google_chromeec_get_pd_port_caps(int port, + struct usb_pd_port_caps *port_caps) +{ + struct ec_params_get_pd_port_caps params = { + .port = port, + }; + struct ec_response_get_pd_port_caps resp = {}; + struct chromeec_command cmd = { + .cmd_code = EC_CMD_GET_PD_PORT_CAPS, + .cmd_version = 0, + .cmd_data_in = ¶ms, + .cmd_size_in = sizeof(params), + .cmd_data_out = &resp, + .cmd_size_out = sizeof(resp), + .cmd_dev_index = 0, + }; + int rv; + + rv = google_chromeec_command(&cmd); + if (rv) + return rv; + + port_caps->power_role_cap = resp.pd_power_role_cap; + port_caps->try_power_role_cap = resp.pd_try_power_role_cap; + port_caps->data_role_cap = resp.pd_data_role_cap; + port_caps->port_location = resp.pd_port_location; + + return 0; +} + void google_chromeec_init(void) { google_chromeec_log_uptimeinfo(); diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index d90d24c767..5ce375e00b 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -299,4 +299,34 @@ int google_chromeec_get_protocol_info( */ int google_chromeec_get_cmd_versions(int command, uint32_t *pmask); +/** + * Get number of PD-capable USB ports from EC. + * + * @param *num_ports If successful, num_ports is the number + * of PD-capable USB ports according to the EC. + * @return 0 on success, -1 on error + */ +int google_chromeec_get_num_pd_ports(int *num_ports); + +/* Structure representing the capabilities of a USB-PD port */ +struct usb_pd_port_caps { + enum ec_pd_power_role_caps power_role_cap; + enum ec_pd_try_power_role_caps try_power_role_cap; + enum ec_pd_data_role_caps data_role_cap; + enum ec_pd_port_location port_location; +}; + +/** + * Get role-based capabilities for a USB-PD port + * + * @param port Which port to get information about + * @param *power_role_cap The power-role capabillity of the port + * @param *try_power_role_cap The Try-power-role capability of the port + * @param *data_role_cap The data role capability of the port + * @param *port_location Location of the port on the device + * @return 0 on success, -1 on error + */ +int google_chromeec_get_pd_port_caps(int port, + struct usb_pd_port_caps *port_caps); + #endif /* _EC_GOOGLE_CHROMEEC_EC_H */ From 60a4e952e9df5206d3b5acc7e063057d9bd2aed5 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Thu, 30 Jan 2020 08:33:37 -0700 Subject: [PATCH 051/151] mb/google/hatch: Modify kohaku's EC_SCI_EVENTS mask Remove EC_HOST_EVENT_MKBP from kohaku's EC_SCI_EVENTS mask, so that MKBP events don't generate an SCI. The EC is also being changed to use host events to wake up the system, and use the EC_INT_L line for MKBP IRQ signalling. Otherwise, there would be two IRQs generated for MKBP events. BUG=b:144122000 BRANCH=firmware-hatch-12672.B TEST=System shows ACPI interrupt as the wakeup IRQ, and the MKBP host event is properly processed as well. Change-Id: I9ff964e38e66ccb953a1adad5a936a9da6e4f3a1 Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/38654 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../variants/kohaku/include/variant/ec.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h index a58d41d4c6..377b703cdd 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/ec.h @@ -20,12 +20,29 @@ #define EC_ENABLE_MULTIPLE_DPTF_PROFILES +/* Add EC_HOST_EVENT_MKBP from baseboard */ #undef MAINBOARD_EC_S3_WAKE_EVENTS - #define MAINBOARD_EC_S3_WAKE_EVENTS \ (MAINBOARD_EC_S5_WAKE_EVENTS |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) +/* Removing EC_HOST_EVENT_MKBP from baseboard mask */ +#undef MAINBOARD_EC_SCI_EVENTS +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + #endif /* VARIANT_EC_H */ From a58e5034426f657491550ccc6d6d2423e4cdb45f Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 29 Jan 2020 21:01:27 +0100 Subject: [PATCH 052/151] util/cbfstool/lzma: Make clang-11+'s indentation checker happy Newest clang compilers warn about "misleading indentation", and because warnings-are-errors in our builds, that breaks the build. The lzma code base is vendored in, so we might just have to update it, but that's a bigger effort than just removing a couple of spaces (the coding style of the file is horrible, but I will only change it as much as the compilers ask for). BUG=chromium:1039526 Change-Id: I6b9d7a760380081af996ea5412d7e3e688048bfd Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38637 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel Reviewed-by: Idwer Vollering Reviewed-by: Angel Pons --- util/cbfstool/lzma/C/LzmaEnc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/cbfstool/lzma/C/LzmaEnc.c b/util/cbfstool/lzma/C/LzmaEnc.c index e7d14c59a8..f2a832059a 100644 --- a/util/cbfstool/lzma/C/LzmaEnc.c +++ b/util/cbfstool/lzma/C/LzmaEnc.c @@ -1246,7 +1246,7 @@ static uint32_t GetOptimum(struct CLzmaEnc *p, uint32_t position, uint32_t *back startLen = lenTest + 1; /* if (_maxMode) */ - { + { uint32_t lenTest2 = lenTest + 1; uint32_t limit = lenTest2 + p->numFastuint8_ts; uint32_t nextRepMatchPrice; @@ -1290,7 +1290,7 @@ static uint32_t GetOptimum(struct CLzmaEnc *p, uint32_t position, uint32_t *back } } } - } + } } } /* for (uint32_t lenTest = 2; lenTest <= newLen; lenTest++) */ From 0174ea78bf51fc5f7c6261449835bf621de448b2 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Sat, 4 Jan 2020 15:14:59 +0100 Subject: [PATCH 053/151] util/inteltool: Add GPIO dumping capabilites for Ice Lake U systems MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This GPIO dumping was implemented using the Document Number: 341080-001 Intel® 495 Series Chipset Family On-Package Platform Controller Hub Volume 1 of 2 datasheet. The GPIO community ports can be found in table 36-1, while the community and pin descriptions are taken from linux/pinctrl/intel/pinctrl-icelake.c . This commit was tested on the late 2019 Razer Blade Stealth with 1065G7 and Chipset 495 PCH and the output manually compared against linux/pinctrl-intel. Change-Id: Ib40f1dbae57169678e92ea9ad0df60ff91b5b22c Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/38175 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Alexander Couzens --- util/inteltool/gpio.c | 1 + util/inteltool/gpio_groups.c | 477 +++++++++++++++++++++++++++++++++++ util/inteltool/pcr.c | 1 + 3 files changed, 479 insertions(+) diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index efeab5665f..9610fd6cb3 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1070,6 +1070,7 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs) case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: print_gpio_groups(sb); return 0; case PCI_DEVICE_ID_INTEL_82371XX: diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 321cf97970..4ec79c4c6e 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -2157,6 +2157,477 @@ static const struct gpio_community *const cannonlake_pch_h_communities[] = { &cannonlake_pch_h_community_4, }; +/* Ice Lake-LP */ +static const char *const icelake_pch_h_group_g_names[] = { + /* GPP_G */ + "GPP_G0", "SD3_CMD", + "GPP_G1", "SD3_D0", + "GPP_G2", "SD3_D1", + "GPP_G3", "SD3_D2", + "GPP_G4", "SD3_D3", + "GPP_G5", "SD3_CDB", + "GPP_G6", "SD3_CLK", + "GPP_G7", "SD3_WP", +}; + +static const char *const icelake_pch_h_group_b_names[] = { + /* GPP_B */ + "GPP_B0", "CORE_VID_0", + "GPP_B1", "CORE_VID_1", + "GPP_B2", "VRALERTB", + "GPP_B3", "CPU_GP_2", + "GPP_B4", "CPU_GP_3", + "GPP_B5", "ISH_I2C0_SDA", + "GPP_B6", "ISH_I2C0_SCL", + "GPP_B7", "ISH_I2C1_SDA", + "GPP_B8", "ISH_I2C1_SCL", + "GPP_B9", "I2C5_SDA", + "GPP_B10", "I2C5_SCL", + "GPP_B11", "PMCALERTB", + "GPP_B12", "SLP_S0B", + "GPP_B13", "PLTRSTB", + "GPP_B14", "SPKR", + "GPP_B15", "GSPI0_CS0B", + "GPP_B16", "GSPI0_CLK", + "GPP_B17", "GSPI0_MISO", + "GPP_B18", "GSPI0_MOSI", + "GPP_B19", "GSPI1_CS0B", + "GPP_B20", "GSPI1_CLK", + "GPP_B21", "GSPI1_MISO", + "GPP_B22", "GSPI1_MOSI", + "GPP_B23", "SML1ALERTB", + "GPP_B24", "GSPI0_CLK_LOOPBK", + "GPP_B25", "GSPI1_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_a_names[] = { + /* GPP_A */ + "GPP_A0", "ESPI_IO_0", + "GPP_A1", "ESPI_IO_1", + "GPP_A2", "ESPI_IO_2", + "GPP_A3", "ESPI_IO_3", + "GPP_A4", "ESPI_CSB", + "GPP_A5", "ESPI_CLK", + "GPP_A6", "ESPI_RESETB", + "GPP_A7", "I2S2_SCLK", + "GPP_A8", "I2S2_SFRM", + "GPP_A9", "I2S2_TXD", + "GPP_A10", "I2S2_RXD", + "GPP_A11", "SATA_DEVSLP_2", + "GPP_A12", "SATAXPCIE_1", + "GPP_A13", "SATAXPCIE_2", + "GPP_A14", "USB2_OCB_1", + "GPP_A15", "USB2_OCB_2", + "GPP_A16", "USB2_OCB_3", + "GPP_A17", "DDSP_HPD_C", + "GPP_A18", "DDSP_HPD_B", + "GPP_A19", "DDSP_HPD_1", + "GPP_A20", "DDSP_HPD_2", + "GPP_A21", "I2S5_TXD", + "GPP_A22", "I2S5_RXD", + "GPP_A23", "I2S1_SCLK", + "GPP_A24", "ESPI_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_h_names[] = { + /* GPP_H */ + "GPP_H0", "SD_1P8_SEL", + "GPP_H1", "SD_PWR_EN_B", + "GPP_H2", "GPPC_H_2", + "GPP_H3", "SX_EXIT_HOLDOFFB", + "GPP_H4", "I2C2_SDA", + "GPP_H5", "I2C2_SCL", + "GPP_H6", "I2C3_SDA", + "GPP_H7", "I2C3_SCL", + "GPP_H8", "I2C4_SDA", + "GPP_H9", "I2C4_SCL", + "GPP_H10", "SRCCLKREQB_4", + "GPP_H11", "SRCCLKREQB_5", + "GPP_H12", "M2_SKT2_CFG_0", + "GPP_H13", "M2_SKT2_CFG_1", + "GPP_H14", "M2_SKT2_CFG_2", + "GPP_H15", "M2_SKT2_CFG_3", + "GPP_H16", "DDPB_CTRLCLK", + "GPP_H17", "DDPB_CTRLDATA", + "GPP_H18", "CPU_VCCIO_PWR_GATEB", + "GPP_H19", "TIME_SYNC_0", + "GPP_H20", "IMGCLKOUT_1", + "GPP_H21", "IMGCLKOUT_2", + "GPP_H22", "IMGCLKOUT_3", + "GPP_H23", "IMGCLKOUT_4", +}; + +static const char *const icelake_pch_h_group_d_names[] = { + /* GPP_D */ + "GPP_D0", "ISH_GP_0", + "GPP_D1", "ISH_GP_1", + "GPP_D2", "ISH_GP_2", + "GPP_D3", "ISH_GP_3", + "GPP_D4", "IMGCLKOUT_0", + "GPP_D5", "SRCCLKREQB_0", + "GPP_D6", "SRCCLKREQB_1", + "GPP_D7", "SRCCLKREQB_2", + "GPP_D8", "SRCCLKREQB_3", + "GPP_D9", "ISH_SPI_CSB", + "GPP_D10", "ISH_SPI_CLK", + "GPP_D11", "ISH_SPI_MISO", + "GPP_D12", "ISH_SPI_MOSI", + "GPP_D13", "ISH_UART0_RXD", + "GPP_D14", "ISH_UART0_TXD", + "GPP_D15", "ISH_UART0_RTSB", + "GPP_D16", "ISH_UART0_CTSB", + "GPP_D17", "ISH_GP_4", + "GPP_D18", "ISH_GP_5", + "GPP_D19", "I2S_MCLK", + "GPP_D10", "GSPI2_CLK_LOOPBK", +}; + +static const char *const icelake_pch_h_group_f_names[] = { + /* GPP_F */ + "GPP_F0", "CNV_BRI_DT", + "GPP_F1", "CNV_BRI_RSP", + "GPP_F2", "CNV_RGI_DT", + "GPP_F3", "CNV_RGI_RSP", + "GPP_F4", "CNV_RF_RESET_B", + "GPP_F5", "EMMC_HIP_MON", + "GPP_F6", "CNV_PA_BLANKING", + "GPP_F7", "EMMC_CMD", + "GPP_F8", "EMMC_DATA0", + "GPP_F9", "EMMC_DATA1", + "GPP_F10", "EMMC_DATA2", + "GPP_F11", "EMMC_DATA3", + "GPP_F12", "EMMC_DATA4", + "GPP_F13", "EMMC_DATA5", + "GPP_F14", "EMMC_DATA6", + "GPP_F15", "EMMC_DATA7", + "GPP_F16", "EMMC_RCLK", + "GPP_F17", "EMMC_CLK", + "GPP_F18", "EMMC_RESETB", + "GPP_F19", "A4WP_PRESENT", +}; + +static const char *const icelake_pch_h_group_vgpio_names[] = { + /* vGPIO */ + "CNV_BTEN", "", + "CNV_WCEN", "", + "CNV_BT_HOST_WAKEB", "", + "CNV_BT_IF_SELECT", "", + "vCNV_BT_UART_TXD", "", + "vCNV_BT_UART_RXD", "", + "vCNV_BT_UART_CTS_B", "", + "vCNV_BT_UART_RTS_B", "", + "vCNV_MFUART1_TXD", "", + "vCNV_MFUART1_RXD", "", + "vCNV_MFUART1_CTS_B", "", + "vCNV_MFUART1_RTS_B", "", + "vUART0_TXD", "", + "vUART0_RXD", "", + "vUART0_CTS_B", "", + "vUART0_RTS_B", "", + "vISH_UART0_TXD", "", + "vISH_UART0_RXD", "", + "vISH_UART0_CTS_B", "", + "vISH_UART0_RTS_B", "", + "vCNV_BT_I2S_BCLK", "", + "vCNV_BT_I2S_WS_SYNC", "", + "vCNV_BT_I2S_SDO", "", + "vCNV_BT_I2S_SDI", "", + "vI2S2_SCLK", "", + "vI2S2_SFRM", "", + "vI2S2_TXD", "", + "vI2S2_RXD", "", + "vSD3_CD_B", "", +}; + +static const char *const icelake_pch_h_group_c_names[] = { + /* GPP_C */ + "GPP_C0", "SMBCLK", + "GPP_C1", "SMBDATA", + "GPP_C2", "SMBALERTB", + "GPP_C3", "SML0CLK", + "GPP_C4", "SML0DATA", + "GPP_C5", "SML0ALERTB", + "GPP_C6", "SML1CLK", + "GPP_C7", "SML1DATA", + "GPP_C8", "UART0_RXD", + "GPP_C9", "UART0_TXD", + "GPP_C10", "UART0_RTSB", + "GPP_C11", "UART0_CTSB", + "GPP_C12", "UART1_RXD", + "GPP_C13", "UART1_TXD", + "GPP_C14", "UART1_RTSB", + "GPP_C15", "UART1_CTSB", + "GPP_C16", "I2C0_SDA", + "GPP_C17", "I2C0_SCL", + "GPP_C18", "I2C1_SDA", + "GPP_C19", "I2C1_SCL", + "GPP_C20", "UART2_RXD", + "GPP_C21", "UART2_TXD", + "GPP_C22", "UART2_RTSB", + "GPP_C23", "UART2_CTSB", +}; + +static const char *const icelake_pch_h_group_hvcmos_names[] = { + /* HVCMOS */ + "L_BKLTEN", "", + "L_BKLTCTL", "", + "L_VDDEN", "", + "SYS_PWROK", "", + "SYS_RESETB", "", + "MLK_RSTB", "", +}; + +static const char *const icelake_pch_h_group_e_names[] = { + /* GPP_E */ + "GPP_E0", "SATAXPCIE_0", + "GPP_E1", "SPI1_IO_2", + "GPP_E2", "SPI1_IO_3", + "GPP_E3", "CPU_GP_0", + "GPP_E4", "SATA_DEVSLP_0", + "GPP_E5", "SATA_DEVSLP_1", + "GPP_E6", "GPPC_E_6", + "GPP_E7", "CPU_GP_1", + "GPP_E8", "SATA_LEDB", + "GPP_E9", "USB2_OCB_0", + "GPP_E10", "SPI1_CSB", + "GPP_E11", "SPI1_CLK", + "GPP_E12", "SPI1_MISO_IO_1", + "GPP_E13", "SPI1_MOSI_IO_0", + "GPP_E14", "DDSP_HPD_A", + "GPP_E15", "ISH_GP_6", + "GPP_E16", "ISH_GP_7", + "GPP_E17", "DISP_MISC_4", + "GPP_E18", "DDP1_CTRLCLK", + "GPP_E19", "DDP1_CTRLDATA", + "GPP_E20", "DDP2_CTRLCLK", + "GPP_E21", "DDP2_CTRLDATA", + "GPP_E22", "DDPA_CTRLCLK", + "GPP_E23", "DDPA_CTRLDATA", +}; + +static const char *const icelake_pch_h_group_jtag_names[] = { + /* JTAG */ + "JTAG0", "JTAG_TDO", + "JTAG1", "JTAGX", + "JTAG2", "PRDYB", + "JTAG3", "PREQB", + "JTAG4", "CPU_TRSTB", + "JTAG5", "JTAG_TDI", + "JTAG6", "JTAG_TMS", + "JTAG7", "JTAG_TCK", + "JTAG8", "ITP_PMODE", +}; + +static const char *const icelake_pch_h_group_r_names[] = { + /* GPP_R */ + "GPP_R0", "HDA_BCLK", + "GPP_R1", "HDA_SYNC", + "GPP_R2", "HDA_SDO", + "GPP_R3", "HDA_SDI_0", + "GPP_R4", "HDA_RSTB", + "GPP_R5", "HDA_SDI_1", + "GPP_R6", "I2S1_TXD", + "GPP_R7", "I2S1_RXD", +}; + +static const char *const icelake_pch_h_group_s_names[] = { + /* GPP_S */ + "GPP_S0", "SNDW1_CLK", + "GPP_S1", "SNDW1_DATA", + "GPP_S2", "SNDW2_CLK", + "GPP_S3", "SNDW2_DATA", + "GPP_S4", "SNDW3_CLK", + "GPP_S5", "SNDW3_DATA", + "GPP_S6", "SNDW4_CLK", + "GPP_S7", "SNDW4_DATA", +}; + +static const char *const icelake_pch_h_group_spi_names[] = { + /* SPI */ + "SPIP0", "SPI0_IO_2", + "SPIP1", "SPI0_IO_3", + "SPIP2", "SPI0_MOSI_IO_0", + "SPIP3", "SPI0_MISO_IO_1", + "SPIP4", "SPI0_TPM_CSB", + "SPIP5", "SPI0_FLASH_0_CSB", + "SPIP6", "SPI0_FLASH_1_CSB", + "SPIP7", "SPI0_CLK", + "SPIP8", "SPI0_CLK_LOOPBK", +}; + +static const struct gpio_group icelake_pch_h_group_g = { + .display = "------- GPIO Group GPP_G -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_g_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_g_names, +}; + +static const struct gpio_group icelake_pch_h_group_b = { + .display = "------- GPIO Group GPP_B -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_b_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_b_names, +}; + +static const struct gpio_group icelake_pch_h_group_a = { + .display = "------- GPIO Group GPP_A -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_a_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_a_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_0_groups[] = { + &icelake_pch_h_group_g, + &icelake_pch_h_group_b, + &icelake_pch_h_group_a, +}; + +static const struct gpio_community icelake_pch_h_community_0 = { + .name = "------- GPIO Community 0 -------", + .pcr_port_id = 0x6e, + .group_count = ARRAY_SIZE(icelake_pch_h_community_0_groups), + .groups = icelake_pch_h_community_0_groups, +}; + +static const struct gpio_group icelake_pch_h_group_h = { + .display = "------- GPIO Group GPP_H -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_h_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_h_names, +}; + +static const struct gpio_group icelake_pch_h_group_d = { + .display = "------- GPIO Group GPP_D -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_d_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_d_names, +}; + +static const struct gpio_group icelake_pch_h_group_f = { + .display = "------- GPIO Group GPP_F -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_f_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_f_names, +}; + +static const struct gpio_group icelake_pch_h_group_vgpio_0 = { + .display = "------- GPIO Group vGPIO_0 -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_vgpio_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_vgpio_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_1_groups[] = { + &icelake_pch_h_group_h, + &icelake_pch_h_group_d, + &icelake_pch_h_group_f, + &icelake_pch_h_group_vgpio_0, +}; + +static const struct gpio_community icelake_pch_h_community_1 = { + .name = "------- GPIO Community 1 -------", + .pcr_port_id = 0x6d, + .group_count = ARRAY_SIZE(icelake_pch_h_community_1_groups), + .groups = icelake_pch_h_community_1_groups, +}; + + +static const struct gpio_community icelake_pch_h_community_2 = { + .name = "------- GPIO Community 2 (skipped)-------", + .pcr_port_id = 0x6c, + .group_count = 0, +}; + +static const struct gpio_community icelake_pch_h_community_3 = { + .name = "------- GPIO Community 3 (skipped)-------", + .pcr_port_id = 0x6b, + .group_count = 0, +}; + +static const struct gpio_group icelake_pch_h_group_c = { + .display = "------- GPIO Group GPP_C -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_c_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_c_names, +}; + +static const struct gpio_group icelake_pch_h_group_hvcmos = { + .display = "------- GPIO Group HVCMOS -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_hvcmos_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_hvcmos_names, +}; + +static const struct gpio_group icelake_pch_h_group_e = { + .display = "------- GPIO Group E -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_e_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_e_names, +}; + +static const struct gpio_group icelake_pch_h_group_jtag = { + .display = "------- GPIO Group JTAG -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_jtag_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_jtag_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_4_groups[] = { + &icelake_pch_h_group_c, + &icelake_pch_h_group_hvcmos, + &icelake_pch_h_group_e, + &icelake_pch_h_group_jtag, +}; + +static const struct gpio_community icelake_pch_h_community_4 = { + .name = "------- GPIO Community 4 -------", + .pcr_port_id = 0x6a, + .group_count = ARRAY_SIZE(icelake_pch_h_community_4_groups), + .groups = icelake_pch_h_community_4_groups, +}; + +static const struct gpio_group icelake_pch_h_group_r = { + .display = "------- GPIO Group R -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_r_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_r_names, +}; + +static const struct gpio_group icelake_pch_h_group_s = { + .display = "------- GPIO Group S -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_s_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_s_names, +}; + +static const struct gpio_group icelake_pch_h_group_spi = { + .display = "------- GPIO Group SPI -------", + .pad_count = ARRAY_SIZE(icelake_pch_h_group_spi_names) / 2, + .func_count = 2, + .pad_names = icelake_pch_h_group_spi_names, +}; + +static const struct gpio_group *const icelake_pch_h_community_5_groups[] = { + &icelake_pch_h_group_r, + &icelake_pch_h_group_s, + &icelake_pch_h_group_spi, +}; + +static const struct gpio_community icelake_pch_h_community_5 = { + .name = "------- GPIO Community 5 -------", + .pcr_port_id = 0x69, + .group_count = ARRAY_SIZE(icelake_pch_h_community_5_groups), + .groups = icelake_pch_h_community_5_groups, +}; + +static const struct gpio_community *const icelake_pch_h_communities[] = { + &icelake_pch_h_community_0, + &icelake_pch_h_community_1, + &icelake_pch_h_community_2, + &icelake_pch_h_community_3, + &icelake_pch_h_community_4, + &icelake_pch_h_community_5, +}; static const char *decode_pad_mode(const struct gpio_group *const group, const size_t pad, const uint32_t dw0) @@ -2299,6 +2770,12 @@ void print_gpio_groups(struct pci_dev *const sb) pad_stepping = 16; pcr_init(sb); break; + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: + community_count = ARRAY_SIZE(icelake_pch_h_communities); + communities = icelake_pch_h_communities; + pad_stepping = 16; + pcr_init(sb); + break; default: return; } diff --git a/util/inteltool/pcr.c b/util/inteltool/pcr.c index ef6bb39d16..f4bf87bfb2 100644 --- a/util/inteltool/pcr.c +++ b/util/inteltool/pcr.c @@ -132,6 +132,7 @@ void pcr_init(struct pci_dev *const sb) case PCI_DEVICE_ID_INTEL_QM370: case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: + case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: sbbar_phys = 0xfd000000; use_p2sb = false; break; From cc805d9dd64ca2d3c8de2b2de2ea7c53b387ff8f Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Fri, 27 Dec 2019 18:56:24 +0300 Subject: [PATCH 054/151] sb/intel/common/acpi: Add more Windows versions For the up-to-date list of Windows versions follow this link: https://docs.microsoft.com/en-us/windows-hardware/drivers/acpi/winacpi-osi Change-Id: I5ee724f0b03edbfff7dd5b2ae642020cbcbab6d2 Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37943 Reviewed-by: Patrick Georgi Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../intel/common/acpi/platform.asl | 34 +++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/common/acpi/platform.asl b/src/southbridge/intel/common/acpi/platform.asl index 03cb625ce6..057d5c28d8 100644 --- a/src/southbridge/intel/common/acpi/platform.asl +++ b/src/southbridge/intel/common/acpi/platform.asl @@ -61,10 +61,16 @@ Method(GOS, 0) * OSYS value | Operating System * -----------+------------------ * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) + * 2001 | Windows XP + * 2001 | Windows XP SP1 + * 2001 | Windows Server 2003 + * 2001 | Windows Server 2003 SP1 * 2002 | Windows XP SP2 * 2006 | Windows Vista - * ???? | Windows 7 + * 2006 | Windows Vista SP1 + * 2006 | Windows Server 2008 + * 2009 | Windows 7 + * 2012 | Windows 8 */ /* Let's assume we're running at least Windows 2000 */ @@ -79,6 +85,14 @@ Method(GOS, 0) Store (2001, OSYS) } + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + If (_OSI("Windows 2001 SP2")) { Store (2002, OSYS) } @@ -86,5 +100,21 @@ Method(GOS, 0) If (_OSI("Windows 2006")) { Store (2006, OSYS) } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } } } From b3100775ae29caebd068db8f6209561abda2fb0c Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Fri, 27 Dec 2019 18:56:43 +0300 Subject: [PATCH 055/151] mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method Change-Id: I6408cb3c9ef1227d8cf7df12d192b10341205e2c Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37944 Reviewed-by: Alexander Couzens Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x201/acpi/platform.asl | 58 +------------------ .../packardbell/ms2290/acpi/platform.asl | 58 +------------------ 2 files changed, 2 insertions(+), 114 deletions(-) diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index ac7c00fbbc..ece96c4408 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -71,62 +71,6 @@ Scope(\_SB) /* TRAP(71) */ /* TODO */ - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } + \GOS() } } diff --git a/src/mainboard/packardbell/ms2290/acpi/platform.asl b/src/mainboard/packardbell/ms2290/acpi/platform.asl index 2371eab70f..a8296cc677 100644 --- a/src/mainboard/packardbell/ms2290/acpi/platform.asl +++ b/src/mainboard/packardbell/ms2290/acpi/platform.asl @@ -46,62 +46,6 @@ Scope(\_SB) /* TRAP(71) */ /* TODO */ - /* Determine the Operating System and save the value in OSYS. - * We have to do this in order to be able to work around - * certain windows bugs. - * - * OSYS value | Operating System - * -----------+------------------ - * 2000 | Windows 2000 - * 2001 | Windows XP(+SP1) - * 2002 | Windows XP SP2 - * 2006 | Windows Vista - * ???? | Windows 7 - */ - - /* Let's assume we're running at least Windows 2000 */ - Store (2000, OSYS) - - If (CondRefOf(_OSI)) { - If (_OSI("Windows 2001")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001 SP2")) { - Store (2002, OSYS) - } - - If (_OSI("Windows 2001.1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2001.1 SP1")) { - Store (2001, OSYS) - } - - If (_OSI("Windows 2006")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006.1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2006 SP1")) { - Store (2006, OSYS) - } - - If (_OSI("Windows 2009")) { - Store (2009, OSYS) - } - - If (_OSI("Windows 2012")) { - Store (2012, OSYS) - } - } + \GOS() } } From 123b191b47b3502eb326c2c229da6d5d1d15259e Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Sat, 25 Jan 2020 22:14:04 +0800 Subject: [PATCH 056/151] ec/google/wilco: Set cpu id and cores to EC Set CPU ID and cores to EC then EC will adapt power table according to the CPU ID and number of cores. BUG=b:148126144 BRANCH=None TEST=check EC can get correct CPU id and cores. Signed-off-by: Eric Lai Change-Id: I23f5580b15a20a01e03a5f4c798e73574f874c9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/38566 Reviewed-by: Duncan Laurie Reviewed-by: Mathew King Tested-by: build bot (Jenkins) --- src/ec/google/wilco/chip.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index b44cbd6c64..5729b4aa27 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -16,10 +16,13 @@ #include #include #include +#include #include #include +#include #include #include +#include #include #include @@ -124,6 +127,14 @@ static void wilco_ec_resume(void *unused) } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, wilco_ec_resume, NULL); +static int wilco_set_cpu_id(void) +{ + uint32_t cpu_phy_cores, cpu_virtual_cores; + + cpu_read_topology(&cpu_phy_cores, &cpu_virtual_cores); + return wilco_ec_set_cpuid(cpu_get_cpuid(), cpu_phy_cores, 0); +} + static void wilco_ec_init(struct device *dev) { if (!dev->enabled) @@ -153,6 +164,10 @@ static void wilco_ec_init(struct device *dev) /* Turn on camera power */ wilco_ec_send(KB_CAMERA, CAMERA_ON); + + /* Set cpu id and phy cores */ + if (wilco_set_cpu_id()) + printk(BIOS_ERR, "EC: use default cpu power table\n"); } static void wilco_ec_resource(struct device *dev, int index, From 81fa1b34dc77b619378d1c2067f524900b065d02 Mon Sep 17 00:00:00 2001 From: Amanda Huang Date: Mon, 6 Jan 2020 15:57:28 +0800 Subject: [PATCH 057/151] mb/google/hatch/variants/mushu: Enable dGPU BOMACO mode Configure GPP_H22 as output pin for BOMACO mode enabled. BOMACO stands for "Bus Off Memory Alive Core Off". BUG=b:146081272 TEST=emerge-mushu coreboot Change-Id: Ic35e55771d76b7254bcb457fcb38f37433b9ad67 Signed-off-by: Amanda Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/38210 Reviewed-by: Paul Menzel Reviewed-by: Angel Pons Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/hatch/variants/mushu/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index 09e159492c..a60662a264 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -41,6 +41,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C15, 1, DEEP), /* H3 : SPKR_PA_EN */ PAD_CFG_GPO(GPP_H3, 0, DEEP), + /* H22 : BOMACO_EN */ + PAD_CFG_GPO(GPP_H22, 0, DEEP), }; const struct pad_config *override_gpio_table(size_t *num) From e7601b5d6c6c3a0fdf0d779cfe12b9a381f0fba4 Mon Sep 17 00:00:00 2001 From: Craig Hesling Date: Tue, 28 Jan 2020 21:16:18 -0800 Subject: [PATCH 058/151] hatch/mushu: Fix FPMCU pwr/rst gpio handling Asserting reset in RO instead of in RW has no impact on security or performance, but it does limit improvements to this process later. This fix removes reset line control from RO and makes these variants consistent with other hatch variants. This fix reinforces the concept from commit fcd8c9e99e (hatch: Fix FPMCU pwr/rst gpio handling). BUG=b:148457345 TEST=None Change-Id: I12dc0c3bead7672e2d3207771212efb0d246973a Signed-off-by: Craig Hesling Reviewed-on: https://review.coreboot.org/c/coreboot/+/38623 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Paul Menzel --- .../google/hatch/variants/hatch/Makefile.inc | 4 ++- .../google/hatch/variants/hatch/gpio.c | 2 -- .../google/hatch/variants/hatch/ramstage.c | 25 +++++++++++++++++++ .../google/hatch/variants/mushu/Makefile.inc | 4 ++- .../google/hatch/variants/mushu/gpio.c | 2 -- .../google/hatch/variants/mushu/ramstage.c | 25 +++++++++++++++++++ 6 files changed, 56 insertions(+), 6 deletions(-) create mode 100644 src/mainboard/google/hatch/variants/hatch/ramstage.c create mode 100644 src/mainboard/google/hatch/variants/mushu/ramstage.c diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc index a990b5ad05..4bf640a7f4 100644 --- a/src/mainboard/google/hatch/variants/hatch/Makefile.inc +++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 -ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c index 862b28fe4a..2c4fa50cd6 100644 --- a/src/mainboard/google/hatch/variants/hatch/gpio.c +++ b/src/mainboard/google/hatch/variants/hatch/gpio.c @@ -55,8 +55,6 @@ const struct pad_config *override_gpio_table(size_t *num) * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/hatch/ramstage.c b/src/mainboard/google/hatch/variants/hatch/ramstage.c new file mode 100644 index 0000000000..5459f55cd1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc index a990b5ad05..4bf640a7f4 100644 --- a/src/mainboard/google/hatch/variants/mushu/Makefile.inc +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -19,5 +19,7 @@ SPD_SOURCES += 8G_2666 # 0b011 SPD_SOURCES += 16G_2400 # 0b100 SPD_SOURCES += 16G_2666 # 0b101 -ramstage-y += gpio.c bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c index a60662a264..fd12eb0e52 100644 --- a/src/mainboard/google/hatch/variants/mushu/gpio.c +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -59,8 +59,6 @@ const struct pad_config *override_gpio_table(size_t *num) * needed in this table. */ static const struct pad_config early_gpio_table[] = { - /* A12 : FPMCU_RST_ODL */ - PAD_CFG_GPO(GPP_A12, 0, DEEP), /* B15 : H1_SLAVE_SPI_CS_L */ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), /* B16 : H1_SLAVE_SPI_CLK */ diff --git a/src/mainboard/google/hatch/variants/mushu/ramstage.c b/src/mainboard/google/hatch/variants/mushu/ramstage.c new file mode 100644 index 0000000000..5459f55cd1 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +void variant_ramstage_init(void) +{ + /* + * Enable power to FPMCU, wait for power rail to stabilize, + * and then deassert FPMCU reset. + * Waiting for the power rail to stabilize can take a while, + * a minimum of 400us on Kohaku. + */ + gpio_output(GPP_C11, 1); + mdelay(1); + gpio_output(GPP_A12, 1); +} From 1ab6f0c176c1aa6947bf0d3fbe0a213f316e9c67 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 28 Jan 2020 22:06:37 -0800 Subject: [PATCH 059/151] soc/intel/tigerlake: Configure TCSS xHCI and xDCI Configure xHCI, xDCI according to board design BUG=none BRANCH=none TEST=Build and boot to OS Signed-off-by: Wonkyu Kim Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/38624 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/chip.h | 6 +++++- src/soc/intel/tigerlake/romstage/fsp_params_tgl.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 3f980d1552..4f57b0e07a 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corporation. + * Copyright (C) 2019-2020 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -218,6 +218,10 @@ struct soc_intel_tigerlake_config { FORCE_ENABLE, } CnviBtAudioOffload; + /* Tcss */ + uint8_t TcssXhciEn; + uint8_t TcssXdciEn; + /* * Override GPIO PM configuration: * 0: Use FSP default GPIO PM program, diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c index 9c105cadc2..fc3155f8ad 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2019 Intel Corp. + * Copyright (C) 2019-2020 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -105,6 +105,10 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Image clock: disable all clocks for bypassing FSP pin mux */ memset(m_cfg->ImguClkOutEn, 0, sizeof(m_cfg->ImguClkOutEn)); + /* Tcss */ + m_cfg->TcssXhciEn = config->TcssXhciEn; + m_cfg->TcssXdciEn = config->TcssXdciEn; + /* Enable Hyper Threading */ m_cfg->HyperThreading = 1; /* Disable Lock PCU Thermal Management registers */ From e127a8711f71067979211d53d4b855a353344f50 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Thu, 30 Jan 2020 19:19:37 +0800 Subject: [PATCH 060/151] lenovo/t440p: fix keyboard backlight It is found that keyboard backlight in T440p is enabled by clearing bit 3 of EC RAM 0x01. This patch sets has_keyboard_backlight in devicetree.cb and also corrects the CMOS configuration. Change-Id: Ib4c2b1591d26e2bb33f9549e3933efe9a6e0b043 Signed-off-by: Iru Cai Reviewed-on: https://review.coreboot.org/c/coreboot/+/38650 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Dennis Witzig Reviewed-by: Alexander Couzens --- src/mainboard/lenovo/t440p/cmos.default | 2 +- src/mainboard/lenovo/t440p/cmos.layout | 7 ++++--- src/mainboard/lenovo/t440p/devicetree.cb | 1 + 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t440p/cmos.default b/src/mainboard/lenovo/t440p/cmos.default index b104ae145c..0949e7b13c 100644 --- a/src/mainboard/lenovo/t440p/cmos.default +++ b/src/mainboard/lenovo/t440p/cmos.default @@ -9,5 +9,5 @@ fn_ctrl_swap=Disable f1_to_f12_as_primary=Enable sticky_fn=Disable trackpoint=Enable -backlight=Both +backlight=Keyboard usb_always_on=Disable diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 8c5fb0b14b..f65933a715 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -103,9 +103,10 @@ enumerations 8 1 Primary 9 0 AHCI 9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only +# Haswell ThinkPads have no Thinklight +#10 0 Both +10 1 Keyboard +#10 2 Thinklight only 10 3 None #12 0 Integrated Only #12 1 Discrete Only diff --git a/src/mainboard/lenovo/t440p/devicetree.cb b/src/mainboard/lenovo/t440p/devicetree.cb index 7e5e616d03..b63767e808 100644 --- a/src/mainboard/lenovo/t440p/devicetree.cb +++ b/src/mainboard/lenovo/t440p/devicetree.cb @@ -83,6 +83,7 @@ chip northbridge/intel/haswell register "config1" = "0x0d" register "config2" = "0xa8" register "config3" = "0xc4" + register "has_keyboard_backlight" = "1" register "event2_enable" = "0xff" register "event3_enable" = "0xff" register "event4_enable" = "0xd0" From 4519277ca2e11ed728754efbe13e1a444c479da3 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Sat, 1 Feb 2020 13:04:11 -0700 Subject: [PATCH 061/151] drivers/generic/gfx: Add null pointer error check acpi_device_scope() will return NULL if it is unable to find the path of the parent device. Return early if this is the case to prevent a null pointer dereference. Change-Id: I3eff1c1e3477c75c7130b52898de7d59692ba412 Signed-off-by: Jacob Garber Found-by: Coverity CID 1409672 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38669 Reviewed-by: David Hendricks Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/drivers/generic/gfx/gfx.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/drivers/generic/gfx/gfx.c b/src/drivers/generic/gfx/gfx.c index b2bda4a43c..0386e9b2ef 100644 --- a/src/drivers/generic/gfx/gfx.c +++ b/src/drivers/generic/gfx/gfx.c @@ -69,6 +69,9 @@ static void gfx_fill_ssdt_generator(struct device *dev) const char *scope = acpi_device_scope(dev); + if (!scope) + return; + acpigen_write_scope(scope); /* Method (_DOD, 0) */ From 84c7d2dfeac2b1b4f7c0449744c58c3f80a8607d Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 2 Oct 2019 13:35:08 -0600 Subject: [PATCH 062/151] xcompile: Disable null pointer optimizations According to the C standard, accessing the NULL pointer (memory at address zero) is undefined behaviour, and so GCC is allowed to optimize it out. Of course, accessing this memory location is sometimes necessary, so this optimization can be disabled using -fno-delete-null-pointer-checks. This is already done in coreboot, but adding it to xcompile will also disable it for all the payloads. For example, coreinfo compiled with LTO libpayload crashes when this flag isn't set, presumably because the compiler is optimizing something out that it shouldn't. Change-Id: I4492277f02418ade3fe7a75304e8e0611f49ef36 Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38289 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- Makefile.inc | 1 - util/xcompile/xcompile | 2 +- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index e9c5054e8a..4ca173b866 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -414,7 +414,6 @@ CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) -CFLAGS_common += -fno-delete-null-pointer-checks # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 8335c347fb..a116407b8b 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -221,7 +221,7 @@ SUBARCH_SUPPORTED+=${TSUPP-${TARCH}} GCC_CC_${TARCH}:=${GCC} GCC_CFLAGS_${TARCH}:=${CFLAGS_GCC} # Generally available for GCC's cc1: -GCC_CFLAGS_${TARCH}+=-Wlogical-op +GCC_CFLAGS_${TARCH}+=-fno-delete-null-pointer-checks -Wlogical-op GCC_ADAFLAGS_${TARCH}:=${CFLAGS_GCC} GCC_COMPILER_RT_${TARCH}:=${CC_RT_GCC} GCC_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_GCC} From 94e5ceea8c40e8fd17a9d07ce5bf577e61e3fd33 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 27 Jan 2020 22:37:59 -0800 Subject: [PATCH 063/151] Update vboot submodule to upstream master Updating from commit id 6ef33b99: 2019-11-22 Hung-Te Lin futility: updater: refactor: unify getting temp files for firmware images to commit id 0e97e25e: 2020-01-23 Julius Werner 2lib: Fix struct vb2_hash the way it was meant to be Change-Id: I539aba2f283804f67ff3ff4f98324b3d10b2bb54 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38604 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index f5367d598a..0e97e25e85 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit f5367d598a985520a8c935f68ac90d295c7b8d8e +Subproject commit 0e97e25e85f0499e23b09a31a2c7116759f191d5 From bd62472f76caa691b79084c060955b633fa4fe02 Mon Sep 17 00:00:00 2001 From: Jacob Garber Date: Wed, 2 Oct 2019 14:44:28 -0600 Subject: [PATCH 064/151] coreinfo/coreinfo.c: Correct main function signature libpayload passes argc and argv to main(), and ignoring these arguments causes a compile time error when using LTO. Change-Id: I5d2b30158ebabe1d1534a9684874018483ad769b Signed-off-by: Jacob Garber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38292 Reviewed-by: HAOUAS Elyes Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- payloads/coreinfo/coreinfo.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/payloads/coreinfo/coreinfo.c b/payloads/coreinfo/coreinfo.c index 53985b293a..b1017f079c 100644 --- a/payloads/coreinfo/coreinfo.c +++ b/payloads/coreinfo/coreinfo.c @@ -290,8 +290,11 @@ static void loop(void) } } -int main(void) +int main(int argc, char **argv) { + (void)argc; + (void)argv; + int j; if (CONFIG(LP_USB)) From bd3c1c7dd87aea3d9f06ed2cce4268104fae9c95 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Mon, 3 Feb 2020 11:44:18 -0700 Subject: [PATCH 065/151] commonlib/cbfs.h: Correct spelling error in comment Signed-off-by: Marshall Dawson Change-Id: Iac3ae21a381119bd0f24f68d4dd991817f2ff51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38684 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber --- src/commonlib/include/commonlib/cbfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index 470173023e..f5842d9047 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -24,7 +24,7 @@ struct cbfsf { struct region_device data; }; -/* Locate file by name and optional type. Returns 0 on succcess else < 0 on +/* Locate file by name and optional type. Returns 0 on success else < 0 on * error.*/ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, const char *name, uint32_t *type); From 16a23c0e101ae567b9b32aeb1d643f4b0a992cf0 Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Mon, 3 Feb 2020 17:39:44 +0800 Subject: [PATCH 066/151] mb/google/puff: Enable HECI communication Set HeciEnabled = 1 on puff device tree to turn on Intel ME communication interface. BUG=b:143232330 BRANCH=None TEST=Build puff and boot up OS. ran lspci and confirmed there is a HECI device. 00:16.0 Communication controller: Intel Corporation Device 02e0 Change-Id: I2debb885022ae31e395869d014a91824b5dd980c Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/38676 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie Reviewed-by: Edward O'Callaghan --- src/mainboard/google/hatch/variants/puff/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/overridetree.cb b/src/mainboard/google/hatch/variants/puff/overridetree.cb index d84b36986d..4ffbfed2b2 100644 --- a/src/mainboard/google/hatch/variants/puff/overridetree.cb +++ b/src/mainboard/google/hatch/variants/puff/overridetree.cb @@ -1,4 +1,6 @@ chip soc/intel/cannonlake + # Enable heci communication + register "HeciEnabled" = "1" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, From 3d2e18ad50d6dd0e93af1bb6efad20b4faede3b3 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Tue, 28 Jan 2020 11:20:05 -0700 Subject: [PATCH 067/151] soc/amd: unify SMBus support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/smbus/Kconfig | 5 + src/soc/amd/common/block/smbus/Makefile.inc | 7 + .../{stoneyridge => common/block/smbus}/sm.c | 0 .../{picasso => common/block/smbus}/smbus.c | 0 src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/Makefile.inc | 3 - src/soc/amd/picasso/sm.c | 103 --------- src/soc/amd/stoneyridge/Kconfig | 1 + src/soc/amd/stoneyridge/Makefile.inc | 3 - src/soc/amd/stoneyridge/smbus.c | 196 ------------------ 10 files changed, 14 insertions(+), 305 deletions(-) create mode 100644 src/soc/amd/common/block/smbus/Kconfig create mode 100644 src/soc/amd/common/block/smbus/Makefile.inc rename src/soc/amd/{stoneyridge => common/block/smbus}/sm.c (100%) rename src/soc/amd/{picasso => common/block/smbus}/smbus.c (100%) delete mode 100644 src/soc/amd/picasso/sm.c delete mode 100644 src/soc/amd/stoneyridge/smbus.c diff --git a/src/soc/amd/common/block/smbus/Kconfig b/src/soc/amd/common/block/smbus/Kconfig new file mode 100644 index 0000000000..dd54b638ea --- /dev/null +++ b/src/soc/amd/common/block/smbus/Kconfig @@ -0,0 +1,5 @@ +config SOC_AMD_COMMON_BLOCK_SMBUS + bool + default n + help + Select this option to add FCH SMBus controller functions to the build. diff --git a/src/soc/amd/common/block/smbus/Makefile.inc b/src/soc/amd/common/block/smbus/Makefile.inc new file mode 100644 index 0000000000..cfc954ec4f --- /dev/null +++ b/src/soc/amd/common/block/smbus/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y) + +romstage-y += smbus.c +ramstage-y += smbus.c +ramstage-y += sm.c + +endif diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/common/block/smbus/sm.c similarity index 100% rename from src/soc/amd/stoneyridge/sm.c rename to src/soc/amd/common/block/smbus/sm.c diff --git a/src/soc/amd/picasso/smbus.c b/src/soc/amd/common/block/smbus/smbus.c similarity index 100% rename from src/soc/amd/picasso/smbus.c rename to src/soc/amd/common/block/smbus/smbus.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 7561414c55..acceb00cad 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_HDA select SOC_AMD_COMMON_BLOCK_SATA + select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index f1e10c183f..680f0fa956 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -41,7 +41,6 @@ romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c -romstage-y += smbus.c romstage-y += memmap.c romstage-$(CONFIG_PICASSO_UART) += uart.c romstage-y += tsc_freq.c @@ -71,8 +70,6 @@ ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += acp.c ramstage-y += sata.c -ramstage-y += sm.c -ramstage-y += smbus.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c deleted file mode 100644 index f0ba559f3b..0000000000 --- a/src/soc/amd/picasso/sm.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* -* The southbridge enables all USB controllers by default in SMBUS Control. -* The southbridge enables SATA by default in SMBUS Control. -*/ - -static void sm_init(struct device *dev) -{ - setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); -} - -static u32 get_sm_mmio(struct device *dev) -{ - struct resource *res; - struct bus *pbus; - - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, 0x90); - if (res->base == SMB_BASE_ADDR) - return ACPIMMIO_SMBUS_BASE; - - return ACPIMMIO_ASF_BASE; -} - -static int lsmbus_recv_byte(struct device *dev) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_recv_byte(get_sm_mmio(dev), device); -} - -static int lsmbus_send_byte(struct device *dev, u8 val) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_send_byte(get_sm_mmio(dev), device, val); -} - -static int lsmbus_read_byte(struct device *dev, u8 address) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_read_byte(get_sm_mmio(dev), device, address); -} - -static int lsmbus_write_byte(struct device *dev, u8 address, u8 val) -{ - u8 device; - - device = dev->path.i2c.device; - return do_smbus_write_byte(get_sm_mmio(dev), device, address, val); -} -static struct smbus_bus_operations lops_smbus_bus = { - .recv_byte = lsmbus_recv_byte, - .send_byte = lsmbus_send_byte, - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static struct pci_operations lops_pci = { - .set_subsystem = pci_dev_set_subsystem, -}; -static struct device_operations smbus_ops = { - .read_resources = DEVICE_NOOP, - .set_resources = DEVICE_NOOP, - .enable_resources = pci_dev_enable_resources, - .init = sm_init, - .scan_bus = scan_smbus, - .ops_pci = &lops_pci, - .ops_smbus_bus = &lops_smbus_bus, -}; -static const struct pci_driver smbus_driver __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CZ_SMBUS, -}; diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index a03b8f3e84..c3fcad9a50 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PSP select SOC_AMD_COMMON_BLOCK_CAR select SOC_AMD_COMMON_BLOCK_S3 + select SOC_AMD_COMMON_BLOCK_SMBUS select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select PARALLEL_MP diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index e6cfa12ac4..eb8af2d7b2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -56,7 +56,6 @@ romstage-y += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c romstage-y += pmutil.c -romstage-y += smbus.c romstage-y += smbus_spd.c romstage-y += memmap.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -90,8 +89,6 @@ ramstage-y += southbridge.c ramstage-y += northbridge.c ramstage-y += pmutil.c ramstage-y += sata.c -ramstage-y += sm.c -ramstage-y += smbus.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c diff --git a/src/soc/amd/stoneyridge/smbus.c b/src/soc/amd/stoneyridge/smbus.c deleted file mode 100644 index 5474c5cd45..0000000000 --- a/src/soc/amd/stoneyridge/smbus.c +++ /dev/null @@ -1,196 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include - -/* - * Between 1-10 seconds, We should never timeout normally - * Longer than this is just painful when a timeout condition occurs. - */ -#define SMBUS_TIMEOUT (100 * 1000 * 10) - -static u8 controller_read8(uintptr_t base, u8 reg) -{ - switch (base) { - case ACPIMMIO_SMBUS_BASE: - return smbus_read8(reg); - case ACPIMMIO_ASF_BASE: - return asf_read8(reg); - default: - printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n", - base); - } - return 0xff; -} - -static void controller_write8(uintptr_t base, u8 reg, u8 val) -{ - switch (base) { - case ACPIMMIO_SMBUS_BASE: - smbus_write8(reg, val); - break; - case ACPIMMIO_ASF_BASE: - asf_write8(reg, val); - break; - default: - printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n", - base); - } -} - -static int smbus_wait_until_ready(uintptr_t mmio) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - val = controller_read8(mmio, SMBHSTSTAT); - val &= SMBHST_STAT_VAL_BITS; - if (val == 0) { /* ready now */ - return 0; - } - controller_write8(mmio, SMBHSTSTAT, val); - } while (--loops); - return -2; /* time out */ -} - -static int smbus_wait_until_done(uintptr_t mmio) -{ - u32 loops; - loops = SMBUS_TIMEOUT; - do { - u8 val; - - val = controller_read8(mmio, SMBHSTSTAT); - val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */ - if (val & SMBHST_STAT_ERROR_BITS) - return -5; /* error */ - if (val == SMBHST_STAT_NOERROR) { - controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */ - return 0; - } - } while (--loops); - return -3; /* timeout */ -} - -int do_smbus_recv_byte(uintptr_t mmio, u8 device) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - /* read results of transaction */ - byte = controller_read8(mmio, SMBHSTDAT0); - - return byte; -} - -int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the command... */ - controller_write8(mmio, SMBHSTDAT0, val); - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - return 0; -} - -int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the command/address... */ - controller_write8(mmio, SMBHSTCMD, address & 0xff); - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - /* read results of transaction */ - byte = controller_read8(mmio, SMBHSTDAT0); - - return byte; -} - -int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val) -{ - u8 byte; - - if (smbus_wait_until_ready(mmio) < 0) - return -2; /* not ready */ - - /* set the command/address... */ - controller_write8(mmio, SMBHSTCMD, address & 0xff); - - /* set the device I'm talking to */ - controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0); - - /* output value */ - controller_write8(mmio, SMBHSTDAT0, val); - - byte = controller_read8(mmio, SMBHSTCTRL); - byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */ - byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */ - controller_write8(mmio, SMBHSTCTRL, byte); - - /* poll for transaction completion */ - if (smbus_wait_until_done(mmio) < 0) - return -3; /* timeout or error */ - - return 0; -} From 6ec322ec7c27005d64a907076188b09a7cf09aa7 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 16 Jan 2020 11:11:09 -0800 Subject: [PATCH 068/151] cpu/x86: Make MP init timeout configurable The current MP init timeout is hardcoded as 1s. To support platform with many cpus, the timeout needs to be adjusted. The number of cpus is calculated as: number of sockets * number of cores per socket * number of threads per core How long the timeout should be set to, is heuristic. It needs to be set long enough to ensure reboot stability, but not unreasonable so that real failures can be detected soon enough, especially for smaller systems. This patch sets timeout to be minimum as 1 second, while each cpu adds 0.1 second. Signed-off-by: Jonathan Zhang Signed-off-by: Reddy Chagam Change-Id: Ibc079fc6aa8641d4ac8d8e726899b6c8d055052e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38546 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks --- src/cpu/x86/mp_init.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 45776f8186..b093be7003 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -13,6 +13,7 @@ */ #include +#include #include #include #include @@ -518,11 +519,12 @@ static int bsp_do_flight_plan(struct mp_params *mp_params) int i; int ret = 0; /* - * Set time-out to wait for APs to a huge value (=1 second) since it - * could take a longer time for APs to check-in as the number of APs - * increases (contention for resources like UART also increases). + * Set time out for flight plan to a huge minimum value (>=1 second). + * CPUs with many APs may take longer if there is contention for + * resources such as UART, so scale the time out up by increments of + * 100ms if needed. */ - const int timeout_us = 1000000; + const int timeout_us = MAX(1000000, 100000 * mp_params->num_cpus); const int step_us = 100; int num_aps = mp_params->num_cpus - 1; struct stopwatch sw; From d8663e0fc6629835eba44cc78e63e285aced897f Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Feb 2020 10:51:01 +0530 Subject: [PATCH 069/151] soc/intel: Remove duplicate CPUID entry This patch removes duplicate CPUID entry between KBL and CFL. CFL-D0 has KBL CPU + CNP PCH hence no need to redefine same KBL CPUID (0x806EA) for CFL-D0. TEST=CFL-D0 report platform serial msg shows "Cofeelake D0" with CPUID 0x806EA. Change-Id: I078dd7860891896b512967dc8dec5dd94d069193 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38672 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya --- src/soc/intel/cannonlake/bootblock/report_platform.c | 2 +- src/soc/intel/common/block/cpu/mp_init.c | 1 - src/soc/intel/common/block/include/intelblocks/mp_init.h | 1 - 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 67dd452e8e..b89c3b4147 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -37,7 +37,7 @@ static struct { { CPUID_CANNONLAKE_B0, "Cannonlake B0" }, { CPUID_CANNONLAKE_C0, "Cannonlake C0" }, { CPUID_CANNONLAKE_D0, "Cannonlake D0" }, - { CPUID_COFFEELAKE_D0, "Coffeelake D0" }, + { CPUID_KABYLAKE_Y0, "Coffeelake D0" }, { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index f3c6c7d573..66a358f09a 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -75,7 +75,6 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0 }, - { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index e0b0d8c174..c0c58afc8d 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -40,7 +40,6 @@ #define CPUID_GLK_R0 0x706a8 #define CPUID_WHISKEYLAKE_V0 0x806ec #define CPUID_WHISKEYLAKE_W0 0x806eb -#define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea #define CPUID_COFFEELAKE_B0 0x906eb #define CPUID_COFFEELAKE_P0 0x906ec From 4d9d3f164de7002dd38f12dc40f9b260f63d2d9b Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 9 Dec 2019 16:05:52 +0530 Subject: [PATCH 070/151] soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle With Audio DSP OSC qualification disabled from S0ix criteria. S0ix is achieved before the DSP is suspended. When driver tries to suspend DSP its already turned off. BUG=b:139481313 Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604 Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 5 +++++ src/soc/intel/cannonlake/finalize.c | 9 ++++++++- src/soc/intel/cannonlake/include/soc/pmc.h | 3 +++ 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0712146544..fd37d26492 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -59,8 +59,13 @@ struct soc_intel_cannonlake_config { uint32_t gen3_dec; uint32_t gen4_dec; + /* S0ix configuration */ + /* Enable S0iX support */ int s0ix_enable; + /* Enable Audio DSP oscillator qualification for S0ix */ + uint8_t cppmvric2_adsposcdis; + /* Enable DPTF support */ int dptf_enable; diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 002e8ea42b..b2fb9f9ec6 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -91,11 +91,18 @@ static void pch_finalize(void) write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); } - /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { + /* Disable XTAL shutdown qualification for low power idle. */ reg32 = read32(pmcbase + CPPMVRIC); reg32 |= XTALSDQDIS; write32(pmcbase + CPPMVRIC, reg32); + + if (config->cppmvric2_adsposcdis) { + /* Enable Audio DSP OSC qualification for S0ix */ + reg32 = read32(pmcbase + CPPMVRIC2); + reg32 &= ~ADSPOSCDIS; + write32(pmcbase + CPPMVRIC2, reg32); + } } pch_handle_sideband(config); diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 252c719925..fbd366bb2c 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -156,6 +156,9 @@ #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define CPPMVRIC2 0x1B4C +#define ADSPOSCDIS (1 << 22) + #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 #define ACTL 0x1BD8 From e65f500a0b90ccbf1a172427b7a61a047571ff02 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 4 Feb 2020 08:31:18 +0530 Subject: [PATCH 071/151] mb/google/hatch: Enable Audio DSP oscillator qualification for S0ix BUG=b:139481313 Change-Id: I1a0911b7967e5823fdce98195420728bd38c80f6 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/38680 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/hatch/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index e0291bbd3f..f7cf3cd466 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -142,6 +142,9 @@ chip soc/intel/cannonlake register "PchPmSlpSusMinAssert" = "1" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s + # Enable Audio DSP oscillator qualification for S0ix + register "cppmvric2_adsposcdis" = "1" + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 0 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC2)" # Type-C Port 1 register "usb2_ports[2]" = "USB2_PORT_SHORT(OC3)" # Type-A Port 0 From c9ac0bcb9827ab2bef5fd7548eb13302cfd9c57d Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Tue, 28 Jan 2020 19:54:33 +0100 Subject: [PATCH 072/151] security/tpm/tss: Add ClearControl Function Add ClearControl Function which is needed for a follow-up patch. Change-Id: Ia19185528fd821e420b0bdb424760c93b79523a4 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/38617 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/security/tpm/tss.h | 5 ++++ src/security/tpm/tss/tcg-2.0/tss.c | 17 ++++++++++++++ src/security/tpm/tss/tcg-2.0/tss_marshaling.c | 23 +++++++++++++++++++ src/security/tpm/tss/tcg-2.0/tss_structures.h | 5 ++++ 4 files changed, 50 insertions(+) diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 336935d911..5237387a74 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -170,6 +170,11 @@ uint32_t tlcl_set_nv_locked(void); */ uint32_t tlcl_force_clear(void); +/** + * Set Clear Control. The TPM error code is returned. + */ +uint32_t tlcl_clear_control(bool disable); + /** * Set the bGlobalLock flag, which only a reboot can clear. The TPM error * code is returned. diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 6bc30966ff..49a6cea083 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -170,6 +170,23 @@ uint32_t tlcl_force_clear(void) return TPM_SUCCESS; } +uint32_t tlcl_clear_control(bool disable) +{ + struct tpm2_response *response; + struct tpm2_clear_control_cmd cc = { + .disable = 0, + }; + + response = tpm_process_command(TPM2_ClearControl, &cc); + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} + static uint8_t tlcl_init_done; /* This function is called directly by vboot, uses vboot return types. */ diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 48798c7a04..45ade1a314 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -281,6 +281,24 @@ static int marshal_hierarchy_control(struct obuf *ob, return rc; } +static int marshal_clear_control(struct obuf *ob, + struct tpm2_clear_control_cmd *command_body) +{ + int rc = 0; + struct tpm2_session_header session_header; + + tpm_tag = TPM_ST_SESSIONS; + + rc |= marshal_TPM_HANDLE(ob, TPM_RH_PLATFORM); + memset(&session_header, 0, sizeof(session_header)); + session_header.session_handle = TPM_RS_PW; + rc |= marshal_session_header(ob, &session_header); + + rc |= obuf_write_be8(ob, command_body->disable); + + return rc; +} + static int marshal_cr50_vendor_command(struct obuf *ob, void *command_body) { int rc = 0; @@ -383,6 +401,10 @@ int tpm_marshal_command(TPM_CC command, void *tpm_command_body, struct obuf *ob) rc |= marshal_hierarchy_control(ob, tpm_command_body); break; + case TPM2_ClearControl: + rc |= marshal_clear_control(ob, tpm_command_body); + break; + case TPM2_Clear: rc |= marshal_clear(ob); break; @@ -583,6 +605,7 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) case TPM2_Hierarchy_Control: case TPM2_Clear: + case TPM2_ClearControl: case TPM2_NV_DefineSpace: case TPM2_NV_Write: case TPM2_NV_WriteLock: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 1530613226..ade9b27873 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -84,6 +84,7 @@ struct tpm_header { /* TPM command codes. */ #define TPM2_Hierarchy_Control ((TPM_CC)0x00000121) #define TPM2_Clear ((TPM_CC)0x00000126) +#define TPM2_ClearControl ((TPM_CC)0x00000127) #define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) #define TPM2_NV_Write ((TPM_CC)0x00000137) #define TPM2_NV_WriteLock ((TPM_CC)0x00000138) @@ -417,6 +418,10 @@ struct tpm2_pcr_extend_cmd { TPML_DIGEST_VALUES digests; }; +struct tpm2_clear_control_cmd { + TPMI_YES_NO disable; +}; + struct tpm2_hierarchy_control_cmd { TPMI_RH_ENABLES enable; TPMI_YES_NO state; From ebc8423cbcb0bcd95c45e68cdf04af9f10be1bfe Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Tue, 21 Jan 2020 16:46:16 -0500 Subject: [PATCH 073/151] soc/intel: Add get_pmbase Originally a part of security/intel/stm. Add get_pmbase to the intel platform setup code. get_pmbase is used by the coreboot STM setup functions to ensure that the pmbase is accessable by the SMI handler during runtime. The pmbase has to be accounted for in the BIOS resource list so that the SMI handler is allowed this access. Change-Id: If6f6295c5eba9eb20e57ab56e7f965c8879e93d2 Signed-off-by: Eugene D. Myers Reviewed-on: https://review.coreboot.org/c/coreboot/+/37990 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/include/soc/pm.h | 3 +++ src/soc/intel/apollolake/pmutil.c | 6 ++++++ src/soc/intel/broadwell/include/soc/pm.h | 3 +++ src/soc/intel/broadwell/pmutil.c | 6 ++++++ src/soc/intel/cannonlake/include/soc/pm.h | 3 +++ src/soc/intel/cannonlake/pmutil.c | 6 ++++++ src/soc/intel/icelake/include/soc/pm.h | 3 +++ src/soc/intel/icelake/pmutil.c | 6 ++++++ src/soc/intel/quark/acpi.c | 7 +++++++ src/soc/intel/quark/include/soc/pm.h | 3 +++ src/soc/intel/skylake/include/soc/pm.h | 3 +++ src/soc/intel/skylake/pmutil.c | 6 ++++++ src/soc/intel/tigerlake/include/soc/pm.h | 2 ++ src/soc/intel/tigerlake/pmutil.c | 6 ++++++ 14 files changed, 63 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index d0b0421561..22e414c803 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -250,4 +250,7 @@ void pch_log_state(void); void enable_pm_timer_emulation(void); +/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 559adad405..8151afc08d 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -246,3 +246,9 @@ int vbnv_cmos_failed(void) return rtc_failure; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/broadwell/include/soc/pm.h b/src/soc/intel/broadwell/include/soc/pm.h index 18004fa77d..c9074d8a0b 100644 --- a/src/soc/intel/broadwell/include/soc/pm.h +++ b/src/soc/intel/broadwell/include/soc/pm.h @@ -155,4 +155,7 @@ void disable_gpe(uint32_t mask); /* Return the selected ACPI SCI IRQ */ int acpi_sci_irq(void); +/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/broadwell/pmutil.c b/src/soc/intel/broadwell/pmutil.c index 00db6156ec..2445dfacf6 100644 --- a/src/soc/intel/broadwell/pmutil.c +++ b/src/soc/intel/broadwell/pmutil.c @@ -458,3 +458,9 @@ int vboot_platform_is_resuming(void) return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 5b85e74bf5..356f0bcc6f 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -172,5 +172,8 @@ void pmc_set_disb(void); /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void); +/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index aded9c0cec..2d691adbb2 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -272,3 +272,9 @@ void soc_fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/icelake/include/soc/pm.h b/src/soc/intel/icelake/include/soc/pm.h index 44888ec747..34c32a9ac2 100644 --- a/src/soc/intel/icelake/include/soc/pm.h +++ b/src/soc/intel/icelake/include/soc/pm.h @@ -171,5 +171,8 @@ void pmc_set_disb(void); /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void); +/* STM Support */ +uint16_t get_pmbase(void); + #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 7b6168b084..440efd011f 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -271,3 +271,9 @@ void soc_fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index ffcd91f13d..5006b19d47 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -104,3 +104,10 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) printk(BIOS_SPEW, " 0x%08x: RESET\n", fadt->reset_reg.addrl); } + +uint16_t get_pmbase(void) +{ + struct device *dev = pcidev_on_root(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC); + return (uint16_t) pci_read_config32(dev, R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK; +} diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h index a3fb02f7db..e02b8a274e 100644 --- a/src/soc/intel/quark/include/soc/pm.h +++ b/src/soc/intel/quark/include/soc/pm.h @@ -27,4 +27,7 @@ struct chipset_power_state { struct chipset_power_state *get_power_state(void); int fill_power_state(void); +/* STM Support */ +uint16_t get_pmbase(void); + #endif /* _SOC_PM_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 18b0c15d64..007d29cadc 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -197,4 +197,7 @@ static inline int deep_s5_enabled(void) return !!(deep_s5_pol & (S5DC_GATE_SUS | S5AC_GATE_SUS)); } +/* STM Support */ +uint16_t get_pmbase(void); + #endif diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 2b2141b377..afe9b71117 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -275,3 +275,9 @@ void soc_fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return ACPI_BASE_ADDRESS; +} diff --git a/src/soc/intel/tigerlake/include/soc/pm.h b/src/soc/intel/tigerlake/include/soc/pm.h index fb9b67bc23..d2f47e271b 100644 --- a/src/soc/intel/tigerlake/include/soc/pm.h +++ b/src/soc/intel/tigerlake/include/soc/pm.h @@ -177,5 +177,7 @@ void pmc_set_disb(void); /* Clear PMCON status bits */ void pmc_clear_pmcon_sts(void); +/* STM Support */ +uint16_t get_pmbase(void); #endif /* !defined(__ACPI__) */ #endif diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 84a93aebbc..d9eb18665e 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -279,3 +279,9 @@ void soc_fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "GBLRST_CAUSE: %08x %08x\n", ps->gblrst_cause[0], ps->gblrst_cause[1]); } + +/* STM Support */ +uint16_t get_pmbase(void) +{ + return (uint16_t) ACPI_BASE_ADDRESS; +} From 7a4983d1d2731cf3ea82016b6b8009668c1fc3f2 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Wed, 9 Oct 2019 00:38:43 -0400 Subject: [PATCH 074/151] arch/x86/include/arch: Add SMM_TASK_STATE_SEG This define is used to set up the STM SMM Descriptor table tr entry. Signed-off-by: Eugene D. Myers Change-Id: Iddb1f45444d03465a66a4ebb9fde5f206dc5b300 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38657 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/arch/x86/include/arch/rom_segs.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/arch/x86/include/arch/rom_segs.h b/src/arch/x86/include/arch/rom_segs.h index a19d3de461..c11def6b02 100644 --- a/src/arch/x86/include/arch/rom_segs.h +++ b/src/arch/x86/include/arch/rom_segs.h @@ -18,4 +18,11 @@ #define ROM_DATA_SEG 0x10 #define ROM_CODE_SEG64 0x18 +/* + * This define is placed here to make sure future romstage programmers + * know about it. + * It is used for STM setup code. + */ +#define SMM_TASK_STATE_SEG 0x20 + #endif /* ROM_SEGS_H */ From 821004776ffbf2a7d0bc321bdf094cff13dfcc09 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 27 Jan 2020 15:47:44 +0100 Subject: [PATCH 075/151] vendorcode/eltan/security: Switch to vb2 vboot library The eltan verified_boot is using the vboot 2.1 data structures and code, as well as the fwlib21 build target, they are all deprecated. Refer to CB:37654 for more information. The verified_boot code is updated to use the vb2 structures and code and make sure only public functions are used. BUG=N/A TEST=build Change-Id: I1e1a7bce6110fe35221a4d7a47c1eb7c7074c318 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38590 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/security/vboot/Kconfig | 1 - src/vendorcode/eltan/security/Makefile.inc | 1 - .../eltan/security/include/cb_sha.h | 26 ------ .../eltan/security/lib/Makefile.inc | 60 ------------- src/vendorcode/eltan/security/lib/cb_sha.c | 38 -------- src/vendorcode/eltan/security/mboot/Kconfig | 1 + src/vendorcode/eltan/security/mboot/mboot.c | 4 +- src/vendorcode/eltan/security/mboot/mboot.h | 1 - .../eltan/security/verified_boot/Kconfig | 6 +- .../eltan/security/verified_boot/Makefile.inc | 1 + .../security/verified_boot/vboot_check.c | 87 +++++++++++-------- .../security/verified_boot/vboot_check.h | 2 +- 12 files changed, 59 insertions(+), 169 deletions(-) delete mode 100644 src/vendorcode/eltan/security/include/cb_sha.h delete mode 100644 src/vendorcode/eltan/security/lib/Makefile.inc delete mode 100644 src/vendorcode/eltan/security/lib/cb_sha.c diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 30b99afc8f..ea70e65256 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -17,7 +17,6 @@ menu "Verified Boot (vboot)" config VBOOT_LIB bool - depends on !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT help Build and link the vboot library. Makes the vboot API accessible across all coreboot stages, without enabling vboot verification. For verification, diff --git a/src/vendorcode/eltan/security/Makefile.inc b/src/vendorcode/eltan/security/Makefile.inc index 16f17fddd7..c0d9057977 100644 --- a/src/vendorcode/eltan/security/Makefile.inc +++ b/src/vendorcode/eltan/security/Makefile.inc @@ -12,7 +12,6 @@ ## GNU General Public License for more details. ## -subdirs-y += lib subdirs-y += verified_boot subdirs-y += mboot diff --git a/src/vendorcode/eltan/security/include/cb_sha.h b/src/vendorcode/eltan/security/include/cb_sha.h deleted file mode 100644 index 9a231d8a1e..0000000000 --- a/src/vendorcode/eltan/security/include/cb_sha.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018-2019, Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SECURITY_CB_SHA_H__ -#define __SECURITY_CB_SHA_H__ - -#include <2rsa.h> -#include -#include - -vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, - uint32_t len, uint8_t *digest); - -#endif diff --git a/src/vendorcode/eltan/security/lib/Makefile.inc b/src/vendorcode/eltan/security/lib/Makefile.inc deleted file mode 100644 index 2e11fb5a00..0000000000 --- a/src/vendorcode/eltan/security/lib/Makefile.inc +++ /dev/null @@ -1,60 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2018-2019 Eltan B.V. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -# call with $1 = stage name to create rules for building the library -# for the stage and adding it to the stage's set of object files. -define vendor-security-lib -VEN_SEC_LIB_$(1) = $(obj)/external/ven_sec_lib-$(1)/vboot_fw21.a -VEN_SEC_CFLAGS_$(1) += $$(patsubst -I%,-I$(top)/%,\ - $$(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ - $$(filter-out -I$(obj), $$(CPPFLAGS_$(1))))) -VEN_SEC_CFLAGS_$(1) += $$(CFLAGS_$(1)) -VEN_SEC_CFLAGS_$(1) += $$($(1)-c-ccopts) -VEN_SEC_CFLAGS_$(1) += -I$(abspath $(obj)) -Wno-missing-prototypes - -$$(VEN_SEC_LIB_$(1)): $(obj)/config.h - printf " MAKE $(subst $(obj)/,,$(@))\n" - +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ - CFLAGS="$$(VEN_SEC_CFLAGS_$(1))" VBOOT2="y" \ - $(MAKE) -C $(VBOOT_SOURCE) \ - BUILD=$$(abspath $$(dir $$(VEN_SEC_LIB_$(1)))) \ - V=$(V) \ - fwlib21 -endef # vendor-security-for-stage - -CFLAGS_common += -I3rdparty/vboot/firmware/2lib/include -CFLAGS_common += -I3rdparty/vboot/firmware/lib21/include - -ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBOOT)),) - -bootblock-y += cb_sha.c -bootblock-y += ../../../../security/vboot/vboot_logic.c -$(eval $(call vendor-security-lib,bootblock)) -bootblock-srcs += $(obj)/external/ven_sec_lib-bootblock/vboot_fw21.a - -postcar-y += cb_sha.c -$(eval $(call vendor-security-lib,postcar)) -postcar-srcs += $(obj)/external/ven_sec_lib-postcar/vboot_fw21.a - -ramstage-y += cb_sha.c -$(eval $(call vendor-security-lib,ramstage)) -ramstage-srcs += $(obj)/external/ven_sec_lib-ramstage/vboot_fw21.a - -romstage-y += cb_sha.c -$(eval $(call vendor-security-lib,romstage)) -romstage-srcs += $(obj)/external/ven_sec_lib-romstage/vboot_fw21.a - -endif \ No newline at end of file diff --git a/src/vendorcode/eltan/security/lib/cb_sha.c b/src/vendorcode/eltan/security/lib/cb_sha.c deleted file mode 100644 index 20a84afacc..0000000000 --- a/src/vendorcode/eltan/security/lib/cb_sha.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2019 Eltan B.V. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include - -vb2_error_t cb_sha_little_endian(enum vb2_hash_algorithm hash_alg, const uint8_t *data, - uint32_t len, uint8_t *digest) -{ - int i; - int rv; - uint32_t digest_size = vb2_digest_size(hash_alg); - uint8_t result[VB2_MAX_DIGEST_SIZE]; - - if (!digest_size) - return VB2_ERROR_SHA_INIT_ALGORITHM; - - rv = vb2_digest_buffer(data, len, hash_alg, (uint8_t *)&result, digest_size); - if (rv) - return rv; - - for (i = 0; i < digest_size; ++i) { - /* use little endian */ - digest[digest_size - i - 1] = result[i]; - } - return rv; -} diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index c4e8dbabee..b95c125578 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -17,6 +17,7 @@ menu "Measured Boot (mboot)" config VENDORCODE_ELTAN_MBOOT bool "Measure firmware with mboot." default n + select VBOOT_LIB help Enabling MBOOT will use mboot to measure the components of the firmware (stages, payload, etc). diff --git a/src/vendorcode/eltan/security/mboot/mboot.c b/src/vendorcode/eltan/security/mboot/mboot.c index c5523a5fd8..4429c1f5a0 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.c +++ b/src/vendorcode/eltan/security/mboot/mboot.c @@ -142,8 +142,8 @@ int mboot_hash_extend_log(uint64_t flags, uint8_t *hashData, uint32_t hashDataLe /* The hash is provided as data */ memcpy(digest->digest.sha256, (void *)hashData, hashDataLen); } else { - if (cb_sha_little_endian(VB2_HASH_SHA256, hashData, hashDataLen, - digest->digest.sha256)) + if (vb2_digest_buffer(hashData, hashDataLen, VB2_HASH_SHA256, digest->digest.sha256, + VB2_SHA256_DIGEST_SIZE)) return TPM_E_IOERROR; } diff --git a/src/vendorcode/eltan/security/mboot/mboot.h b/src/vendorcode/eltan/security/mboot/mboot.h index 79f23087c2..9cb94b11df 100644 --- a/src/vendorcode/eltan/security/mboot/mboot.h +++ b/src/vendorcode/eltan/security/mboot/mboot.h @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index ab254c48d9..d6ff541744 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -18,6 +18,7 @@ config VENDORCODE_ELTAN_VBOOT bool "Enable Verified Boot" depends on !VBOOT default n + select VBOOT_LIB config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST bool "Enable Signed Manifest" @@ -57,11 +58,10 @@ config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION config VENDORCODE_ELTAN_VBOOT_KEY_FILE string "Verified boot Key File" depends on VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST - default "3rdparty/eltan/verified_boot/Keys/key.vbpubk2" + default "3rdparty/eltan/verified_boot/Keys/key.vbpubk" config VENDORCODE_ELTAN_VBOOT_KEY_SIZE int - default 610 if VENDORCODE_ELTAN_VBOOT_USE_SHA512 - default 576 + default 552 endmenu # Verified Boot (verified_boot) diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 97d8f81c91..827535b963 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -17,6 +17,7 @@ ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBO CPPFLAGS_common += -I$(src)/security/vboot +bootblock-y += ../../../../security/vboot/vboot_logic.c bootblock-y += vboot_check.c postcar-y += vboot_check.c romstage-y += vboot_check.c diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.c b/src/vendorcode/eltan/security/verified_boot/vboot_check.c index 461a847b71..2edd8f9a74 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.c +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.c @@ -13,6 +13,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#define NEED_VB20_INTERNALS + #include #include #include @@ -32,12 +35,17 @@ int verified_boot_check_manifest(void) { uint8_t *buffer; - uint8_t sig_buffer[1024]; /* used to build vb21_signature */ - size_t size = 0; - struct vb2_public_key key; - struct vb2_workbuf wb; - struct vb21_signature *vb2_sig_hdr = (struct vb21_signature *)sig_buffer; - uint8_t wb_buffer[1024]; + struct vb2_context *ctx; + struct vb2_kernel_preamble *pre; + static struct vb2_shared_data *sd; + size_t size; + uint8_t wb_buffer[2800]; + + if (vb2api_init(&wb_buffer, sizeof(wb_buffer), &ctx)) { + goto fail; + } + + sd = vb2_get_sd(ctx); buffer = cbfs_boot_map_with_leak(RSA_PUBLICKEY_FILE_NAME, CBFS_TYPE_RAW, &size); if (!buffer || !size) { @@ -46,48 +54,61 @@ int verified_boot_check_manifest(void) } if ((size != CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_SIZE) || - (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { + (buffer != (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION)) { printk(BIOS_ERR, "ERROR: Illegal public key!\n"); goto fail; } - if (vb21_unpack_key(&key, buffer, size)) { - printk(BIOS_ERR, "ERROR: Invalid public key!\n"); + /* + * Check if all items will fit into workbuffer: + * vb2_shared data, Public Key, Preamble data + */ + if ((sd->workbuf_used + size + sizeof(struct vb2_kernel_preamble) + + ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) > + sizeof(wb_buffer)) { + printk(BIOS_ERR, "ERROR: Work buffer too small\n"); goto fail; } + /* Add public key */ + sd->data_key_offset = sd->workbuf_used; + sd->data_key_size = size; + sd->workbuf_used += sd->data_key_size; + memcpy((void *)((void *)sd + (long)sd->data_key_offset), (uint8_t *)buffer, size); + + /* Fill preamble area */ + sd->preamble_size = sizeof(struct vb2_kernel_preamble); + sd->preamble_offset = sd->data_key_offset + sd->data_key_size; + sd->workbuf_used += sd->preamble_size; + pre = (struct vb2_kernel_preamble *)((void *)sd + (long)sd->preamble_offset); + + pre->flags = VB2_FIRMWARE_PREAMBLE_DISALLOW_HWCRYPTO; + + /* Fill body_signature (vb2_structure). RSA2048 key is used */ cbfs_boot_map_with_leak("oemmanifest.bin", CBFS_TYPE_RAW, &size); - if (size != (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + - vb2_rsa_sig_size(VB2_SIG_RSA2048)) { + if (size != ((CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE) + (2048/8))) { printk(BIOS_ERR, "ERROR: Incorrect manifest size!\n"); goto fail; } - - /* prepare work buffer structure */ - wb.buf = (uint8_t *)&wb_buffer; - wb.size = sizeof(wb_buffer); - - /* Build vb2_sig_hdr buffer */ - vb2_sig_hdr->sig_offset = sizeof(struct vb21_signature) + - (CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE); - vb2_sig_hdr->sig_alg = VB2_SIG_RSA2048; - vb2_sig_hdr->sig_size = vb2_rsa_sig_size(VB2_SIG_RSA2048); - vb2_sig_hdr->hash_alg = HASH_ALG; - vb2_sig_hdr->data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * DIGEST_SIZE; - memcpy(&sig_buffer[sizeof(struct vb21_signature)], + pre->body_signature.data_size = CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_ITEMS * + DIGEST_SIZE; + pre->body_signature.sig_offset = sizeof(struct vb2_signature) + + pre->body_signature.data_size; + pre->body_signature.sig_size = size - pre->body_signature.data_size; + sd->workbuf_used += size; + memcpy((void *)((void *)&pre->body_signature + (long)sizeof(struct vb2_signature)), (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, size); - if (vb21_verify_data(&sig_buffer[sizeof(struct vb21_signature)], vb2_sig_hdr->data_size, - (struct vb21_signature *)&sig_buffer, &key, &wb)) { - printk(BIOS_ERR, "ERROR: Signature verification failed for hash table\n"); + + if (vb2api_verify_kernel_data(ctx, (void *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC, + pre->body_signature.data_size)) goto fail; - } printk(BIOS_INFO, "%s: Successfully verified hash_table signature.\n", __func__); return 0; fail: - die("HASH table verification failed!\n"); + die("ERROR: HASH table verification failed!\n"); return -1; } @@ -131,20 +152,14 @@ static void verified_boot_check_buffer(const char *name, void *start, size_t siz uint32_t hash_index, int32_t pcr) { uint8_t digest[DIGEST_SIZE]; - int hash_algorithm; vb2_error_t status; printk(BIOS_DEBUG, "%s: %s HASH verification buffer %p size %d\n", __func__, name, start, (int)size); if (start && size) { - if (CONFIG(VENDORCODE_ELTAN_VBOOT_USE_SHA512)) - hash_algorithm = VB2_HASH_SHA512; - else - hash_algorithm = VB2_HASH_SHA256; - status = cb_sha_little_endian(hash_algorithm, (const uint8_t *)start, size, - digest); + status = vb2_digest_buffer((const uint8_t *)start, size, HASH_ALG, digest, DIGEST_SIZE); if ((CONFIG(VENDORCODE_ELTAN_VBOOT) && memcmp((void *)( (uint8_t *)CONFIG_VENDORCODE_ELTAN_OEM_MANIFEST_LOC + sizeof(digest) * hash_index), digest, sizeof(digest))) || status) { diff --git a/src/vendorcode/eltan/security/verified_boot/vboot_check.h b/src/vendorcode/eltan/security/verified_boot/vboot_check.h index bd284925ae..d4f3b5ef9c 100644 --- a/src/vendorcode/eltan/security/verified_boot/vboot_check.h +++ b/src/vendorcode/eltan/security/verified_boot/vboot_check.h @@ -23,7 +23,7 @@ #include #include CONFIG_VENDORCODE_ELTAN_VBOOT_MANIFEST #include -#include +#include #include #include #include From cf2ac543a0e628bfcce4ea348876a310cb81335c Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 9 Oct 2019 21:40:36 -0600 Subject: [PATCH 076/151] pciexp: Add support for allocating PCI express hotplug resources This change adds support for allocating resources for PCI express hotplug bridges when PCIEXP_HOTPLUG is selected. By default, this will add 32 PCI subordinate numbers (buses), 256 MiB of prefetchable memory, 8 MiB of non-prefetchable memory, and 8 KiB of I/O space to any device with the PCI_EXP_SLTCAP_HPC bit set in the PCI_EXP_SLTCAP register, which indicates hot-plugging capability. The resource allocation is configurable, please see the PCIEXP_HOTPLUG_* variables in src/device/Kconfig. In order to support the allocation of hotplugged PCI buses, a new field is added to struct device called hotplug_buses. This is defaulted to zero, but when set, it adds the hotplug_buses value to the subordinate value of the PCI bridge. This allows devices to be plugged in and unplugged after boot. This code was tested on the System76 Darter Pro (darp6). Before this change, there are not enough resources allocated to the Thunderbolt PCI bridge to allow plugging in new devices after boot. This can be worked around in the Linux kernel by passing a boot param such as: pci=assign-busses,hpbussize=32,realloc This change makes it possible to use Thunderbolt hotplugging without kernel parameters, and attempts to match closely what our motherboard manufacturer's firmware does by default. Signed-off-by: Jeremy Soller Change-Id: I500191626584b83e6a8ae38417fd324b5e803afc Reviewed-on: https://review.coreboot.org/c/coreboot/+/35946 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/device/Kconfig | 44 +++++++++++++++++++++++++++ src/device/pci_device.c | 10 +++++- src/device/pciexp_device.c | 59 ++++++++++++++++++++++++++++++++++++ src/include/device/device.h | 1 + src/include/device/pci_def.h | 1 + src/include/device/pciexp.h | 6 ++++ 6 files changed, 120 insertions(+), 1 deletion(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index 0bd9fe1d8b..a25bb911c9 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -555,6 +555,50 @@ config PCIEXP_L1_SUB_STATE help Detect and enable ASPM on PCIe links. +config PCIEXP_HOTPLUG + prompt "Enable PCIe Hotplug Support" + bool + default n + help + Allocate resources for PCIe hotplug bridges + +if PCIEXP_HOTPLUG + +config PCIEXP_HOTPLUG_BUSES + int "PCI Express Hotplug Buses" + default 32 + help + This is the number of buses allocated for hotplug PCI express + bridges, for use by hotplugged child devices. The default is 32 + buses. + +config PCIEXP_HOTPLUG_MEM + hex "PCI Express Hotplug Memory" + default 0x800000 + help + This is the amount of memory space, in bytes, to allocate to + hotplug PCI express bridges, for use by hotplugged child devices. + This size should be page-aligned. The default is 8 MiB. + +config PCIEXP_HOTPLUG_PREFETCH_MEM + hex "PCI Express Hotplug Prefetch Memory" + default 0x10000000 + help + This is the amount of pre-fetchable memory space, in bytes, to + allocate to hot-plug PCI express bridges, for use by hotplugged + child devices. This size should be page-aligned. The default is + 256 MiB. + +config PCIEXP_HOTPLUG_IO + hex "PCI Express Hotplug I/O Space" + default 0x2000 + help + This is the amount of I/O space to allocate to hot-plug PCI + express bridges, for use by hotplugged child devices. The default + is 8 KiB. + +endif # PCIEXP_HOTPLUG + endif # PCIEXP_PLUGIN_SUPPORT config EARLY_PCI_BRIDGE diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 36b7c82d2a..47c0e9f2d2 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -878,6 +878,14 @@ static struct device_operations *get_pci_bridge_ops(struct device *dev) case PCI_EXP_TYPE_DOWNSTREAM: printk(BIOS_DEBUG, "%s subordinate bus PCI Express\n", dev_path(dev)); +#if CONFIG(PCIEXP_HOTPLUG) + u16 sltcap; + sltcap = pci_read_config16(dev, pciexpos + PCI_EXP_SLTCAP); + if (sltcap & PCI_EXP_SLTCAP_HPC) { + printk(BIOS_DEBUG, "%s hot-plug capable\n", dev_path(dev)); + return &default_pciexp_hotplug_ops_bus; + } +#endif /* CONFIG(PCIEXP_HOTPLUG) */ return &default_pciexp_ops_bus; case PCI_EXP_TYPE_PCI_BRIDGE: printk(BIOS_DEBUG, "%s subordinate PCI\n", @@ -1259,7 +1267,7 @@ static void pci_bridge_route(struct bus *link, scan_state state) if (state == PCI_ROUTE_SCAN) { link->secondary = parent->subordinate + 1; - link->subordinate = link->secondary; + link->subordinate = link->secondary + dev->hotplug_buses; } if (state == PCI_ROUTE_CLOSE) { diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 479891c5d6..b0ad1450e0 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -518,3 +518,62 @@ struct device_operations default_pciexp_ops_bus = { .reset_bus = pci_bus_reset, .ops_pci = &pciexp_bus_ops_pci, }; + +#if CONFIG(PCIEXP_HOTPLUG) + +static void pciexp_hotplug_dummy_read_resources(struct device *dev) +{ + struct resource *resource; + + // Add extra memory space + resource = new_resource(dev, 0x10); + resource->size = CONFIG_PCIEXP_HOTPLUG_MEM; + resource->align = 12; + resource->gran = 12; + resource->limit = 0xffffffff; + resource->flags |= IORESOURCE_MEM; + + // Add extra prefetchable memory space + resource = new_resource(dev, 0x14); + resource->size = CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM; + resource->align = 12; + resource->gran = 12; + resource->limit = 0xffffffffffffffff; + resource->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; + + // Add extra I/O space + resource = new_resource(dev, 0x18); + resource->size = CONFIG_PCIEXP_HOTPLUG_IO; + resource->align = 12; + resource->gran = 12; + resource->limit = 0xffff; + resource->flags |= IORESOURCE_IO; +} + +static struct device_operations pciexp_hotplug_dummy_ops = { + .read_resources = pciexp_hotplug_dummy_read_resources, +}; + +void pciexp_hotplug_scan_bridge(struct device *dev) +{ + dev->hotplug_buses = CONFIG_PCIEXP_HOTPLUG_BUSES; + + /* Normal PCIe Scan */ + pciexp_scan_bridge(dev); + + /* Add dummy slot to preserve resources, must happen after bus scan */ + struct device *dummy; + struct device_path dummy_path = { .type = DEVICE_PATH_NONE }; + dummy = alloc_dev(dev->link_list, &dummy_path); + dummy->ops = &pciexp_hotplug_dummy_ops; +} + +struct device_operations default_pciexp_hotplug_ops_bus = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pciexp_hotplug_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &pciexp_bus_ops_pci, +}; +#endif /* CONFIG(PCIEXP_HOTPLUG) */ diff --git a/src/include/device/device.h b/src/include/device/device.h index 2d7400b464..c3a1106023 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -121,6 +121,7 @@ struct device { unsigned int disable_pcie_aspm : 1; unsigned int hidden : 1; /* set if we should hide from UI */ u8 command; + uint16_t hotplug_buses; /* Number of hotplug buses to allocate */ /* Base registers for this device. I/O, MEM and Expansion ROM */ DEVTREE_CONST struct resource *resource_list; diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index d906445157..07ba4a2b30 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -435,6 +435,7 @@ #define PCI_EXP_LNKSTA_LT 0x800 /* Link Training */ #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ +#define PCI_EXP_SLTCAP_HPC 0x0040 /* Hot-Plug Capable */ #define PCI_EXP_SLTCTL 24 /* Slot Control */ #define PCI_EXP_SLTSTA 26 /* Slot Status */ #define PCI_EXP_RTCTL 28 /* Root Control */ diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h index 3a9825d871..44914063f6 100644 --- a/src/include/device/pciexp.h +++ b/src/include/device/pciexp.h @@ -26,5 +26,11 @@ void pciexp_scan_bridge(struct device *dev); extern struct device_operations default_pciexp_ops_bus; +#if CONFIG(PCIEXP_HOTPLUG) +void pciexp_hotplug_scan_bridge(struct device *dev); + +extern struct device_operations default_pciexp_hotplug_ops_bus; +#endif /* CONFIG(PCIEXP_HOTPLUG) */ + unsigned int pciexp_find_extended_cap(struct device *dev, unsigned int cap); #endif /* DEVICE_PCIEXP_H */ From 3f5f74d1349625fa33bcbdfd2956d1e36b3f236d Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Tue, 28 Jan 2020 19:53:01 -0800 Subject: [PATCH 077/151] mb/intel/tglrvp: pin mux for ISH TGL FSP does pin mux for ISH related to pins by UPD(PchIshSpiEnable, PchIshUartEnable, PchIshI2cEnable, PchIshGpEnable) but as default UPD value is disabled, FSP doesn't do pin mux. So pin mux for ISH in gpio.c. Pin mux for ISH for TGLRVP ISHUART0: GPP_D13, GPP_D14 as NF1 ISHI2C0: GPP_B5, GPP_B6 as NF1 ISHGPIO0-7: GPP_D0~D3, GPP_D17~D18, GPP_E15~E16 as NF1 BUG=none BRANCH=none TEST=Build and boot to OS and check pinctl driver to check pin mux. Check ISHUART0, ISHI2C0, ISHGPIO0-7 native function setting. They should be NF1. Signed-off-by: Wonkyu Kim Change-Id: I1a9ba3a713527f5ce962659960418cd0f37dd262 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38622 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- .../intel/tglrvp/variants/tglrvp_up3/gpio.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index d1dc4ca251..8638b806b6 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -32,6 +32,24 @@ static const struct pad_config gpio_table[] = { /* Image clock: IMGCLKOUT_0, IMGCLKOUT_1 */ PAD_CFG_NF(GPP_D4, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_H20, NONE, PLTRST, NF1), + + /* ISH UART0 RX/TX */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1), + + /* ISH I2C0 */ + PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF1), + + /* ISH GPI 0-6 */ + PAD_CFG_NF(GPP_D0, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D1, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D2, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D3, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D17, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_D18, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), }; /* Early pad configuration in bootblock */ From b48148f4b35dbf7fc36612cb933c133a37a69261 Mon Sep 17 00:00:00 2001 From: Amanda Huang Date: Tue, 4 Feb 2020 11:36:43 +0800 Subject: [PATCH 078/151] mb/google/hatch: Correct PCIe ports setting for mushu 1. Enable PCIe port for dGPU 2. Change WLAN PCIe port from port 14 to port 7 BUG=b:147249494 TEST=Ensure dGPU and WLAN shows up with lspci. Change-Id: Iea3292be7d8029c35847118228bbb773418632a1 Signed-off-by: Amanda Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/38399 Reviewed-by: Shelley Chen Tested-by: build bot (Jenkins) --- .../google/hatch/variants/mushu/overridetree.cb | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb index c623fde5ba..f50bab248d 100644 --- a/src/mainboard/google/hatch/variants/mushu/overridetree.cb +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -64,6 +64,21 @@ chip soc/intel/cannonlake }, }" + # PCIe port 7 for M.2 E-key WLAN + register "PcieRpEnable[6]" = "1" + register "PcieRpLtrEnable[6]" = "1" + # RP 7 uses CLK SRC 3 + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable Root port 13 (x4) for dGPU + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + # RP 13 uses CLK SRC 5 + register "PcieClkSrcUsage[5]" = "12" + # ClkReq-to-ClkSrc mapping for CLK SRC 5 + register "PcieClkSrcClkReq[5]" = "5" + # GPIO for SD card detect register "sdcard_cd_gpio" = "vSD3_CD_B" From a3d79292e7a6adc0c5dc4c53117feb5225bc6225 Mon Sep 17 00:00:00 2001 From: Kangheui Won Date: Fri, 24 Jan 2020 21:53:01 +1100 Subject: [PATCH 079/151] libpayload/xhci: Fix MPS handling in set_address We set MPS to speed_to_default_mps(speed) initially but later compare maxpacketsize with 8 to change mps. So compare with speed_to_default_mps(speed) to determine if we need to change settings here. BUG=b:147783572 BRANCH=none TEST=works with 12Mbps/8MPS USB device Signed-off-by: Kangheui Won Change-Id: I32455483fceec56f14af6118b77615c14b3f9f39 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38556 Reviewed-by: Edward O'Callaghan Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- payloads/libpayload/drivers/usb/xhci_devconf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/usb/xhci_devconf.c b/payloads/libpayload/drivers/usb/xhci_devconf.c index 3f50caa512..51ff29f5c8 100644 --- a/payloads/libpayload/drivers/usb/xhci_devconf.c +++ b/payloads/libpayload/drivers/usb/xhci_devconf.c @@ -227,7 +227,7 @@ xhci_set_address (hci_t *controller, usb_speed speed, int hubport, int hubaddr) } dev->endpoints[0].maxpacketsize = usb_decode_mps0(speed, buf[7]); - if (dev->endpoints[0].maxpacketsize != 8) { + if (dev->endpoints[0].maxpacketsize != speed_to_default_mps(speed)) { memset((void *)ic->dev.ep0, 0x00, ctxsize); *ic->add = (1 << 1); /* EP0 Context */ EC_SET(MPS, ic->dev.ep0, dev->endpoints[0].maxpacketsize); From 9c5263c9c705396113b9553440c1f9250d68bd95 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Sat, 1 Feb 2020 14:25:43 +0800 Subject: [PATCH 080/151] mb/google/drallion: Fine tune touch screen power sequence Follow HW change to use GPP_D15 as TS_RST. And change GPP_B21 from pltrst to deep in order to met power off timing. BUG=b:143733039 TEST=Check touch screen is functional in s0 and resume from s0ix Signed-off-by: Eric Lai Change-Id: Ieec7eb78a05e653f271e348ed11f7e31c08bd5dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/38665 Reviewed-by: Duncan Laurie Tested-by: build bot (Jenkins) --- .../drallion/variants/drallion/devicetree.cb | 17 +++++++++++++++-- .../google/drallion/variants/drallion/gpio.c | 4 ++-- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 97860f4b2d..06d3e5dd26 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -336,9 +336,15 @@ chip soc/intel/cannonlake register "generic.desc" = ""Wacom Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "5" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "20" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" @@ -352,6 +358,10 @@ chip soc/intel/cannonlake register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "10" + register "generic.reset_off_delay_ms" = "5" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "generic.stop_delay_ms" = "10" @@ -369,6 +379,9 @@ chip soc/intel/cannonlake register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "5" register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" register "stop_delay_ms" = "10" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index f2b70792f7..1c864caff7 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -78,7 +78,7 @@ static const struct pad_config gpio_table[] = { /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), -/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* PCH_3.3V_TS_EN */ +/* GSPI1_MISO */ PAD_CFG_GPO(GPP_B21, 0, DEEP), /* PCH_3.3V_TS_EN */ /* GSPI1_MOSI */ PAD_NC(GPP_B22, NONE), /* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), @@ -124,7 +124,7 @@ static const struct pad_config gpio_table[] = { /* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1), /* ISH_CPU_UART0_TX */ /* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), -/* ISH_UART0_RTS# */ PAD_NC(GPP_D15, NONE), +/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* TS_RST */ /* ISH_UART0_CTS# */ PAD_CFG_GPI(GPP_D16, NONE, PLTRST), /* DMIC_CLK1 */ PAD_CFG_GPI(GPP_D17, NONE, PLTRST), /* KB_DET# */ /* DMIC_DATA1 */ PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST, From d498e52c3f024971f342da9029fd7f11668c0a3d Mon Sep 17 00:00:00 2001 From: Evgeny Zinoviev Date: Fri, 8 Nov 2019 05:20:20 +0300 Subject: [PATCH 081/151] Documentation: xx30 ThinkPads internal flashing Add detailed instructions on how to unlock protected SPI ranges and flash coreboot internally on Lenovo ThinkPad Ivy Bridge series by exploiting stock BIOS security issues. Change-Id: I8d8551910c31fd2e6ff728e17dafaea45970166b Signed-off-by: Evgeny Zinoviev Reviewed-on: https://review.coreboot.org/c/coreboot/+/36666 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- Documentation/mainboard/index.md | 1 + .../mainboard/lenovo/ivb_bios_flashing1.jpg | Bin 0 -> 62320 bytes .../mainboard/lenovo/ivb_bios_flashing2.jpg | Bin 0 -> 58984 bytes .../mainboard/lenovo/ivb_bios_legacy_only.jpg | Bin 0 -> 64404 bytes .../mainboard/lenovo/ivb_bios_uefi_only.jpg | Bin 0 -> 63883 bytes .../mainboard/lenovo/ivb_internal_flashing.md | 372 ++++++++++++++++++ 6 files changed, 373 insertions(+) create mode 100644 Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg create mode 100644 Documentation/mainboard/lenovo/ivb_bios_flashing2.jpg create mode 100644 Documentation/mainboard/lenovo/ivb_bios_legacy_only.jpg create mode 100644 Documentation/mainboard/lenovo/ivb_bios_uefi_only.jpg create mode 100644 Documentation/mainboard/lenovo/ivb_internal_flashing.md diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index a0436afb1f..ce30ee2f1c 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -92,6 +92,7 @@ The boards in this section are not real mainboards, but emulators. - [W530](lenovo/w530.md) - [T430 / T530 / X230 / W530 common](lenovo/xx30_series.md) - [T431s](lenovo/t431s.md) +- [Internal flashing](lenovo/ivb_internal_flashing.md) ### Haswell series diff --git a/Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg b/Documentation/mainboard/lenovo/ivb_bios_flashing1.jpg new file mode 100644 index 0000000000000000000000000000000000000000..10a27b08e39d28b73d9418d601f93004103562a8 GIT binary patch literal 62320 zcmb4JRa6{Ju%5-;0>K>uizZlbw_V&FlAw!Qa8J;ni-zFt!6gI_ngm;1g1fuJ<$t*6 z+}B&DA7-YzzN#})Q&nF-%{(mw1W`R!1^!o%K}aZQ04h2L zCf4)35di>t_8aNhZ4_*5OmtKb==m5xB}5~lM}PA|N&|zK;XRK_aKab~qjWCjOHy9V z53cZY&ciC=9rPUYixyy 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+# Ivy Bridge Lenovo ThinkPad Internal Flashing + +## Introduction + +Old versions of stock BIOS for these models have several security issues. +In order to flash coreboot internally, two of them are of interest. + +**First** is the fact the SMM_BWP and BLE are not enabled in BIOS +versions released before 2014. We have tested many versions on T430 and +X230 and found out that SMM_BWP=1 only since the update, the changelog +of which contains following line: + +> (New) Improved the UEFI BIOS security feature. + +**Second** is [S3 Boot Script vulnerability](https://support.lenovo.com/eg/ru/product_security/s3_boot_protect), +that was discovered and fixed later. + +## Requirements + +- USB drive (in case you need to downgrade BIOS) +- Linux install that (can be) loaded in UEFI mode +- [CHIPSEC](https://github.com/chipsec/chipsec) + +## BIOS versions + +Below is a table of BIOS versions that are vulnerable enough for our +goals, per model. The version number means that you need to downgrade to +that or earlier version. + +```eval_rst ++------------+--------------+ +| Model | BIOS version | ++============+==============+ +| X230 | 2.60 | ++------------+--------------+ +| X230T | 2.58 | ++------------+--------------+ +| T430 | 2.64 | ++------------+--------------+ +| T430s | 2.59 | ++------------+--------------+ +| T530 | 2.60 | ++------------+--------------+ +| W530 | 2.58 | ++------------+--------------+ +``` + +If your BIOS version is equal or lower, skip to the +**[Examining protections](#examining-protections-theory)** section. If not, +go through the downgrade process, described next. + +## Downgrading BIOS + +Go to the Lenovo web site and download BIOS Update Bootable CD for your +machine of needed version (see above). + +Lenovo states that BIOS has "security rollback prevention", meaning once +you update it to some version X, you will not be able to downgrade it to +pre-X version. That's not true. It seems that this is completely +client-side restriction in flashing utilities (both Windows utility and +Bootable CD). You just need to call `winflash.exe` or `dosflash.exe` +directly. Therefore you need to modify the bootable CD image you just +downloaded. + +Extract an El Torito image: +``` +geteltorito -o ./bios.img g1uj41us.iso +``` +Mount the partition in that image: +``` +sudo mount -t vfat ./bios.img /mnt -o loop,offset=16384 +``` +List files, find the `AUTOEXEC.BAT` file and the `FLASH` directory: +``` +ls /mnt +ls /mnt/FLASH +``` + +Inside the `FLASH` directory, there should be a directory called +`G1ET93WW` or similar (exact name depends on your ThinkPad model and +BIOS version). See what's inside: +``` +ls /mnt/FLASH/G1ET93WW +``` +There must be a file with `.FL1` extension called `$01D2000.FL1` or +something similar. + +Now open the `AUTOEXEC.BAT` file: +``` +sudo vim /mnt/AUTOEXEC.BAT +``` +You will see a list of commands: +``` +@ECHO OFF +PROMPT $p$g +cd c:\flash +command.com +``` +Replace the last line (`command.com`) with this (change path to the +`.FL1` file according to yours): +``` +dosflash.exe /sd /file G1ET93WW\$01D2000.FL1 +``` + +Save the file, then unmount the partition: +``` +sudo unmount /mnt +``` + +Write this image to a USB drive (replace `/dev/sdX` with your USB drive +device name): +``` +sudo dd if=./bios.img of=/dev/sdX bs=1M +``` + +Now reboot and press F1 to enter BIOS settings. Open the **Startup** tab +and set the startup mode to **Legacy** (or **Both**/**Legacy First**): + +![](ivb_bios_legacy_only.jpg) + +Press F10 to save changes and reboot. + +Now, before you process, make sure that AC adapter is connected! If your +battery will die during the process, you'll likely need external +programmer to recover. + +Boot from the USB drive (press F12 to select boot device), and BIOS +flashing process should begin: + +![](ivb_bios_flashing1.jpg) + +![](ivb_bios_flashing2.jpg) + +It may reboot a couple of times in the process. Do not interrupt it. + +When it's completed, go back to the BIOS settings and set startup mode +to **UEFI** (or **Both**/**UEFI First**). This is required for +vulnerability exploitation. + +![](ivb_bios_uefi_only.jpg) + +Then boot to your system and make sure that `/sys/firmware/efi` or +`/sys/firmware/efivars` exist. + +## Examining protections (theory) + +There are two main ways that Intel platform provides to protect BIOS +chip: +- **BIOS_CNTL** register of LPC Interface Bridge Registers (accessible + via PCI configuration space, offset 0xDC). It has: + * **SMM_BWP** (*SMM BIOS Write Protect*) bit. If set to 1, the BIOS is + writable only in SMM. Once set to 1, cannot be changed anymore. + * **BLE** (*BIOS Lock Enable*) bit. If set to 1, setting BIOSWE to 1 + will raise SMI. Once set to 1, cannot be changed anymore. + * **BIOSWE** (*BIOS Write Enable*) bit. Controls whether BIOS is + writable. This bit is always R/W. +- SPI Protected Range Registers (**PR0**-**PR4**) of SPI Configuration + Registers (SPIBAR+0x74 - SPIBAR+0x84). Each register has bits that + define protected range, plus WP bit, that defines whether write + protection is enabled. + + There's also **FLOCKDN** bit of HSFS register (SPIBAR+0x04) of SPI + Configuration Registers. When set to 1, PR0-PR4 registers cannot be + written. Once set to 1, cannot be changed anymore. + +To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or +SPI protected ranges (PRx) to have a WP bit set to 0. + +Let's see what we have. Examine HSFS register: +``` +sudo chipsec_main -m chipsec.modules.common.spi_lock +``` +You should see that FLOCKDN=1: +``` +[x][ ======================================================================= +[x][ Module: SPI Flash Controller Configuration Locks +[x][ ======================================================================= +[*] HSFS = 0xE009 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) + [00] FDONE = 1 << Flash Cycle Done + [01] FCERR = 0 << Flash Cycle Error + [02] AEL = 0 << Access Error Log + [03] BERASE = 1 << Block/Sector Erase Size + [05] SCIP = 0 << SPI cycle in progress + [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status + [14] FDV = 1 << Flash Descriptor Valid + [15] FLOCKDN = 1 << Flash Configuration Lock-Down +``` + +Then check BIOS_CNTL and PR0-PR4: +``` +sudo chipsec_main -m common.bios_wp +``` +Good news: on old BIOS versions, SMM_BWP=0 and BLE=0. + +Bad news: there are 4 write protected SPI ranges: + +``` +[x][ ======================================================================= +[x][ Module: BIOS Region Write Protection +[x][ ======================================================================= +[*] BC = 0x 8 << BIOS Control (b:d.f 00:31.0 + 0xDC) + [00] BIOSWE = 0 << BIOS Write Enable + [01] BLE = 0 << BIOS Lock Enable + [02] SRC = 2 << SPI Read Configuration + [04] TSS = 0 << Top Swap Status + [05] SMM_BWP = 0 << SMM BIOS Write Protection +[-] BIOS region write protection is disabled! + +[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF +SPI Protected Ranges +------------------------------------------------------------ +PRx (offset) | Value | Base | Limit | WP? | RP? +------------------------------------------------------------ +PR0 (74) | 00000000 | 00000000 | 00000000 | 0 | 0 +PR1 (78) | 8BFF0B40 | 00B40000 | 00BFFFFF | 1 | 0 +PR2 (7C) | 8B100B10 | 00B10000 | 00B10FFF | 1 | 0 +PR3 (80) | 8ADE0AD0 | 00AD0000 | 00ADEFFF | 1 | 0 +PR4 (84) | 8AAF0800 | 00800000 | 00AAFFFF | 1 | 0 +``` + +Other way to examine SPI configuration registers is to just dump SPIBAR: +``` +sudo chipsec_util mmio dump SPIBAR +``` +You will see SPIBAR address (0xFED1F800) and registers (for example, +00000004 is HSFS): +``` +[mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]: ++00000000: 0BFF0500 ++00000004: 0004E009 +... +``` +As you can see, the only thing we need is to unset WP bit on PR0-PR4. +But that cannot be done once FLOCKDN is set to 1. + +Now the fun part! + +FLOCKDN may only be cleared by a hardware reset, which includes S3 +state. On S3 resume boot path, the chipset configuration has to be +restored and it's done by executing so-called S3 Boot Scripts. You can +dump these scripts by executing: +``` +sudo chipsec_util uefi s3bootscript +``` +There are many entries. Along them, you can find instructions to write +to HSFS (remember, we know that SPIBAR is 0xFED1F800): +``` +Entry at offset 0x2B8F (len = 0x17, header len = 0x0): +Data: +02 00 17 02 00 00 00 01 00 00 00 04 f8 d1 fe 00 | +00 00 00 09 e0 04 00 | +Decoded: + Opcode : S3_BOOTSCRIPT_MEM_WRITE (0x0002) + Width : 0x02 (4 bytes) + Address: 0xFED1F804 + Count : 0x1 + Values : 0x0004E009 +``` +These scripts are stored in memory. The vulnerability is that we can +overwrite this memory, change these instructions and they will be +executed on S3 resume. Once we patch that instruction to not set FLOCKDN +bit, we will be able to write to PR0-PR4 registers. + +## Creating a backup + +Before you proceed, please create a backup of the `bios` region. Then, +in case something goes wrong, you'll be able to flash it back externally. + +The `me` region is locked, so an attempt to create a full dump will fail. +But you can back up the `bios`: +``` +sudo flashrom -p internal -r bios_backup.rom --ifd -i bios +``` + +If you will ever need to flash it back, use `--ifd -i bios` as well: +``` +sudo flashrom -p -w bios_backup.rom --ifd -i bios +``` +**Caution:** if you will omit `--ifd -i bios` for flashing, you will +brick your machine, because your backup has `FF`s in place of `fd` and +`me` regions. Flash only `bios` region! + +## Removing protections (practice) + +The original boot script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so +let's write 0x6009 instead: +``` +sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2 +``` +You will get a lot of output and in the end you should see something +like this: +``` +[*] Modifying S3 boot script entry at address 0x00000000DAF49B8F.. +[mem] 0x00000000DAF49B8F +[*] Original entry: + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 e0 4 0 | +[mem] buffer len = 0x17 to PA = 0x00000000DAF49B8F + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 60 0 0 | ` +[mem] 0x00000000DAF49B8F +[*] Modified entry: + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 60 0 0 | ` +[*] After sleep/resume, check the value of register 0xFED1F804 is 0x6009 +[+] PASSED: The script has been modified. Go to sleep.. +``` +Now go to S3, then resume and check FLOCKDN. It should be 0: +``` +sudo chipsec_main -m chipsec.modules.common.spi_lock +``` +``` +... +[x][ ======================================================================= +[x][ Module: SPI Flash Controller Configuration Locks +[x][ ======================================================================= +[*] HSFS = 0x6008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) + [00] FDONE = 0 << Flash Cycle Done + [01] FCERR = 0 << Flash Cycle Error + [02] AEL = 0 << Access Error Log + [03] BERASE = 1 << Block/Sector Erase Size + [05] SCIP = 0 << SPI cycle in progress + [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status + [14] FDV = 1 << Flash Descriptor Valid + [15] FLOCKDN = 0 << Flash Configuration Lock-Down +[-] SPI Flash Controller configuration is not locked +[-] FAILED: SPI Flash Controller not locked correctly. +... +``` +Remove WP from protected ranges: +``` +sudo chipsec_util mmio write SPIBAR 0x74 0x4 0xAAF0800 +sudo chipsec_util mmio write SPIBAR 0x78 0x4 0xADE0AD0 +sudo chipsec_util mmio write SPIBAR 0x7C 0x4 0xB100B10 +sudo chipsec_util mmio write SPIBAR 0x80 0x4 0xBFF0B40 +``` +Verify that it worked: +``` +sudo chipsec_main -m common.bios_wp +``` +``` +[x][ ======================================================================= +[x][ Module: BIOS Region Write Protection +[x][ ======================================================================= +[*] BC = 0x 9 << BIOS Control (b:d.f 00:31.0 + 0xDC) + [00] BIOSWE = 1 << BIOS Write Enable + [01] BLE = 0 << BIOS Lock Enable + [02] SRC = 2 << SPI Read Configuration + [04] TSS = 0 << Top Swap Status + [05] SMM_BWP = 0 << SMM BIOS Write Protection +[-] BIOS region write protection is disabled! + +[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF +SPI Protected Ranges +------------------------------------------------------------ +PRx (offset) | Value | Base | Limit | WP? | RP? +------------------------------------------------------------ +PR0 (74) | 0AAF0800 | 00800000 | 00AAF000 | 0 | 0 +PR1 (78) | 0ADE0AD0 | 00AD0000 | 00ADE000 | 0 | 0 +PR2 (7C) | 0B100B10 | 00B10000 | 00B10000 | 0 | 0 +PR3 (80) | 0BFF0B40 | 00B40000 | 00BFF000 | 0 | 0 +PR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0 +``` + +Bingo! + +Now you can [flash internally](/flash_tutorial/int_flashrom.md). +Remember to flash only the `bios` region (use `--ifd -i bios -N` +flashrom arguments). `fd` and `me` are still locked. + +Note that you should have an external SPI programmer as a backup method. +It will help you recover if you flash non-working ROM by mistake. From ae438be57856e994774ec0e2521d49f1ad09bd6f Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Tue, 21 Jan 2020 17:01:47 -0500 Subject: [PATCH 082/151] security/intel/stm: Add STM support This update is a combination of all four of the patches so that the commit can be done without breaking parts of coreboot. This possible breakage is because of the cross-dependencies between the original separate patches would cause failure because of data structure changes. security/intel/stm This directory contains the functions that check and move the STM to the MSEG, create its page tables, and create the BIOS resource list. The STM page tables is a six page region located in the MSEG and are pointed to by the CR3 Offset field in the MSEG header. The initial page tables will identity map all memory between 0-4G. The STM starts in IA32e mode, which requires page tables to exist at startup. The BIOS resource list defines the resources that the SMI Handler is allowed to access. This includes the SMM memory area where the SMI handler resides and other resources such as I/O devices. The STM uses the BIOS resource list to restrict the SMI handler's accesses. The BIOS resource list is currently located in the same area as the SMI handler. This location is shown in the comment section before smm_load_module in smm_module_loader.c Note: The files within security/intel/stm come directly from their Tianocore counterparts. Unnecessary code has been removed and the remaining code has been converted to meet coreboot coding requirements. For more information see: SMI Transfer Monitor (STM) User Guide, Intel Corp., August 2015, Rev 1.0, can be found at firmware.intel.com include/cpu/x86: Addtions to include/cpu/x86 for STM support. cpu/x86: STM Set up - The STM needs to be loaded into the MSEG during BIOS initialization and the SMM Monitor Control MSR be set to indicate that an STM is in the system. cpu/x86/smm: SMI module loader modifications needed to set up the SMM descriptors used by the STM during its initialization Change-Id: If4adcd92c341162630ce1ec357ffcf8a135785ec Signed-off-by: Eugene D. Myers Reviewed-on: https://review.coreboot.org/c/coreboot/+/33234 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi Reviewed-by: ron minnich --- configs/config.stm | 4 + src/cpu/x86/mp_init.c | 34 + src/cpu/x86/smm/smm_module_loader.c | 19 +- src/cpu/x86/smm/smm_stub.S | 13 + src/include/cpu/x86/msr.h | 10 + src/include/cpu/x86/smm.h | 3 + src/security/intel/Kconfig | 1 + src/security/intel/Makefile.inc | 1 + src/security/intel/stm/Kconfig | 49 ++ src/security/intel/stm/Makefile.inc | 10 + src/security/intel/stm/SmmStm.c | 691 ++++++++++++++++++ src/security/intel/stm/SmmStm.h | 120 +++ src/security/intel/stm/StmApi.h | 726 +++++++++++++++++++ src/security/intel/stm/StmPlatformResource.c | 188 +++++ src/security/intel/stm/StmPlatformResource.h | 32 + src/security/intel/stm/StmPlatformSmm.c | 204 ++++++ 16 files changed, 2104 insertions(+), 1 deletion(-) create mode 100644 configs/config.stm create mode 100644 src/security/intel/stm/Kconfig create mode 100644 src/security/intel/stm/Makefile.inc create mode 100644 src/security/intel/stm/SmmStm.c create mode 100644 src/security/intel/stm/SmmStm.h create mode 100644 src/security/intel/stm/StmApi.h create mode 100644 src/security/intel/stm/StmPlatformResource.c create mode 100644 src/security/intel/stm/StmPlatformResource.h create mode 100644 src/security/intel/stm/StmPlatformSmm.c diff --git a/configs/config.stm b/configs/config.stm new file mode 100644 index 0000000000..59792b2fa5 --- /dev/null +++ b/configs/config.stm @@ -0,0 +1,4 @@ +CONFIG_VENDOR_PURISM=y +CONFIG_BOARD_PURISM_LIBREM15_V4=y +CONFIG_STM=y +CONFIG_IED_REGION_SIZE=0 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index b093be7003..331f3b552a 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -38,6 +38,8 @@ #include #include +#include + #define MAX_APIC_IDS 256 struct mp_callback { @@ -743,6 +745,23 @@ static void asmlinkage smm_do_relocation(void *arg) /* Setup code checks this callback for validity. */ mp_state.ops.relocation_handler(cpu, curr_smbase, perm_smbase); + + if (CONFIG(STM)) { + if (is_smm_enabled()) { + uintptr_t mseg; + + mseg = mp_state.perm_smbase + + (mp_state.perm_smsize - CONFIG_MSEG_SIZE); + + stm_setup(mseg, p->cpu, runtime->num_cpus, + perm_smbase, + mp_state.perm_smbase, + runtime->start32_offset); + } else { + printk(BIOS_DEBUG, + "STM not loaded because SMM is not enabled!\n"); + } + } } static void adjust_smm_apic_id_map(struct smm_loader_params *smm_params) @@ -1022,6 +1041,21 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) ops->get_smm_info(&state->perm_smbase, &state->perm_smsize, &state->smm_save_state_size); + /* + * Make sure there is enough room for the SMM descriptor + */ + if (CONFIG(STM)) + state->smm_save_state_size += + sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); + + /* Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (align on 4K) + * note: In the future, this will need to handle newer x86 processors + * that require alignment of the save state on 32K boundaries. + */ + state->smm_save_state_size = + ALIGN_UP(state->smm_save_state_size, 0x1000); + /* * Default to smm_initiate_relocation() if trigger callback isn't * provided. diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index c6c6b38737..a421436893 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -17,6 +17,7 @@ #include #include #include +#include #define FXSAVE_SIZE 512 @@ -267,6 +268,7 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params, stub_params->fxsave_area_size = FXSAVE_SIZE; stub_params->runtime.smbase = (uintptr_t)smbase; stub_params->runtime.save_state_size = params->per_cpu_save_state_size; + stub_params->runtime.num_cpus = params->num_concurrent_stacks; /* Initialize the APIC id to CPU number table to be 1:1 */ for (i = 0; i < params->num_concurrent_stacks; i++) @@ -313,6 +315,11 @@ int smm_setup_relocation_handler(struct smm_loader_params *params) * +-----------------+ <- smram + size * | stacks | * +-----------------+ <- smram + size - total_stack_size + * | fxsave area | + * +-----------------+ <- smram + size - total_stack_size - fxsave_size + * | BIOS resource | + * | list (STM) | + * +-----------------+ <- .. - CONFIG_BIOS_RESOURCE_LIST_SIZE * | ... | * +-----------------+ <- smram + handler_size + SMM_DEFAULT_SIZE * | handler | @@ -353,7 +360,12 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Stacks start at the top of the region. */ base = smram; - base += size; + + if (CONFIG(STM)) + base += size - CONFIG_MSEG_SIZE; // take out the mseg + else + base += size; + params->stack_top = base; /* SMM module starts at offset SMM_DEFAULT_SIZE with the load alignment @@ -382,6 +394,11 @@ int smm_load_module(void *smram, size_t size, struct smm_loader_params *params) /* Does the required amount of memory exceed the SMRAM region size? */ total_size = total_stack_size + handler_size; total_size += fxsave_size + SMM_DEFAULT_SIZE; + + // account for the bios resource list + if (CONFIG(STM)) + total_size += CONFIG_BIOS_RESOURCE_LIST_SIZE; + if (total_size > size) return -1; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index f0e55f9a18..8207d233a0 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -44,6 +44,11 @@ smbase: .long 0 save_state_size: .long 0 +num_cpus: +.long 0 +/* allows the STM to bring up SMM in 32-bit mode */ +start32_offset: +.long smm_trampoline32 - _start /* apic_to_cpu_num is a table mapping the default APIC id to CPU num. If the * APIC id is found at the given index, the contiguous CPU number is index * into the table. */ @@ -90,6 +95,14 @@ smm_relocate_gdt: /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 + + /* gdt selector 0x18, flat code segment (64-bit) */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 + + /* gdt selector 0x20 tss segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x8b, 0x80, 0x00 smm_relocate_gdt_end: .align 4 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 63cb8bde28..49abd41c00 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -16,6 +16,7 @@ /* Page attribute type MSR */ #define TSC_MSR 0x10 #define IA32_PLATFORM_ID 0x17 +#define IA32_APIC_BASE_MSR_INDEX 0x1B #define IA32_FEATURE_CONTROL 0x3a #define FEATURE_CONTROL_LOCK_BIT (1 << 0) #define FEATURE_ENABLE_VMX (1 << 2) @@ -30,6 +31,10 @@ #define IA32_BIOS_SIGN_ID 0x8b #define IA32_MPERF 0xe7 #define IA32_APERF 0xe8 +/* STM */ +#define IA32_SMM_MONITOR_CTL_MSR 0x9B +#define SMBASE_RO_MSR 0x98 +#define IA32_SMM_MONITOR_VALID (1 << 0) #define IA32_MCG_CAP 0x179 #define MCG_CTL_P (1 << 3) #define MCA_BANKS_MASK 0xff @@ -45,6 +50,9 @@ #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define IA32_PLATFORM_DCA_CAP 0x1f8 +#define SMRR_PHYSBASE_MSR 0x1F2 +#define SMRR_PHYSMASK_MSR 0x1F3 +#define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_PAT 0x277 #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 @@ -65,6 +73,8 @@ #define MCA_STATUS_LO_ERRCODE_EXT_SH 16 #define MCA_STATUS_LO_ERRCODE_EXT_MASK (0x3f << MCA_STATUS_LO_ERRCODE_EXT_SH) #define MCA_STATUS_LO_ERRCODE_MASK (0xffff << 0) +#define IA32_VMX_BASIC_MSR 0x480 +#define IA32_VMX_MISC_MSR 0x485 #define MC0_ADDR 0x402 #define MC0_MISC 0x403 #define MC0_CTL_MASK 0xC0010044 diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index cf107b121a..9efe2e04eb 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -64,6 +64,9 @@ extern unsigned char _binary_smm_end[]; struct smm_runtime { u32 smbase; u32 save_state_size; + u32 num_cpus; + /* STM's 32bit entry into SMI handler */ + u32 start32_offset; /* The apic_id_to_cpu provides a mapping from APIC id to CPU number. * The CPU number is indicated by the index into the array by matching * the default APIC id and value at the index. The stub loader diff --git a/src/security/intel/Kconfig b/src/security/intel/Kconfig index a4525e7b9b..aa24e8ac68 100644 --- a/src/security/intel/Kconfig +++ b/src/security/intel/Kconfig @@ -14,3 +14,4 @@ ## source "src/security/intel/txt/Kconfig" +source "src/security/intel/stm/Kconfig" diff --git a/src/security/intel/Makefile.inc b/src/security/intel/Makefile.inc index 9388d3f798..e00802ad06 100644 --- a/src/security/intel/Makefile.inc +++ b/src/security/intel/Makefile.inc @@ -1 +1,2 @@ subdirs-y += txt +subdirs-y += stm diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig new file mode 100644 index 0000000000..a74eba8522 --- /dev/null +++ b/src/security/intel/stm/Kconfig @@ -0,0 +1,49 @@ + + +config STM + bool "Enable STM" + default n + depends on SMM_TSEG + select USE_BLOBS + + help + Enabling the STM will load a simple hypervisor into SMM that will + restrict the actions of the SMI handler, which is the part of BIOS + that functions in system management mode (SMM). The kernel can + configure the STM to prevent the SMI handler from accessing platform + resources. + The STM closes a vulnerability in Intel TXT (D-RTM) + The SMI handler provides a list of platform resources that it + requires access to the STM during STM startup, which the kernel + cannot override. + An additional capability, called STM-PE, provides a protected + execution capability that allows modules to be executed without + observation and interference. Examples of usage include kernel + introspection and virtualized trusted platform module (vTPM). + Requirement: SMM must be enabled and there must be sufficient room + within the TSEG to fit the MSEG. + +if STM + +menu "SMI Transfer Monitor (STM)" + +config MSEG_SIZE + hex "mseg size" + default 0x400000 + help + STM only - 0x100000 + STM/PE - 0x300000+ depending on the amount of memory needed + for the protected execution virtual + machine (VM/PE) + +config BIOS_RESOURCE_LIST_SIZE + hex "bios_resource_list_size" + default 0x1000 + +config STM_BINARY_FILE + string "STM binary file" + default "3rdparty/blobs/cpu/intel/stm/stm.bin" + +endmenu #STM + +endif diff --git a/src/security/intel/stm/Makefile.inc b/src/security/intel/stm/Makefile.inc new file mode 100644 index 0000000000..1a23fe97f2 --- /dev/null +++ b/src/security/intel/stm/Makefile.inc @@ -0,0 +1,10 @@ + +# put the stm where it can be found + +cbfs-files-$(CONFIG_STM) += stm.bin +stm.bin-file := $(CONFIG_STM_BINARY_FILE) +stm.bin-type := raw + +ramstage-$(CONFIG_STM) += SmmStm.c +ramstage-$(CONFIG_STM) += StmPlatformSmm.c +ramstage-$(CONFIG_STM) += StmPlatformResource.c diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c new file mode 100644 index 0000000000..f23be70217 --- /dev/null +++ b/src/security/intel/stm/SmmStm.c @@ -0,0 +1,691 @@ +/* @file + * SMM STM support + * + * Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + * + * This program and the accompanying materials are licensed and made available + * under the terms and conditions of the BSD License which accompanies this + * distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php. + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define TXT_EVTYPE_BASE 0x400 +#define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +#define SIZE_4KB 0x00001000 +#define SIZE_4MB 0x00400000 + +#define PTP_SIZE SIZE_4KB + +#define IA32_PG_P (1 << 0) +#define IA32_PG_RW (1 << 1) +#define IA32_PG_PS (1 << 7) + +#define STM_PAGE_SHIFT 12 +#define STM_PAGE_MASK 0xFFF +#define STM_SIZE_TO_PAGES(a) \ + (((a) >> STM_PAGE_SHIFT) + (((a)&STM_PAGE_MASK) ? 1 : 0)) +#define STM_PAGES_TO_SIZE(a) ((a) << STM_PAGE_SHIFT) + +#define STM_ACCESS_DENIED 15 +#define STM_UNSUPPORTED 3 + +#define STM_BUFFER_TOO_SMALL 1 + +#define STM_SM_MONITOR_STATE_ENABLED 1 + +typedef struct { + + uint64_t vmcs_revision_id : 31; + uint64_t always_zero : 1; + uint64_t vmcs_size : 13; + uint64_t reserved1 : 3; + uint64_t vmxon_add_width : 1; + uint64_t stm_supported : 1; + uint64_t vmcs_memory_type : 4; + uint64_t in_out_reporting : 1; + uint64_t may_clear_defaults : 1; + uint64_t reserved2 : 8; +} VMX_BASIC_MSR_BITS; + +typedef union { + VMX_BASIC_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} VMX_BASIC_MSR; + +typedef struct { + uint64_t valid : 1; + uint64_t reserved1 : 1; + uint64_t vmx_off_blockSmi : 1; + uint64_t reserved2 : 9; + uint64_t mseg_address : 20; + uint64_t reserved3 : 32; +} SMM_MONITOR_CTL_MSR_BITS; + +extern struct mp_state { + struct mp_ops ops; + int cpu_count; + uintptr_t perm_smbase; + size_t perm_smsize; + size_t smm_save_state_size; + int do_smm; +} mp_state; + +typedef union { + SMM_MONITOR_CTL_MSR_BITS bits; + uint64_t uint64; + msr_t msr; +} SMM_MONITOR_CTL_MSR; + +// Template of STM_RSC_END structure for copying. + +STM_RSC_END m_rsc_end_node = { + {END_OF_RESOURCES, sizeof(STM_RSC_END)}, +}; + +uint8_t *m_stm_resources_ptr = NULL; +uint32_t m_stm_resource_total_size = 0x0; +uint32_t m_stm_resource_size_used = 0x0; +uint32_t m_stm_resource_size_available = 0x0; + +uint8_t *stm_resource_heap = NULL; + +uint32_t m_stm_state = 0; + +/* + * Handle single Resource to see if it can be merged into Record. + * + * @param resource A pointer to resource node to be added + * @param record A pointer to record node to be merged + * + * @retval true resource handled + * @retval false resource is not handled + */ + +static bool handle_single_resource(STM_RSC *resource, STM_RSC *record) +{ + uint64_t resource_lo = 0; + uint64_t resource_hi = 0; + uint64_t record_lo = 0; + uint64_t record_hi = 0; + + // Calling code is responsible for making sure that + // Resource->Header.RscType == (*Record)->Header.RscType + // thus we use just one of them as switch variable. + + switch (resource->header.rsc_type) { + case MEM_RANGE: + case MMIO_RANGE: + resource_lo = resource->mem.base; + resource_hi = resource->mem.base + resource->mem.length; + record_lo = record->mem.base; + record_hi = record->mem.base + record->mem.length; + if (resource->mem.rwx_attributes + != record->mem.rwx_attributes) { + if ((resource_lo == record_lo) + && (resource_hi == record_hi)) { + record->mem.rwx_attributes = + resource->mem.rwx_attributes + | record->mem.rwx_attributes; + return true; + } else { + return false; + } + } + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + resource_lo = (uint64_t)resource->io.base; + resource_hi = (uint64_t)resource->io.base + + (uint64_t)resource->io.length; + record_lo = (uint64_t)record->io.base; + record_hi = + (uint64_t)record->io.base + (uint64_t)record->io.length; + break; + case PCI_CFG_RANGE: + if ((resource->pci_cfg.originating_bus_number + != record->pci_cfg.originating_bus_number) + || (resource->pci_cfg.last_node_index + != record->pci_cfg.last_node_index)) + return false; + + if (memcmp(resource->pci_cfg.pci_device_path, + record->pci_cfg.pci_device_path, + sizeof(STM_PCI_DEVICE_PATH_NODE) + * (resource->pci_cfg.last_node_index + 1)) + != 0) { + return false; + } + resource_lo = (uint64_t)resource->pci_cfg.base; + resource_hi = (uint64_t)resource->pci_cfg.base + + (uint64_t)resource->pci_cfg.length; + record_lo = (uint64_t)record->pci_cfg.base; + record_hi = (uint64_t)record->pci_cfg.base + + (uint64_t)record->pci_cfg.length; + if (resource->pci_cfg.rw_attributes + != record->pci_cfg.rw_attributes) { + if ((resource_lo == record_lo) + && (resource_hi == record_hi)) { + record->pci_cfg.rw_attributes = + resource->pci_cfg.rw_attributes + | record->pci_cfg.rw_attributes; + return true; + } else { + return false; + } + } + break; + case MACHINE_SPECIFIC_REG: + + // Special case - merge MSR masks in place. + if (resource->msr.msr_index != record->msr.msr_index) + return false; + record->msr.read_mask |= resource->msr.read_mask; + record->msr.write_mask |= resource->msr.write_mask; + return true; + default: + return false; + } + + // If resources are disjoint + if ((resource_hi < record_lo) || (resource_lo > record_hi)) + return false; + + // If resource is consumed by record. + if ((resource_lo >= record_lo) && (resource_hi <= record_hi)) + return true; + + // Resources are overlapping. + // Resource and record are merged. + resource_lo = (resource_lo < record_lo) ? resource_lo : record_lo; + resource_hi = (resource_hi > record_hi) ? resource_hi : record_hi; + + switch (resource->header.rsc_type) { + case MEM_RANGE: + case MMIO_RANGE: + record->mem.base = resource_lo; + record->mem.length = resource_hi - resource_lo; + break; + case IO_RANGE: + case TRAPPED_IO_RANGE: + record->io.base = (uint64_t)resource_lo; + record->io.length = (uint64_t)(resource_hi - resource_lo); + break; + case PCI_CFG_RANGE: + record->pci_cfg.base = (uint64_t)resource_lo; + record->pci_cfg.length = (uint64_t)(resource_hi - resource_lo); + break; + default: + return false; + } + + return true; +} + +/* + * Add resource node. + * + * @param Resource A pointer to resource node to be added + */ +static void add_single_resource(STM_RSC *resource) +{ + STM_RSC *record; + + record = (STM_RSC *)m_stm_resources_ptr; + + while (true) { + if (record->header.rsc_type == END_OF_RESOURCES) + break; + + // Go to next record if resource and record types don't match. + if (resource->header.rsc_type != record->header.rsc_type) { + record = (STM_RSC *)((void *)record + + record->header.length); + continue; + } + + // Record is handled inside of procedure - don't adjust. + if (handle_single_resource(resource, record)) + return; + record = (STM_RSC *)((void *)record + record->header.length); + } + + // Add resource to the end of area. + memcpy(m_stm_resources_ptr + m_stm_resource_size_used + - sizeof(m_rsc_end_node), + resource, resource->header.length); + memcpy(m_stm_resources_ptr + m_stm_resource_size_used + - sizeof(m_rsc_end_node) + resource->header.length, + &m_rsc_end_node, sizeof(m_rsc_end_node)); + m_stm_resource_size_used += resource->header.length; + m_stm_resource_size_available = + m_stm_resource_total_size - m_stm_resource_size_used; +} + +/* + * Add resource list. + * + * @param resource_list A pointer to resource list to be added + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + */ +static void add_resource(STM_RSC *resource_list, uint32_t num_entries) +{ + uint32_t count; + uint32_t index; + STM_RSC *resource; + + if (num_entries == 0) + count = 0xFFFFFFFF; + else + count = num_entries; + + resource = resource_list; + + for (index = 0; index < count; index++) { + if (resource->header.rsc_type == END_OF_RESOURCES) + return; + add_single_resource(resource); + resource = + (STM_RSC *)((void *)resource + resource->header.length); + } +} + +/* + * Validate resource list. + * + * @param resource_list A pointer to resource list to be added + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + * + * @retval true resource valid + * @retval false resource invalid + */ +static bool validate_resource(STM_RSC *resource_list, uint32_t num_entries) +{ + uint32_t count; + uint32_t index; + STM_RSC *resource; + uint32_t sub_index; + + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + if (num_entries == 0) + count = 0xFFFFFFFF; + else + count = num_entries; + + // Start from beginning of resource list. + resource = resource_list; + + for (index = 0; index < count; index++) { + printk(BIOS_DEBUG, "STM: %s (%u) - RscType(%x) length(0x%x)\n", + __func__, + index, + resource->header.rsc_type, + resource->header.length); + // Validate resource. + switch (resource->header.rsc_type) { + case END_OF_RESOURCES: + if (resource->header.length != sizeof(STM_RSC_END)) + return false; + + // If we are passed actual number of resources to add, + // END_OF_RESOURCES structure between them is considered + // an error. If NumEntries == 0 END_OF_RESOURCES is a + // termination. + if (num_entries != 0) + return false; + + // If NumEntries == 0 and list reached end - return + // success. + return true; + + case MEM_RANGE: + case MMIO_RANGE: + printk(BIOS_DEBUG, + "STM: %s - MEM (0x%0llx, 0x%0llx)\n", + __func__, + resource->mem.base, + resource->mem.length); + + if (resource->header.length != sizeof(STM_RSC_MEM_DESC)) + return false; + + if (resource->mem.rwx_attributes > FULL_ACCS) + return false; + break; + + case IO_RANGE: + case TRAPPED_IO_RANGE: + if (resource->header.length != sizeof(STM_RSC_IO_DESC)) + return false; + + if ((resource->io.base + resource->io.length) > 0xFFFF) + return false; + break; + + case PCI_CFG_RANGE: + printk(BIOS_DEBUG, + "STM: %s - PCI (0x%02x, 0x%08x, 0x%02x, 0x%02x)\n", + __func__, + resource->pci_cfg.originating_bus_number, + resource->pci_cfg.last_node_index, + resource->pci_cfg.pci_device_path[0].pci_device, + resource->pci_cfg.pci_device_path[0] + .pci_function); + if (resource->header.length + != sizeof(STM_RSC_PCI_CFG_DESC) + + (sizeof(STM_PCI_DEVICE_PATH_NODE) + * resource->pci_cfg.last_node_index)) + return false; + for (sub_index = 0; + sub_index <= resource->pci_cfg.last_node_index; + sub_index++) { + if ((resource->pci_cfg + .pci_device_path[sub_index] + .pci_device + > 0x1F) + || (resource->pci_cfg + .pci_device_path[sub_index] + .pci_function + > 7)) + return false; + } + if ((resource->pci_cfg.base + resource->pci_cfg.length) + > 0x1000) + return false; + break; + + case MACHINE_SPECIFIC_REG: + if (resource->header.length != sizeof(STM_RSC_MSR_DESC)) + return false; + break; + + default: + printk(BIOS_DEBUG, "STM: %s - Unknown RscType(%x)\n", + __func__, resource->header.rsc_type); + return false; + } + resource = + (STM_RSC *)((void *)resource + resource->header.length); + } + return true; +} + +/* + * Get resource list. + * EndResource is excluded. + * + * @param resou rce_list A pointer to resource list to be added + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + * + * @retval true resource valid + * @retval false resource invalid + */ +static uint32_t get_resource_size(STM_RSC *resource_list, uint32_t num_entries) +{ + uint32_t count; + uint32_t index; + STM_RSC *resource; + + resource = resource_list; + + // If NumEntries == 0 make it very big. Scan will be terminated by + // END_OF_RESOURCES. + if (num_entries == 0) + count = 0xFFFFFFFF; + else + count = num_entries; + + // Start from beginning of resource list. + resource = resource_list; + + for (index = 0; index < count; index++) { + if (resource->header.rsc_type == END_OF_RESOURCES) + break; + resource = + (STM_RSC *)((void *)resource + resource->header.length); + } + return (uint32_t)((uint32_t)resource - (uint32_t)resource_list); +} + +/* + * Add resources in list to database. Allocate new memory areas as needed. + * + * @param resource_list A pointer to resource list to be added + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + * + * @retval SUCCESS If resources are added + * @retval INVALID_PARAMETER If nested procedure detected resource failure + * @retval OUT_OF_RESOURCES If nested procedure returned it and we cannot + * allocate more areas. + */ +int add_pi_resource(STM_RSC *resource_list, uint32_t num_entries) +{ + size_t resource_size; + + printk(BIOS_DEBUG, "STM: %s - Enter\n", __func__); + + if (!validate_resource(resource_list, num_entries)) + return -1; // INVALID_PARAMETER; + + resource_size = get_resource_size(resource_list, num_entries); + printk(BIOS_DEBUG, "STM: ResourceSize - 0x%08lx\n", resource_size); + if (resource_size == 0) + return -1; // INVALID_PARAMETER; + + if (m_stm_resources_ptr == NULL) { + + // Copy EndResource for initialization + m_stm_resources_ptr = stm_resource_heap; + m_stm_resource_total_size = CONFIG_BIOS_RESOURCE_LIST_SIZE; + memset(m_stm_resources_ptr, 0, CONFIG_BIOS_RESOURCE_LIST_SIZE); + + memcpy(m_stm_resources_ptr, &m_rsc_end_node, + sizeof(m_rsc_end_node)); + m_stm_resource_size_used = sizeof(m_rsc_end_node); + m_stm_resource_size_available = + m_stm_resource_total_size - sizeof(m_rsc_end_node); + wbinvd(); // force to memory + + } else { + if (m_stm_resource_size_available < resource_size) { + printk(BIOS_DEBUG, + "STM: ERROR - not enough space for SMM resource list\n"); + return -1; // OUT_OF_RESOURCES + } + } + + // Check duplication + add_resource(resource_list, num_entries); + + return 0; // SUCCESS; +} + +/* + * Delete resources in list to database. + * + * @param resource_list A pointer to resource list to be deleted + * NULL means delete all resources. + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + * + * @retval SUCCESS If resources are deleted + * @retval INVALID_PARAMETER If nested procedure detected resource failure + */ +int32_t delete_pi_resource(STM_RSC *resource_list, uint32_t num_entries) +{ + if (resource_list != NULL) { + // ASSERT (false); + return -1; // UNSUPPORTED; + } + + // Delete all + memcpy(m_stm_resources_ptr, &m_rsc_end_node, sizeof(m_rsc_end_node)); + m_stm_resource_size_used = sizeof(m_rsc_end_node); + m_stm_resource_size_available = + m_stm_resource_total_size - sizeof(m_rsc_end_node); + return 0; // SUCCESS; +} + +/* + * Get BIOS resources. + * + * @param resource_list A pointer to resource list to be filled + * @param resource_size On input it means size of resource list input. + * On output it means size of resource list filled, + * or the size of resource list to be filled if size is + * too small. + * + * @retval SUCCESS If resources are returned. + * @retval BUFFER_TOO_SMALL If resource list buffer is too small to hold + * the whole resource list. + */ +int32_t get_pi_resource(STM_RSC *resource_list, uint32_t *resource_size) +{ + if (*resource_size < m_stm_resource_size_used) { + *resource_size = (uint32_t)m_stm_resource_size_used; + return -1; // BUFFER_TOO_SMALL; + } + + memcpy(resource_list, m_stm_resources_ptr, m_stm_resource_size_used); + *resource_size = (uint32_t)m_stm_resource_size_used; + return 0; // SUCCESS; +} + +/* + * Get 4K page aligned VMCS size. + * @return 4K page aligned VMCS size + */ +static uint32_t get_vmcs_size(void) +{ + uint32_t this_vmcs_size; + VMX_BASIC_MSR msr_data64; + int stm_support; + + msr_data64.msr = rdmsr(IA32_VMX_BASIC_MSR); + + this_vmcs_size = msr_data64.bits.vmcs_size; + stm_support = msr_data64.bits.stm_supported; + printk(BIOS_DEBUG, "STM: %s: Size %d StmSupport %d\n", __func__, + this_vmcs_size, stm_support); + + // VMCS require 0x1000 alignment + this_vmcs_size = STM_PAGES_TO_SIZE(STM_SIZE_TO_PAGES(this_vmcs_size)); + + return this_vmcs_size; +} + +/* + * Create 4G page table for STM. + * 2M PTEs for x86_64 or 2M PTEs for x86_32. + * + * @param pageable_base The page table base in MSEG + */ +void stm_gen_4g_pagetable_x64(uint32_t pagetable_base) +{ + uint32_t index; + uint32_t sub_index; + uint64_t *pde; + uint64_t *pte; + uint64_t *pml4; + + pml4 = (uint64_t *)(uint32_t)pagetable_base; + pagetable_base += PTP_SIZE; + *pml4 = pagetable_base | IA32_PG_RW | IA32_PG_P; + + pde = (uint64_t *)(uint32_t)pagetable_base; + pagetable_base += PTP_SIZE; + pte = (uint64_t *)(uint32_t)pagetable_base; + + for (index = 0; index < 4; index++) { + *pde = pagetable_base | IA32_PG_RW | IA32_PG_P; + pde++; + pagetable_base += PTP_SIZE; + + for (sub_index = 0; sub_index < SIZE_4KB / sizeof(*pte); + sub_index++) { + *pte = (((index << 9) + sub_index) << 21) | IA32_PG_PS + | IA32_PG_RW | IA32_PG_P; + pte++; + } + } +} + +/* + * Check STM image size. + * + * @param stm_image STM image + * @param stm_imageSize STM image size + * + * @retval true check pass + * @retval false check fail + */ + +bool stm_check_stm_image(void *stm_image, uint32_t stm_imagesize) +{ + uint32_t min_mseg_size; + STM_HEADER *stm_header; + + stm_header = (STM_HEADER *)stm_image; + + // Get Minimal required Mseg size + min_mseg_size = (STM_PAGES_TO_SIZE(STM_SIZE_TO_PAGES( + stm_header->sw_stm_hdr.static_image_size)) + + stm_header->sw_stm_hdr.additional_dynamic_memory_size + + (stm_header->sw_stm_hdr.per_proc_dynamic_memory_size + + get_vmcs_size() * 2) + * mp_state.cpu_count); + if (min_mseg_size < stm_imagesize) + min_mseg_size = stm_imagesize; + + if (stm_header->hw_stm_hdr.cr3_offset + >= stm_header->sw_stm_hdr.static_image_size) { + + // We will create page table, just in case that SINIT does not + // create it. + if (min_mseg_size < stm_header->hw_stm_hdr.cr3_offset + + STM_PAGES_TO_SIZE(6)) { + min_mseg_size = stm_header->hw_stm_hdr.cr3_offset + + STM_PAGES_TO_SIZE(6); + } + } + + // Check if it exceeds MSEG size + if (min_mseg_size > CONFIG_MSEG_SIZE) + return false; + + return true; +} + +/* + * This function return BIOS STM resource. + * Produced by SmmStm. + * Comsumed by SmmMpService when Init. + * + * @return BIOS STM resource + */ +void *get_stm_resource(void) +{ + return m_stm_resources_ptr; +} diff --git a/src/security/intel/stm/SmmStm.h b/src/security/intel/stm/SmmStm.h new file mode 100644 index 0000000000..4f72816cae --- /dev/null +++ b/src/security/intel/stm/SmmStm.h @@ -0,0 +1,120 @@ +/* @file + * SMM STM support + * + * Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved. + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may + * be found at http://opensource.org/licenses/bsd-license.php. + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED + * + */ + +#ifndef _SMM_STM_H_ +#define _SMM_STM_H_ + +#include +#include "StmApi.h" + +/* + * Load STM image. + * + * @retval SUCCESS STM is loaded to MSEG + * @retval BUFFER_TOO_SMALL MSEG is too small + * @retval UNSUPPORTED MSEG is not enabled + */ +int load_stm_image(uintptr_t mseg); + +void stm_setup( + uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, + uintptr_t smbase_base, uint32_t offset32); + +/* + * Add resources in list to database. Allocate new memory areas as needed. + * + * @param resource_list A pointer to resource list to be added + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + * + * @retval SUCCESS If resources are added + * @retval INVALID_PARAMETER If nested procedure detected resource failure + * @retval OUT_OF_RESOURCES If nested procedure returned it and we cannot + * allocate more areas. + */ +int add_pi_resource(STM_RSC *resource_list, uint32_t num_entries); + +/* + * Delete resources in list to database. + * + * @param resource_list A pointer to resource list to be deleted + * NULL means delete all resources. + * @param num_entries Optional number of entries. + * If 0, list must be terminated by END_OF_RESOURCES. + * + * @retval SUCCESS If resources are deleted + * @retval NVALID_PARAMETER If nested procedure detected resource fail + */ +int delete_pi_resource(STM_RSC *resource_list, uint32_t num_entries); + +/* + * Get BIOS resources. + * + * @param resource_list A pointer to resource list to be filled + * @param resource_size On input it means size of resource list input. + * On output it means size of resource list filled, + * or the size of resource list to be filled if + * size is too small. + * + * @retval SUCCESS If resources are returned. + * @retval BUFFER_TOO_SMALL If resource list buffer is too small to + * hold the whole resources. + */ +int get_pi_resource(STM_RSC *resource_list, uint32_t *resource_size); + +/* + * This function notifies the STM of a resource change. + * + * @param stm_resource BIOS STM resource + */ +void notify_stm_resource_change(void *stm_resource); + +/* + * This function returns the pointer to the STM BIOS resource list. + * + * @return BIOS STM resource + */ +void *get_stm_resource(void); + +void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, + int32_t entry32_off); + +/* + * Check STM image size. + * + * @param stm_image STM image + * @param stm_image_size STM image size + * + * @retval true check pass + * @retval false check fail + */ +bool stm_check_stm_image(void *stm_image, uint32_t stm_image_size); + +/* + * Create 4G page table for STM. + * 4M Non-PAE page table in IA32 version. + * + * @param page_table_base The page table base in MSEG + */ +void stm_gen_4g_pagetable_ia32(uint32_t pagetable_base); + +/* + * Create 4G page table for STM. + * 2M PAE page table in X64 version. + * + * @param pagetable_base The page table base in MSEG + */ +void stm_gen_4g_pagetable_x64(uint32_t pagetable_base); + +#endif diff --git a/src/security/intel/stm/StmApi.h b/src/security/intel/stm/StmApi.h new file mode 100644 index 0000000000..342ceeacf6 --- /dev/null +++ b/src/security/intel/stm/StmApi.h @@ -0,0 +1,726 @@ +/* @file + * STM API definition + * + * Copyright (c) 2015, Intel Corporation. All rights reserved. + * This program and the accompanying materials are licensed and made available + * under the terms and conditions of the BSD License which accompanies this + * distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php. + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, + * EITHER EXPRESS OR IMPLIED. + * + */ + +#ifndef _STM_API_H_ +#define _STM_API_H_ + +#include + +// definition in STM spec + +#define STM_SPEC_VERSION_MAJOR 1 +#define STM_SPEC_VERSION_MINOR 0 + +#pragma pack(push, 1) + +#define STM_HARDWARE_FIELD_FILL_TO_2K (2048 - sizeof(uint32_t) * 8) +typedef struct { + uint32_t stm_header_revision; + uint32_t monitor_features; + uint32_t gdtr_limit; + uint32_t gdtr_base_offset; + uint32_t cs_selector; + uint32_t eip_offset; + uint32_t esp_offset; + uint32_t cr3_offset; + uint8_t reserved[STM_HARDWARE_FIELD_FILL_TO_2K]; +} HARDWARE_STM_HEADER; + +#define STM_FEATURES_IA32E 0x1 + +typedef struct { + uint32_t intel_64mode_supported : 1; + uint32_t ept_supported : 1; + uint32_t mbz : 30; +} STM_FEAT; + +typedef struct { + uint8_t stm_spec_ver_major; + uint8_t stm_pec_ver_minor; + uint16_t mbz; + uint32_t static_image_size; + uint32_t per_proc_dynamic_memory_size; + uint32_t additional_dynamic_memory_size; + STM_FEAT stm_features; + uint32_t number_of_rev_ids; + uint32_t stm_smm_rev_id[1]; + + // The total STM_HEADER should be 4K. +} SOFTWARE_STM_HEADER; + +typedef struct { + HARDWARE_STM_HEADER hw_stm_hdr; + SOFTWARE_STM_HEADER sw_stm_hdr; +} STM_HEADER; + +#define SHA1 1 +#define SHA256 2 +typedef struct { + uint64_t bios_component_base; + uint32_t image_size; + uint32_t hash_algorithm; // SHA1 or SHA256 + uint8_t hash[32]; +} TXT_BIOS_COMPONENT_STATUS; + +#define PAGE_SIZE 4096 +typedef struct { + uint32_t image_size; + uint32_t reserved; + uint64_t image_page_base[1]; //[NumberOfPages]; +} TXT_BIOS_COMPONENT_UPDATE; + +typedef struct { + uint64_t spe_rip; + uint64_t spe_rsp; + uint16_t spe_ss; + uint16_t page_violation_exception : 1; + uint16_t msr_violation_exception : 1; + uint16_t register_violation_exception : 1; + uint16_t io_violation_exception : 1; + uint16_t pci_violation_exception : 1; + uint16_t reserved1 : 11; + uint32_t reserved2; +} STM_PROTECTION_EXCEPTION_HANDLER; + +typedef struct { + uint8_t execution_disable_outside_smrr : 1; + uint8_t intel_64mode : 1; + uint8_t cr4_pae : 1; + uint8_t cr4_pse : 1; + uint8_t reserved1 : 4; +} STM_SMM_ENTRY_STATE; + +typedef struct { + uint8_t smram_to_vmcs_restore_required : 1; // BIOS restore hint + uint8_t reinitialize_vmcs_required : 1; // BIOS request + uint8_t reserved2 : 6; +} STM_SMM_RESUME_STATE; + +typedef struct { + uint8_t domain_type : 4; // STM input to BIOS on each SM + uint8_t x_state_policy : 2; // STM input to BIOS on each SMI + uint8_t ept_enabled : 1; + uint8_t reserved3 : 1; +} STM_SMM_STATE; + +typedef struct { + uint64_t signature; + uint16_t size; + uint8_t smm_descriptor_ver_major; + uint8_t smm_descriptor_ver_minor; + uint32_t local_apic_id; + STM_SMM_ENTRY_STATE smm_entry_state; + STM_SMM_RESUME_STATE smm_resume_state; + STM_SMM_STATE stm_smm_state; + uint8_t reserved4; + uint16_t smm_cs; + uint16_t smm_ds; + uint16_t smm_ss; + uint16_t smm_other_segment; + uint16_t smm_tr; + uint16_t reserved5; + uint64_t smm_cr3; + uint64_t smm_stm_setup_rip; + uint64_t smm_stm_teardown_rip; + uint64_t smm_smi_handler_rip; + uint64_t smm_smi_handler_rsp; + uint64_t smm_gdt_ptr; + uint32_t smm_gdt_size; + uint32_t required_stm_smm_rev_id; + STM_PROTECTION_EXCEPTION_HANDLER stm_protection_exception_handler; + uint64_t reserved6; + uint64_t bios_hw_resource_requirements_ptr; + // extend area + uint64_t acpi_rsdp; + uint8_t physical_address_bits; +} TXT_PROCESSOR_SMM_DESCRIPTOR; + +#define TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE "TXTPSSIG" +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR 1 +#define TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR 0 + +#define SMM_PSD_OFFSET 0xfb00 + +typedef enum { + TxtSmmPageViolation = 1, + TxtSmmMsrViolation, + TxtSmmRegisterViolation, + TxtSmmIoViolation, + TxtSmmPciViolation +} TXT_SMM_PROTECTION_EXCEPTION_TYPE; + +typedef struct { + uint32_t rdi; + uint32_t rsi; + uint32_t rbp; + uint32_t rdx; + uint32_t rcx; + uint32_t rbx; + uint32_t rax; + uint32_t cr3; + uint32_t cr2; + uint32_t cr0; + uint32_t vmcs_exit_instruction_info; + uint32_t vmcs_exit_instruction_length; + uint64_t vmcs_exit_qualification; + uint32_t error_code; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint32_t rip; + uint32_t cs; + uint32_t rflags; + uint32_t rsp; + uint32_t ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32; + +typedef struct { + uint64_t r15; + uint64_t r14; + uint64_t r13; + uint64_t r12; + uint64_t r11; + uint64_t r10; + uint64_t r9; + uint64_t r8; + uint64_t rdi; + uint64_t rsi; + uint64_t rbp; + uint64_t rdx; + uint64_t rcx; + uint64_t rbx; + uint64_t rax; + uint64_t cr8; + uint64_t cr3; + uint64_t cr2; + uint64_t cr0; + uint64_t vmcs_exit_instruction_info; + uint64_t vmcs_exit_instruction_length; + uint64_t vmcs_exit_qualification; + uint64_t error_code; // TXT_SMM_PROTECTION_EXCEPTION_TYPE + uint64_t rip; + uint64_t cs; + uint64_t rflags; + uint64_t rsp; + uint64_t ss; +} STM_PROTECTION_EXCEPTION_STACK_FRAME_X64; + +typedef union { + STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 *ia32_stack_frame; + STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 *x64_stack_frame; +} STM_PROTECTION_EXCEPTION_STACK_FRAME; + +#define STM_SMM_REV_ID 0x80010100 + +typedef struct _STM_SMM_CPU_STATE { // Writable? + uint8_t reserved1[0x1d0]; // fc00h + uint32_t gdt_base_hi_dword; // fdd0h : NO + uint32_t ldt_base_hi_dword; // fdd4h : NO + uint32_t idt_base_hi_dword; // fdd8h : NO + uint8_t reserved2[0x4]; // fddch + uint64_t io_rdi; // fde0h : NO + // - restricted + uint64_t io_eip; // fde8h : YES + uint64_t io_rcx; // fdf0h : NO + // - restricted + uint64_t io_rsi; // fdf8h : NO + // - restricted + uint8_t reserved3[0x40]; // fe00h + uint32_t cr4; // fe40h : NO + uint8_t reserved4[0x48]; // fe44h + uint32_t gdt_base_lo_dword; // fe8ch : NO + uint32_t gdt_limit; // fe90h : NO + // - RESTRICTED + uint32_t idt_base_lo_dword; // fe94h : NO + uint32_t idt_limit; // fe98h : NO + // - RESTRICTED + uint32_t ldt_base_lo_dword; // fe9ch : NO + uint32_t ldt_limit; // fea0h : NO + // - RESTRICTED + uint32_t ldt_info; // fea4h : NO + // - RESTRICTED + uint8_t reserved5[0x30]; // fea8h + uint64_t eptp; // fed8h : NO + uint32_t enabled_ept; // fee0h : NO + uint8_t reserved6[0x14]; // fee4h + uint32_t smbase; // fef8h : YES + // - NO for STM + uint32_t smm_rev_id; // fefch : NO + uint16_t io_restart; // ff00h : YES + uint16_t auto_halt_restart; // ff02h : YES + uint8_t reserved7[0x18]; // ff04h + uint64_t r15; // ff1ch : YES + uint64_t r14; // ff24h : YES + uint64_t r13; // ff2ch : YES + uint64_t r12; // ff34h : YES + uint64_t r11; // ff3ch : YES + uint64_t r10; // ff44h : YES + uint64_t r9; // ff4ch : YES + uint64_t r8; // ff54h : YES + uint64_t rax; // ff5ch : YES + uint64_t rcx; // ff64h : YES + uint64_t rdx; // ff6ch : YES + uint64_t rbx; // ff74h : YES + uint64_t rsp; // ff7ch : YES + uint64_t rbp; // ff84h : YES + uint64_t rsi; // ff8ch : YES + uint64_t rdi; // ff94h : YES + uint64_t io_mem_addr; // ff9ch : NO + uint32_t io_misc; // ffa4h : NO + uint32_t es; // ffa8h : NO + uint32_t cs; // ffach : NO + uint32_t ss; // ffb0h : NO + uint32_t ds; // ffb4h : NO + uint32_t fs; // ffb8h : NO + uint32_t gs; // ffbch : NO + uint32_t ldtr; // ffc0h : NO + uint32_t tr; // ffc4h : NO + uint64_t dr7; // ffc8h : NO + uint64_t dr6; // ffd0h : NO + uint64_t rip; // ffd8h : YES + uint64_t ia32_efer; // ffe0h : YES + // - NO for STM + uint64_t rflags; // ffe8h : YES + uint64_t cr3; // fff0h : NO + uint64_t cr0; // fff8h : NO +} STM_SMM_CPU_STATE; + +// STM Mapping +typedef struct { + uint64_t physical_address; + uint64_t virtual_ddress; + uint32_t Page_count; + uint32_t Pat_cache_type; +} STM_MAP_ADDRESS_RANGE_DESCRIPTOR; + +#define ST_UC 0x00 +#define WC 0x01 +#define WT 0x04 +#define WP 0x05 +#define WB 0x06 +#define UC 0x07 +#define FOLLOW_MTRR 0xFFFFFFFF + +typedef struct { + uint64_t virtual_address; + uint32_t length; +} STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR; + +typedef struct { + uint64_t interrupted_guest_virtual_address; + uint32_t length; + uint64_t interrupted_cr3; + uint64_t interrupted_eptp; + uint32_t map_to_smm_guest : 2; + uint32_t interrupted_cr4_pae : 1; + uint32_t interrupted_cr4_pse : 1; + uint32_t interrupted_ia32e_mode : 1; + uint32_t reserved1 : 27; + uint32_t reserved2; + uint64_t physical_address; + uint64_t smm_guest_virtual_address; +} STM_ADDRESS_LOOKUP_DESCRIPTOR; + +#define DO_NOT_MAP 0 +#define ONE_TO_ONE 1 +#define VIRTUAL_ADDRESS_SPECIFIED 3 + +// STM_RESOURCE_LIST +#define END_OF_RESOURCES 0 +#define MEM_RANGE 1 +#define IO_RANGE 2 +#define MMIO_RANGE 3 +#define MACHINE_SPECIFIC_REG 4 +#define PCI_CFG_RANGE 5 +#define TRAPPED_IO_RANGE 6 +#define ALL_RESOURCES 7 +#define REGISTER_VIOLATION 8 +#define MAX_DESC_TYPE 8 + +typedef struct { + uint32_t rsc_type; + uint16_t length; + uint16_t return_status : 1; + uint16_t reserved : 14; + uint16_t ignore_resource : 1; +} STM_RSC_DESC_HEADER; + +typedef struct { + STM_RSC_DESC_HEADER Hdr; + uint64_t resource_list_continuation; +} STM_RSC_END; + +// byte granular Memory range support +#define STM_RSC_BGM 0x4 + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint64_t base; + uint64_t length; + uint32_t rwx_attributes : 3; + uint32_t reserved : 29; + uint32_t reserved_2; +} STM_RSC_MEM_DESC; + +#define STM_RSC_MEM_R 0x1 +#define STM_RSC_MEM_W 0x2 +#define STM_RSC_MEM_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint16_t base; + uint16_t length; + uint32_t reserved; +} STM_RSC_IO_DESC; + +// byte granular MMIO range support +#define STM_RSC_BGI 0x2 + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint64_t base; + uint64_t length; + uint32_t rwx_attributes : 3; + uint32_t reserved : 29; + uint32_t reserved_2; +} STM_RSC_MMIO_DESC; + +#define STM_RSC_MMIO_R 0x1 +#define STM_RSC_MMIO_W 0x2 +#define STM_RSC_MMIO_X 0x4 + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint32_t msr_index; + uint32_t kernel_mode_processing : 1; + uint32_t reserved : 31; + uint64_t read_mask; + uint64_t write_mask; +} STM_RSC_MSR_DESC; + +// bit granular MSR resource support +#define STM_RSC_MSR 0x8 + +typedef struct { + uint8_t type; // must be 1, indicating Hardware Device Path + uint8_t subtype; // must be 1, indicating PCI + uint16_t length; // sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6 + uint8_t pci_function; + uint8_t pci_device; +} STM_PCI_DEVICE_PATH_NODE; + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint16_t rw_attributes : 2; + uint16_t reserved : 14; + uint16_t base; + uint16_t length; + uint8_t originating_bus_number; + uint8_t last_node_index; + STM_PCI_DEVICE_PATH_NODE pci_device_path[1]; + // STM_PCI_DEVICE_PATH_NODE PciDevicePath[LastNodeIndex + 1]; +} STM_RSC_PCI_CFG_DESC; + +#define STM_RSC_PCI_CFG_R 0x1 +#define STM_RSC_PCI_CFG_W 0x2 + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint16_t base; + uint16_t length; + uint16_t in : 1; + uint16_t out : 1; + uint16_t api : 1; + uint16_t reserved1 : 13; + uint16_t reserved2; +} STM_RSC_TRAPPED_IO_DESC; + +typedef struct { + STM_RSC_DESC_HEADER hdr; +} STM_RSC_ALL_RESOURCES_DESC; + +typedef struct { + STM_RSC_DESC_HEADER hdr; + uint32_t register_type; + uint32_t reserved; + uint64_t readMask; + uint64_t write_mask; +} STM_REGISTER_VIOLATION_DESC; + +typedef enum { + stm_register_cr0, + stm_register_cr2, + stm_register_cr3, + stm_register_cr4, + stm_register_cr8, + stm_register_max, +} STM_REGISTER_VIOLATION_TYPE; + +typedef union { + STM_RSC_DESC_HEADER header; + STM_RSC_END end; + STM_RSC_MEM_DESC mem; + STM_RSC_IO_DESC io; + STM_RSC_MMIO_DESC mmio; + STM_RSC_MSR_DESC msr; + STM_RSC_PCI_CFG_DESC pci_cfg; + STM_RSC_TRAPPED_IO_DESC trapped_io; + STM_RSC_ALL_RESOURCES_DESC all; + STM_REGISTER_VIOLATION_DESC register_violation; +} STM_RSC; + +// VMCS database +#define STM_VMCS_DATABASE_REQUEST_ADD 1 +#define STM_VMCS_DATABASE_REQUEST_REMOVE 0 + +// Values for DomainType +// Interpreter of DomainType +#define DOMAIN_DISALLOWED_IO_OUT (1u << 0) +#define DOMAIN_DISALLOWED_IO_IN (1u << 1) +#define DOMAIN_INTEGRITY (1u << 2) +#define DOMAIN_CONFIDENTIALITY (1u << 3) + +#define DOMAIN_UNPROTECTED 0x00 +#define DOMAIN_INTEGRITY_PROT_OUT_IN (DOMAIN_INTEGRITY) +#define DOMAIN_FULLY_PROT_OUT_IN (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY) +#define DOMAIN_FULLY_PROT \ + (DOMAIN_CONFIDENTIALITY | DOMAIN_INTEGRITY | DOMAIN_DISALLOWED_IO_IN \ + | DOMAIN_DISALLOWED_IO_OUT) + +// Values for XStatePolicy +#define XSTATE_READWRITE 0x00 +#define XSTATE_READONLY 0x01 +#define XSTATE_SCRUB 0x03 + +typedef struct { + uint64_t vmcs_phys_pointer; // bits 11:0 are reserved and must be 0 + uint32_t domain_type : 4; + uint32_t x_state_policy : 2; + uint32_t degradation_policy : 4; + uint32_t reserved1 : 22; // Must be 0 + uint32_t add_or_remove; +} STM_VMCS_DATABASE_REQUEST; + +// Event log +#define NEW_LOG 1 +#define CONFIGURE_LOG 2 +#define START_LOG 3 +#define STOP_LOG 4 +#define CLEAR_LOG 5 +#define DELETE_LOG 6 +typedef enum { + evt_log_started, + evt_log_stopped, + evt_log_invalid_parameter_detected, + evt_handled_protection_exception, + // unhandled protection exceptions result in reset & cannot be logged + evt_bios_access_to_unclaimed_resource, + evt_mle_resource_protection_granted, + evt_mle_resource_protection_denied, + evt_mle_resource_unprotect, + evt_mle_resource_unprotect_error, + evt_mle_domain_type_degraded, + // add more here + evt_mle_max, + // Not used + evt_invalid = 0xFFFFFFFF, +} EVENT_TYPE; + +typedef struct { + uint32_t page_count; + uint64_t pages[1]; // number of elements is PageCount +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER; + +typedef union { + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA_LOG_BUFFER log_buffer; + uint32_t event_enable_bitmap; // bitmap of EVENT_TYPE +} STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA; + +typedef struct { + uint32_t sub_functionindex; + STM_EVENT_LOG_MANAGEMENT_REQUEST_DATA data; +} STM_EVENT_LOG_MANAGEMENT_REQUEST; + +// VMCALL API Numbers +// +// API number convention: BIOS facing VMCALL interfaces have bit 16 clear +#define STM_API_MAP_ADDRESS_RANGE 0x00000001 +#define STM_API_UNMAP_ADDRESS_RANGE 0x00000002 +#define STM_API_ADDRESS_LOOKUP 0x00000003 +#define STM_API_RETURN_FROM_PROTECTION_EXCEPTION 0x00000004 + +// API number convention: MLE facing VMCALL interfaces have bit 16 set +// +// The STM configuration lifecycle is as follows: +// 1. SENTER->SINIT->MLE: MLE begins execution with SMI disabled (masked). +// 2. MLE invokes InitializeProtectionVMCALL() to prepare STM for setup of +// initial protection profile. This is done on a single CPU and has global +// effect. +// 3. MLE invokes ProtectResourceVMCALL() to define the initial protection +// profile. The protection profile is global across all CPUs. +// 4. MLE invokes StartStmVMCALL() to enable the STM to begin receiving SMI +// events. This must be done on every logical CPU. +// 5. MLE may invoke ProtectResourceVMCALL() or UnProtectResourceVMCALL() +// during runtime as many times as necessary. +// 6. MLE invokes StopStmVMCALL() to disable the STM. SMI is again masked +// following StopStmVMCALL(). +// +#define STM_API_START 0x00010001 +#define STM_API_STOP 0x00010002 +#define STM_API_PROTECT_RESOURCE 0x00010003 +#define STM_API_UNPROTECT_RESOURCE 0x00010004 +#define STM_API_GET_BIOS_RESOURCES 0x00010005 +#define STM_API_MANAGE_VMCS_DATABASE 0x00010006 +#define STM_API_INITIALIZE_PROTECTION 0x00010007 +#define STM_API_MANAGE_EVENT_LOG 0x00010008 + +// Return codes +typedef uint32_t STM_STATUS; + +#define STM_SUCCESS 0x00000000 +#define SMM_SUCCESS 0x00000000 +// all error codes have bit 31 set +// STM errors have bit 16 set +#define ERROR_STM_SECURITY_VIOLATION 0x80010001 +#define ERROR_STM_CACHE_TYPE_NOT_SUPPORTED 0x80010002 +#define ERROR_STM_PAGE_NOT_FOUND 0x80010003 +#define ERROR_STM_BAD_CR3 0x80010004 +#define ERROR_STM_PHYSICAL_OVER_4G 0x80010005 +#define ERROR_STM_VIRTUAL_SPACE_TOO_SMALL 0x80010006 +#define ERROR_STM_UNPROTECTABLE_RESOURCE 0x80010007 +#define ERROR_STM_ALREADY_STARTED 0x80010008 +#define ERROR_STM_WITHOUT_SMX_UNSUPPORTED 0x80010009 +#define ERROR_STM_STOPPED 0x8001000A +#define ERROR_STM_BUFFER_TOO_SMALL 0x8001000B +#define ERROR_STM_INVALID_VMCS_DATABASE 0x8001000C +#define ERROR_STM_MALFORMED_RESOURCE_LIST 0x8001000D +#define ERROR_STM_INVALID_PAGECOUNT 0x8001000E +#define ERROR_STM_LOG_ALLOCATED 0x8001000F +#define ERROR_STM_LOG_NOT_ALLOCATED 0x80010010 +#define ERROR_STM_LOG_NOT_STOPPED 0x80010011 +#define ERROR_STM_LOG_NOT_STARTED 0x80010012 +#define ERROR_STM_RESERVED_BIT_SET 0x80010013 +#define ERROR_STM_NO_EVENTS_ENABLED 0x80010014 +#define ERROR_STM_OUT_OF_RESOURCES 0x80010015 +#define ERROR_STM_FUNCTION_NOT_SUPPORTED 0x80010016 +#define ERROR_STM_UNPROTECTABLE 0x80010017 +#define ERROR_STM_UNSUPPORTED_MSR_BIT 0x80010018 +#define ERROR_STM_UNSPECIFIED 0x8001FFFF + +// SMM errors have bit 17 set +#define ERROR_SMM_BAD_BUFFER 0x80020001 +#define ERROR_SMM_INVALID_RSC 0x80020004 +#define ERROR_SMM_INVALID_BUFFER_SIZE 0x80020005 +#define ERROR_SMM_BUFFER_TOO_SHORT 0x80020006 +#define ERROR_SMM_INVALID_LIST 0x80020007 +#define ERROR_SMM_OUT_OF_MEMORY 0x80020008 +#define ERROR_SMM_AFTER_INIT 0x80020009 +#define ERROR_SMM_UNSPECIFIED 0x8002FFFF + +// Errors that apply to both have bits 15, 16, and 17 set +#define ERROR_INVALID_API 0x80038001 +#define ERROR_INVALID_PARAMETER 0x80038002 + +// STM TXT.ERRORCODE codes +#define STM_CRASH_PROTECTION_EXCEPTION 0xC000F001 +#define STM_CRASH_PROTECTION_EXCEPTION_FAILURE 0xC000F002 +#define STM_CRASH_DOMAIN_DEGRADATION_FAILURE 0xC000F003 +#define STM_CRASH_BIOS_PANIC 0xC000E000 + +typedef struct { + uint32_t event_serial_number; + uint16_t type; + uint16_t lock : 1; + uint16_t valid : 1; + uint16_t read_by_mle : 1; + uint16_t wrapped : 1; + uint16_t reserved : 12; +} LOG_ENTRY_HEADER; + +typedef struct { + uint32_t reserved; +} ENTRY_EVT_LOG_STARTED; + +typedef struct { + uint32_t reserved; +} ENTRY_EVT_LOG_STOPPED; + +typedef struct { + uint32_t vmcall_api_number; +} ENTRY_EVT_LOG_INVALID_PARAM; + +typedef struct { + STM_RSC resource; +} ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION; + +typedef struct { + STM_RSC resource; +} ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC; + +typedef struct { + STM_RSC resource; +} ENTRY_EVT_MLE_RSC_PROT_GRANTED; + +typedef struct { + STM_RSC resource; +} ENTRY_EVT_MLE_RSC_PROT_DENIED; + +typedef struct { + STM_RSC resource; +} ENTRY_EVT_MLE_RSC_UNPROT; + +typedef struct { + STM_RSC resource; +} ENTRY_EVT_MLE_RSC_UNPROT_ERROR; + +typedef struct { + uint64_t vmcs_phys_pointer; + uint8_t expected_domain_type; + uint8_t degraded_domain_type; +} ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED; + +typedef union { + ENTRY_EVT_LOG_STARTED started; + ENTRY_EVT_LOG_STOPPED stopped; + ENTRY_EVT_LOG_INVALID_PARAM invalid_param; + ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION + handled_protection_exception; + ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC bios_unclaimed_rsc; + ENTRY_EVT_MLE_RSC_PROT_GRANTED mle_rsc_prot_granted; + ENTRY_EVT_MLE_RSC_PROT_DENIED mle_rsc_prot_denied; + ENTRY_EVT_MLE_RSC_UNPROT mle_rsc_unprot; + ENTRY_EVT_MLE_RSC_UNPROT_ERROR mle_rsc_unprot_error; + ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED mle_domain_type_degraded; +} LOG_ENTRY_DATA; + +typedef struct { + LOG_ENTRY_HEADER hdr; + LOG_ENTRY_DATA data; +} STM_LOG_ENTRY; + +#define STM_LOG_ENTRY_SIZE 256 +#define STM_CONFIG_SMI_UNBLOCKING_BY_VMX_OFF 0x1 + +// TXT debug +#define SW_SMI_STM_ADD_RUNTIME_RESOURCES_SUB_FUNC 0 +#define SW_SMI_STM_READ_BIOS_RESOURCES_SUB_FUNC 1 +#define SW_SMI_STM_REPLACE_BIOS_RESOURCES_SUB_FUNC 2 + +typedef struct { + uint32_t buffer_size; + uint32_t reserved; + // uint8_t Data[]; +} TXT_BIOS_DEBUG; + +#pragma pack(pop) + +#endif diff --git a/src/security/intel/stm/StmPlatformResource.c b/src/security/intel/stm/StmPlatformResource.c new file mode 100644 index 0000000000..6fef515052 --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.c @@ -0,0 +1,188 @@ +/* @file + * STM platform SMM resource + * + * Copyright (c) 2015, Intel Corporation. All rights reserved. + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be found + * at http://opensource.org/licenses/bsd-license.php. + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#include +#include +#include +#include + +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMCLIB) +#include +#else +#include +#endif +#include +#include + +#define RDWR_ACCS 3 +#define FULL_ACCS 7 + +// Fixed memory ranges +// +// TSEG memory! +static STM_RSC_MEM_DESC rsc_tseg_memory = {{MEM_RANGE, sizeof(STM_RSC_MEM_DESC)}, + 0, + 0, + FULL_ACCS}; + +// Flash part +static STM_RSC_MEM_DESC rsc_spi_memory = { + {MEM_RANGE, sizeof(STM_RSC_MEM_DESC)}, + 0xFE000000, + 0x01000000, + FULL_ACCS}; + +// ACPI +static STM_RSC_IO_DESC rsc_pm_io = {{IO_RANGE, sizeof(STM_RSC_IO_DESC)}, 0, 128}; + +// PCIE MMIO +static STM_RSC_MMIO_DESC rsc_pcie_mmio = {{MMIO_RANGE, sizeof(STM_RSC_MMIO_DESC)}, + 0, + 0, // Length + RDWR_ACCS}; + +// Local APIC +static STM_RSC_MMIO_DESC rsc_apic_mmio = {{MMIO_RANGE, sizeof(STM_RSC_MMIO_DESC)}, + 0, + 0x400, + RDWR_ACCS}; + +// Software SMI +static STM_RSC_TRAPPED_IO_DESC rsc_sw_smi_trap_io = { + {TRAPPED_IO_RANGE, sizeof(STM_RSC_TRAPPED_IO_DESC)}, + 0xB2, + 2}; + +// End of list +static STM_RSC_END rsc_list_end __attribute__((used)) = { + {END_OF_RESOURCES, sizeof(STM_RSC_END)}, 0}; + +// Common PCI devices +// +// LPC bridge +STM_RSC_PCI_CFG_DESC rsc_lpc_bridge_pci = { + {PCI_CFG_RANGE, sizeof(STM_RSC_PCI_CFG_DESC)}, + RDWR_ACCS, + 0, + 0, + 0x1000, + 0, + 0, + { + {1, 1, sizeof(STM_PCI_DEVICE_PATH_NODE), LPC_FUNCTION, + LPC_DEVICE}, + }, +}; + +// Template for MSR resources. +STM_RSC_MSR_DESC rsc_msr_tpl = { + {MACHINE_SPECIFIC_REG, sizeof(STM_RSC_MSR_DESC)}, +}; + +// MSR indices to register +typedef struct { + uint32_t msr_index; + uint64_t read_mask; + uint64_t write_mask; +} MSR_TABLE_ENTRY; + +MSR_TABLE_ENTRY msr_table[] = { + // Index Read Write + // MASK64 means need access, MASK0 means no need access. + {SMRR_PHYSBASE_MSR, MASK64, MASK0}, + {SMRR_PHYSMASK_MSR, MASK64, MASK0}, +}; + +/* + * Fix up PCIE resource. + */ +static void fixup_pciex_resource(void) +{ + // Find max bus number and PCIEX length + rsc_pcie_mmio.length = CONFIG_SA_PCIEX_LENGTH; // 0x10000000;// 256 MB + rsc_pcie_mmio.base = CONFIG_MMCONF_BASE_ADDRESS; +} + +/* + * Add basic resources to BIOS resource database. + */ +static void add_simple_resources(void) +{ + int Status = 0; + msr_t ReadMsr; + + ReadMsr = rdmsr(SMRR_PHYSBASE_MSR); + rsc_tseg_memory.base = ReadMsr.lo & 0xFFFFF000; + + ReadMsr = rdmsr(SMRR_PHYSMASK_MSR); + rsc_tseg_memory.length = (~(ReadMsr.lo & 0xFFFFF000) + 1); + + rsc_pm_io.base = (uint16_t)get_pmbase(); + + // Local APIC. We assume that all thteads are programmed identically + // despite that it is possible to have individual APIC address for + // each of the threads. If this is the case this programming should + // be corrected. + ReadMsr = rdmsr(IA32_APIC_BASE_MSR_INDEX); + rsc_apic_mmio.base = ((uint64_t)ReadMsr.lo & 0xFFFFF000) | + ((uint64_t)(ReadMsr.hi & 0x0000000F) << 32); + + // PCIEX BAR + fixup_pciex_resource(); + + Status |= add_pi_resource((void *)&rsc_tseg_memory, 1); + Status |= add_pi_resource((void *)&rsc_spi_memory, 1); + + Status |= add_pi_resource((void *)&rsc_pm_io, 1); + Status |= add_pi_resource((void *)&rsc_pcie_mmio, 1); + Status |= add_pi_resource((void *)&rsc_apic_mmio, 1); + Status |= add_pi_resource((void *)&rsc_sw_smi_trap_io, 1); + + Status |= add_pi_resource((void *)&rsc_lpc_bridge_pci, 1); + + if (Status != 0) + printk(BIOS_DEBUG, "STM - Error in adding simple resources\n"); +} + +/* + * Add MSR resources to BIOS resource database. + */ +static void add_msr_resources(void) +{ + uint32_t Status = 0; + uint32_t Index; + + for (Index = 0; Index < ARRAY_SIZE(msr_table); Index++) { + + rsc_msr_tpl.msr_index = (uint32_t)msr_table[Index].msr_index; + rsc_msr_tpl.read_mask = (uint64_t)msr_table[Index].read_mask; + rsc_msr_tpl.write_mask = (uint64_t)msr_table[Index].write_mask; + + Status |= add_pi_resource((void *)&rsc_msr_tpl, 1); + } + + if (Status != 0) + printk(BIOS_DEBUG, "STM - Error in adding MSR resources\n"); +} + +/* + * Add resources to BIOS resource database. + */ +void add_resources_cmd(void) +{ + + add_simple_resources(); + + add_msr_resources(); +} diff --git a/src/security/intel/stm/StmPlatformResource.h b/src/security/intel/stm/StmPlatformResource.h new file mode 100644 index 0000000000..7db2fc0330 --- /dev/null +++ b/src/security/intel/stm/StmPlatformResource.h @@ -0,0 +1,32 @@ +/* @file + * STM platform SMM resource + * + * Copyright (c) 2015, Intel Corporation. All rights reserved. + * This program and the accompanying materials are licensed and made available + * under the terms and conditions of the BSD License which accompanies this + * distribution. The full text of the license may be found at + * http://opensource.org/licenses/bsd-license.php. + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#ifndef _STM_PLATFORM_RESOURCE_H_ +#define _STM_PLATFORM_RESOURCE_H_ + +#define MASK0 0 +#define MASK64 0xFFFFFFFFFFFFFFFFull + +// LPC + +#define LPC_DEVICE 31 +#define LPC_FUNCTION 0 +#define R_ACPI_PM_BASE 0x40 +#define ACPI_PM_BASE_MASK 0xFFF8 + +/* + * Add resources to BIOS resource database. + */ +void add_resources_cmd(void); +#endif diff --git a/src/security/intel/stm/StmPlatformSmm.c b/src/security/intel/stm/StmPlatformSmm.c new file mode 100644 index 0000000000..d7064b07f5 --- /dev/null +++ b/src/security/intel/stm/StmPlatformSmm.c @@ -0,0 +1,204 @@ +/* @file + * STM platform SMM API + * + * Copyright (c) 2015, Intel Corporation. All rights reserved. + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be found + * at http://opensource.org/licenses/bsd-license.php. + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + * + */ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/* + * Load STM image to MSEG + * + * @retval SUCCESS STM is loaded to MSEG + */ +int load_stm_image(uintptr_t mseg) +{ + int status; + void *mseg_base; + uint32_t stm_buffer_size; + uint32_t stm_image_size; + bool stm_status; + + STM_HEADER *stm_header; + + // Extract STM image from FV + mseg_base = (void *)mseg; + stm_buffer_size = CONFIG_MSEG_SIZE; + stm_image_size = 0; + + memset((void *)mseg_base, 0, CONFIG_MSEG_SIZE); // clear the mseg + + stm_image_size = cbfs_boot_load_file("stm.bin", mseg_base, + stm_buffer_size, CBFS_TYPE_RAW); + printk(BIOS_DEBUG, "STM:loaded into mseg: 0x%p size: %u\n", mseg_base, + stm_image_size); + /* status is number of bytes loaded */ + stm_status = stm_check_stm_image(mseg_base, stm_image_size); + + if (!stm_status) { + printk(BIOS_DEBUG, "STM: Error in STM image\n"); + return -1; + } + + stm_header = mseg_base; + + stm_gen_4g_pagetable_x64((uint32_t)mseg_base + + stm_header->hw_stm_hdr.cr3_offset); + + // Debug stuff + printk(BIOS_DEBUG, + "STM: Header-Revision %d Features 0x%08x Cr3Offset 0x%08x\n", + stm_header->hw_stm_hdr.stm_header_revision, + stm_header->hw_stm_hdr.monitor_features, + stm_header->hw_stm_hdr.cr3_offset); + printk(BIOS_DEBUG, + "STM: Header-StaticImageSize: %d Cr3Location: 0x%08x\n", + stm_header->sw_stm_hdr.static_image_size, + ((uint32_t)mseg_base + stm_header->hw_stm_hdr.cr3_offset)); + + status = 0; // always return good for now + + return status; +} + +struct descriptor { + uint16_t limit; + uintptr_t base; +} __attribute__((packed)); + + +static void read_gdtr(struct descriptor *gdtr) +{ + __asm__ __volatile__("sgdt %0" : "=m"(*gdtr)); +} + +void setup_smm_descriptor(void *smbase, void *base_smbase, int32_t apic_id, + int32_t entry32_off) +{ + struct descriptor gdtr; + void *smbase_processor; + //msr_t smbase_msr; + + TXT_PROCESSOR_SMM_DESCRIPTOR *psd; + + smbase_processor = (void *) SMM_DEFAULT_BASE;//we are here + psd = smbase + SMM_PSD_OFFSET; + + printk(BIOS_DEBUG, + "STM: Smm Descriptor setup: Smbase: %p Smbase_processor: %p Psd: %p\n", + smbase, + smbase_processor, + psd); + + memset(psd, 0, sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR)); + + memcpy(&psd->signature, TXT_PROCESSOR_SMM_DESCRIPTOR_SIGNATURE, 8); + psd->smm_descriptor_ver_major = + TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MAJOR; + psd->smm_descriptor_ver_minor = + TXT_PROCESSOR_SMM_DESCRIPTOR_VERSION_MINOR; + psd->smm_smi_handler_rip = + (uint64_t)((uintptr_t)base_smbase + SMM_ENTRY_OFFSET + + entry32_off); + psd->local_apic_id = apic_id; + psd->size = sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); + psd->acpi_rsdp = 0; + psd->bios_hw_resource_requirements_ptr = + (uint64_t)((uintptr_t)get_stm_resource()); + psd->smm_cs = ROM_CODE_SEG; + psd->smm_ds = ROM_DATA_SEG; + psd->smm_ss = ROM_DATA_SEG; + psd->smm_other_segment = ROM_DATA_SEG; + psd->smm_tr = SMM_TASK_STATE_SEG; + + + // At this point the coreboot smm_stub is relative to the default + // smbase and not the one for the smi handler in tseg. So we have + // to adjust the gdtr.base + + read_gdtr(&gdtr); + + gdtr.base -= (uintptr_t) smbase_processor; + gdtr.base += (uintptr_t) base_smbase; + + psd->smm_gdt_ptr = gdtr.base; + psd->smm_gdt_size = gdtr.limit + 1; // the stm will subtract, so add + printk(BIOS_DEBUG, "STM: Smm Descriptor setup complete - Smbase: %p Psd: %p\n", + smbase, psd); +} + +extern uint8_t *stm_resource_heap; + +#define FXSAVE_SIZE 512 + +static int stm_load_status = 0; + +void stm_setup(uintptr_t mseg, int cpu, int num_cpus, uintptr_t smbase, + uintptr_t base_smbase, uint32_t offset32) +{ + msr_t InitMseg; + msr_t MsegChk; + uintptr_t addr_calc; // used to calculate the stm resource heap area + + printk(BIOS_DEBUG, "STM: set up for cpu %d/%d\n", cpu, num_cpus); + if (cpu == 0) { + + // need to create the BIOS resource list once + // first calculate the location in SMRAM + addr_calc = (mseg - (CONFIG_SMM_MODULE_STACK_SIZE * num_cpus)); + + if (CONFIG(SSE)) + addr_calc -= FXSAVE_SIZE * num_cpus; + + addr_calc -= CONFIG_BIOS_RESOURCE_LIST_SIZE; + stm_resource_heap = (uint8_t *) addr_calc; + printk(BIOS_DEBUG, "STM: stm_resource_heap located at %p\n", + stm_resource_heap); + //setup the the list + add_resources_cmd(); + + stm_load_status = load_stm_image(mseg); + } + + if (stm_load_status == 0) { + // enable STM for this cpu + InitMseg.lo = mseg | IA32_SMM_MONITOR_VALID; + InitMseg.hi = 0; + + wrmsr(IA32_SMM_MONITOR_CTL_MSR, InitMseg); + + MsegChk = rdmsr(IA32_SMM_MONITOR_CTL_MSR); + + printk(BIOS_DEBUG, "STM: MSEG Initialized (%d) 0x%08x 0x%08x\n", + cpu, MsegChk.hi, MsegChk.lo); + + // setup the descriptor for this cpu + setup_smm_descriptor((void *)smbase, (void *) base_smbase, + cpu, offset32); + } else { + printk(BIOS_DEBUG, + "STM: Error in STM load, STM not enabled: %d\n", + cpu); + } +} From c294fe792c5be9b265236d41b381ee9e15d1d41e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 5 Feb 2020 10:54:25 +0100 Subject: [PATCH 083/151] 3rdparty/blobs: Update to include STM binary Change-Id: I5f053c1270bab71aeab3bb785c60417419736b44 Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/38717 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich Reviewed-by: Stefan Reinauer Reviewed-by: Martin Roth --- 3rdparty/blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 034b278184..7ad2d22452 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 034b27818450428f70aa9316c8bd0d65bacd8ee8 +Subproject commit 7ad2d22452225a14c19b17570cb77920d8fc81a5 From c34ebab4108965c824de4e1271c3f15598567fc5 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Mon, 25 Nov 2019 16:42:56 +0100 Subject: [PATCH 084/151] libpayload: Make pci and endian handling -Wconversion safe Change-Id: Ibd1b179d647f105579bd74b071344668ca0a41ef Signed-off-by: Patrick Georgi Reviewed-on: https://review.coreboot.org/c/coreboot/+/37202 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- payloads/libpayload/include/endian.h | 10 ++++--- payloads/libpayload/include/pci.h | 8 +++--- payloads/libpayload/libpci/libpci.c | 40 ++++++++++++++-------------- 3 files changed, 30 insertions(+), 28 deletions(-) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index dee45f227b..037517c88f 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -86,28 +86,30 @@ static inline uint16_t be16dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return ((p[0] << 8) | p[1]); + return (uint16_t)((p[0] << 8) | p[1]); } static inline uint32_t be32dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return (((unsigned)p[0] << 24) | (p[1] << 16) | (p[2] << 8) | p[3]); + return (((uint32_t)p[0] << 24) | (uint32_t)(p[1] << 16) | + (uint32_t)(p[2] << 8) | p[3]); } static inline uint16_t le16dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return ((p[1] << 8) | p[0]); + return (uint16_t)((p[1] << 8) | p[0]); } static inline uint32_t le32dec(const void *pp) { uint8_t const *p = (uint8_t const *)pp; - return ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | p[0]); + return ((uint32_t)(p[3] << 24) | (uint32_t)(p[2] << 16) | + (uint32_t)(p[1] << 8) | p[0]); } static inline void bebitenc(void *pp, uint32_t u, uint8_t b) diff --git a/payloads/libpayload/include/pci.h b/payloads/libpayload/include/pci.h index ff07d5c94d..a1bac4ab60 100644 --- a/payloads/libpayload/include/pci.h +++ b/payloads/libpayload/include/pci.h @@ -91,11 +91,11 @@ typedef u32 pcidev_t; #define HEADER_TYPE_CARDBUS 2 #define HEADER_TYPE_MULTIFUNCTION 0x80 -#define PCI_ADDR(_bus, _dev, _fn, _reg) \ -(0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8) | (_reg & ~3)) +#define PCI_DEV(_bus, _dev, _fn) (0x80000000 | \ +(uint32_t)(_bus << 16) | (uint32_t)(_dev << 11) | (uint32_t)(_fn << 8)) -#define PCI_DEV(_bus, _dev, _fn) \ -(0x80000000 | (_bus << 16) | (_dev << 11) | (_fn << 8)) +#define PCI_ADDR(_bus, _dev, _fn, _reg) \ +(PCI_DEV(_bus, _dev, _fn) | (uint8_t)(_reg & ~3)) #define PCI_BUS(_d) ((_d >> 16) & 0xff) #define PCI_SLOT(_d) ((_d >> 11) & 0x1f) diff --git a/payloads/libpayload/libpci/libpci.c b/payloads/libpayload/libpci/libpci.c index 82203a16e9..fd0332e067 100644 --- a/payloads/libpayload/libpci/libpci.c +++ b/payloads/libpayload/libpci/libpci.c @@ -40,34 +40,34 @@ static pcidev_t libpci_to_lb(struct pci_dev *dev) /* libpci interface */ u8 pci_read_byte(struct pci_dev *dev, int pos) { - return pci_read_config8(libpci_to_lb(dev), pos); + return pci_read_config8(libpci_to_lb(dev), (uint16_t)pos); } u16 pci_read_word(struct pci_dev *dev, int pos) { - return pci_read_config16(libpci_to_lb(dev), pos); + return pci_read_config16(libpci_to_lb(dev), (uint16_t)pos); } u32 pci_read_long(struct pci_dev *dev, int pos) { - return pci_read_config32(libpci_to_lb(dev), pos); + return pci_read_config32(libpci_to_lb(dev), (uint16_t)pos); } int pci_write_byte(struct pci_dev *dev, int pos, u8 data) { - pci_write_config8(libpci_to_lb(dev), pos, data); + pci_write_config8(libpci_to_lb(dev), (uint16_t)pos, data); return 1; /* success */ } int pci_write_word(struct pci_dev *dev, int pos, u16 data) { - pci_write_config16(libpci_to_lb(dev), pos, data); + pci_write_config16(libpci_to_lb(dev), (uint16_t)pos, data); return 1; /* success */ } int pci_write_long(struct pci_dev *dev, int pos, u32 data) { - pci_write_config32(libpci_to_lb(dev), pos, data); + pci_write_config32(libpci_to_lb(dev), (uint16_t)pos, data); return 1; /* success */ } @@ -110,29 +110,29 @@ char *pci_filter_parse_slot(struct pci_filter* filter, const char* id) char *funcp = strrchr(id, '.'); if (funcp) { - filter->func = strtoul(funcp+1, &endptr, 0); + filter->func = strtol(funcp+1, &endptr, 0); if (endptr[0] != '\0') return invalid_pci_device_string; } char *devp = strrchr(id, ':'); if (!devp) { - filter->dev = strtoul(id, &endptr, 0); + filter->dev = strtol(id, &endptr, 0); } else { - filter->dev = strtoul(devp+1, &endptr, 0); + filter->dev = strtol(devp+1, &endptr, 0); } if (endptr != funcp) return invalid_pci_device_string; if (!devp) return NULL; char *busp = strchr(id, ':'); if (busp == devp) { - filter->bus = strtoul(id, &endptr, 0); + filter->bus = strtol(id, &endptr, 0); } else { - filter->bus = strtoul(busp+1, &endptr, 0); + filter->bus = strtol(busp+1, &endptr, 0); } if (endptr != funcp) return invalid_pci_device_string; if (busp == devp) return NULL; - filter->domain = strtoul(id, &endptr, 0); + filter->domain = strtol(id, &endptr, 0); if (endptr != busp) return invalid_pci_device_string; return NULL; @@ -155,15 +155,15 @@ int pci_filter_match(struct pci_filter* pf, struct pci_dev* dev) return 1; } -static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus) +static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, uint8_t bus) { int devfn; u32 val; unsigned char hdr; for (devfn = 0; devfn < 0x100; devfn++) { - int func = devfn & 0x7; - int slot = (devfn >> 3) & 0x1f; + uint8_t func = devfn & 0x7; + uint8_t slot = (devfn >> 3) & 0x1f; val = pci_read_config32(PCI_DEV(bus, slot, func), REG_VENDOR_ID); @@ -179,7 +179,7 @@ static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus) dev->dev = slot; dev->func = func; dev->vendor_id = val & 0xffff; - dev->device_id = val >> 16; + dev->device_id = (uint16_t)(val >> 16); dev->next = 0; hdr = pci_read_config8(PCI_DEV(bus, slot, func), @@ -187,10 +187,10 @@ static struct pci_dev *pci_scan_single_bus(struct pci_dev *dev, int bus) hdr &= 0x7F; if (hdr == HEADER_TYPE_BRIDGE || hdr == HEADER_TYPE_CARDBUS) { - unsigned int busses; - busses = pci_read_config32(PCI_DEV(bus, slot, func), - REG_PRIMARY_BUS); - busses = (busses >> 8) & 0xFF; + uint8_t busses; + busses = (uint8_t)(pci_read_config32( + PCI_DEV(bus, slot, func), + REG_PRIMARY_BUS) >> 8); /* Avoid recursion if the new bus is the same as * the old bus (insert lame The Who joke here) */ From a547584445c086fdcd0833bbbe649a11019fcd11 Mon Sep 17 00:00:00 2001 From: ashk Date: Tue, 6 Aug 2019 19:00:25 +0530 Subject: [PATCH 085/151] trogdor: Add T32 scripts for full boot chain Change-Id: I4ec1d4f722523f240fa293dd79235ab4e32e4489 Signed-off-by: Ashwin Kumar Reviewed-on: https://review.coreboot.org/c/coreboot/+/35505 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- util/qualcomm/scripts/cmm/clear_bss.cmm | 16 -- util/qualcomm/scripts/cmm/debug_cb_common.cmm | 109 +++------ .../qualcomm/scripts/cmm/debug_cb_trogdor.cmm | 131 +++++++++++ .../scripts/cmm/debug_chroot_common.cmm | 210 ++++++++++++++++++ .../scripts/cmm/debug_chroot_trogdor.cmm | 131 +++++++++++ .../scripts/cmm/pbl32_to_bootblock64_jump.cmm | 15 -- 6 files changed, 503 insertions(+), 109 deletions(-) delete mode 100755 util/qualcomm/scripts/cmm/clear_bss.cmm create mode 100644 util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm create mode 100644 util/qualcomm/scripts/cmm/debug_chroot_common.cmm create mode 100644 util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm delete mode 100644 util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm diff --git a/util/qualcomm/scripts/cmm/clear_bss.cmm b/util/qualcomm/scripts/cmm/clear_bss.cmm deleted file mode 100755 index 16eaac71d8..0000000000 --- a/util/qualcomm/scripts/cmm/clear_bss.cmm +++ /dev/null @@ -1,16 +0,0 @@ -d.a 0x80000000 mov x0,#0x8c -d.a 0x80000004 lsl x0, x0, #0x14 -d.a 0x80000008 mov x1,#0x18 -d.a 0x8000000c lsl x1,x1, #0x10 -d.a 0x80000010 mov x2,#0x0 -d.a 0x80000014 mov x3,#0x80 -d.a 0x80000018 lsl x3, x3, #0x18 -d.a 0x8000001c add x3, x3, #0x14 -d.a 0x80000020 str x2,[x0] -d.a 0x80000024 sub x1, x1, #0x8 -d.a 0x80000028 add x0, x0, #0x8 -d.a 0x8000002c cmp x1,0x0 -d.a 0x80000030 b.ne 0x20 -d.a 0x80000034 b 0x34 -r.s pc 0x80000000 -go diff --git a/util/qualcomm/scripts/cmm/debug_cb_common.cmm b/util/qualcomm/scripts/cmm/debug_cb_common.cmm index 5959ee11e6..bf90575823 100644 --- a/util/qualcomm/scripts/cmm/debug_cb_common.cmm +++ b/util/qualcomm/scripts/cmm/debug_cb_common.cmm @@ -33,8 +33,6 @@ LOCAL &RAMStage // Ram Stage stop? LOCAL &BL31Stage // BL31 Stage stop? LOCAL &DCStage // Depthcharge Stage stop? -LOCAL &KernelSyms // Load Kernel Symbols? - LOCAL &RAMLoad // T32 Load Code? ;============================================================================ @@ -45,10 +43,10 @@ LOCAL &RAMLoad // T32 Load Code? ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName // Parse for RAMLoad first - if (STR.CP("&ImageName","RAM,*")) + if (STR.CP("&ImageName","LOAD,*")) ( &RAMLoad=TRUE() - &ImageName=STR.CUT("&ImageName",4) + &ImageName=STR.CUT("&ImageName",5) ) else &RAMLoad=FALSE() @@ -63,7 +61,6 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName &RAMStage=TRUE() ;&BL31Stage=TRUE() &DCStage=TRUE() - &KernelSyms=STRING.CP("&ImageName", "*KERNEL*") ) else ( @@ -72,14 +69,12 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName &ROMStage=STRING.CP("&ImageName","*ROM*") &QCLStage=STRING.CP("&ImageName","*QCL*") &RAMStage=STRING.CP("&ImageName","*RAM*") - &BL31Stage=STRING.CP("&ImageName","*BL31*") + ;&BL31Stage=STRING.CP("&ImageName","*BL31*") &DCStage=STRING.CP("&ImageName","*DC*") - &KernelSyms=STRING.CP("&ImageName", "*KERNEL*") ) PRINT %String "Debug Script: debug_cb_common.cmm" PRINT %String "Images to debug: &ImageName" - PRINT %String "Loading Kernel Symbols: &KernelSyms" PRINT %String "RAMLoad Requested: &RAMLoad" PRINT %String "BootBlock Entry Addr: &BBEntryAddr" PRINT %String "VerStage Entry Addr: &VEREntryAddr" @@ -104,31 +99,17 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName if &BBStage ( - IF "&debug"=="" - ( - d.load.binary build/coreboot.rom 0xA0000000 - ) - &imgpath="build\cbfs\fallback\bootblock.elf" + &imgpath="build\cbfs\fallback\bootblock.raw.elf" if (&RAMLoad) d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath else d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode - ;uncomment b.s if not simulating (CONFIG_SOC_SIMULATE) - ;b.s run_romstage /o - ;d.set &PreRamConsoleAddr++0x8000 0 - d.dump &PreRamConsoleAddr /spotlight - IF (STR.CP("&debug","DEBUG")) - ( - print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" - print %String "Press enter to go to next stage" - enter - ) - ELSE - ( - go - enddo - ) + d.l + + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter ) go &VEREntryAddr @@ -163,22 +144,29 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName enter ) +;;;; START OF COMMENTED OUT CODE TO SKIP QCLIB DEBUG +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + ; go &QCLEntryAddr ; wait !run() -; + ; if &QCLStage ; ( -; &imgpath="3rdparty\blobs\soc\qualcomm\sdm845\QcLib.elf" + ; if (&RAMLoad) -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /noclear -; else -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode /noclear -; +; d.load ...\QcLib.dll +; else +; d.load ...\QcLib.dll + + ; print %String "Now the control is in QCLStage, press enter after debugging to go to next stage" ; print %String "Press enter to go to next stage" ; enter ; ) +;;;; END OF QCLIB COMMENTED OUT CODE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + go &RAMEntryAddr wait !run() @@ -194,24 +182,9 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName enter ) -; BL31 disabled for now -; Next block of code commented out -; go &BL31EntryAddr -; wait !run() -; -; if &BL31Stage -; ( -; &imgpath="build\bl31.elf" -; if (&RAMLoad) -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath -; else -; d.load.elf &imgpath /strippart "coreboot" /sourcepath &srcpath /nocode -; y.spath.srd 3rdparty/arm-trusted-firmware -; print %String "Now the control is in BL31, press enter after debugging to go to next stage" -; print %String "Press enter to go to next stage" -; enter -; ) -; End of commented out code block: bl31 +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;;; BL31 DEBUG CODE WOULD BE ADDED HERE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; go &DCEntryAddr wait !run() @@ -220,36 +193,16 @@ ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName ( &imgpath="payloads\external\depthcharge\depthcharge\build\depthcharge.elf" symbol.sourcepath.setbasedir &srcpath\payloads + y.spath.srd payloads\external\depthcharge\depthcharge\src if (&RAMLoad) d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath else d.load.elf &imgpath /strippart "payloads" /sourcepath &srcpath /nocode - b.d /all - b.set main - b.set halt - b.set &KernelEntryAddr ; kernel entry point - y.spath.srd + payloads/external/depthcharge/depthcharge - y.spath.srd + 3rdparty\vboot_reference - d.dump &RamConsoleAddr /spotlight - &CBTablePtr=Register(X0) - Data.SAVE.Binary CBTablePtr.bin &CBTablePtr++0x400 - print %String "Now the control is in Depthcharge, press enter after debugging to run free" - ;print %String "Use this command to load kernel symbols: d.load.elf vmlinux /nocode /strippart kernel" - print %String "Press enter when done debugging Depthcharge" - enter + print %String "Now the control is in depthcharge, end of script" + d.l + ;b.s main + ;Execute this command in T32 if you start debugging vboot code, e.g. vboot_select_and_load_kernel() + ;y.spath.srd 3rdparty\vboot\firmware ) -; go &KernelEntryAddr -; wait !run() -; -; if &KernelSyms -; ( -; print %String "Kernel Symbols are being loaded, this requires two files in coreboot root tree:" -; print %String "vmlinux needs to be copied from ChromiumOS build tree" -; print %String "msm-4.4 needs to be symbolic link to kernel source tree" -; d.load.elf vmlinux /strippart "msm-4.4" /nocode -; y.spath.srd msm-4.4 -; print %String "This script now concludes at kernel entry point" -; ) - enddo diff --git a/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm new file mode 100644 index 0000000000..5d72ff792e --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_cb_trogdor.cmm @@ -0,0 +1,131 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2019, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_cb_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName &RegAddress + + // Later these can be parameterized + &TargetPkg="trogdorPkg" + + // These settings come from .../src/soc/qualcomm/sc7180/include/soc/memlayout.ld + &BBEntryAddr=0x14815000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x1486c950 + &RAMEntryAddr=0xA0800000 + &BL31EntryAddr=0x80C00000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14830800 + &VBoot2Work=0x1484B000 + &Stack=0x14847000 + &Ttb=0x14839000 + &Timestamp=0x14838800 + &PreRamCbfsCache=0x1481F000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\.. + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + if (STR.CP("&ImageName","0X*")) + ( + &RegAddress=&ImageName + &ImageName="" + ) + &RegAddress=STRING.UPR("&RegAddress") + + PRINT %String "ImageName: &ImageName" + PRINT %String "RegAddress: &RegAddress" + + sys.d + sys.up + b.d + y.reset + + if (STR.CP("&RegAddress","0X*")) + D.S EZAXI:&RegAddress %LE %Long 0x80000000 + + go &BBEntryAddr + wait !run() + + DO debug_cb_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_chroot_common.cmm b/util/qualcomm/scripts/cmm/debug_chroot_common.cmm new file mode 100644 index 0000000000..0e1d58baf5 --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_chroot_common.cmm @@ -0,0 +1,210 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2018, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_chroot_common.cmm +; +; Description: +; Debug chroot coreboot Environment +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &BBStage // Bootblock Stage stop? +LOCAL &VERStage // Verify Stage stop? +LOCAL &ROMStage // Rom Stage stop? +LOCAL &QCLStage // QCL Stage stop? +LOCAL &RAMStage // Ram Stage stop? +LOCAL &BL31Stage // BL31 Stage stop? +LOCAL &DCStage // Depthcharge Stage stop? + +LOCAL &RAMLoad // T32 Load Code? + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &TargetPkg &srcpath &xblsrcpath &ImageName + + // Parse for RAMLoad first + if (STR.CP("&ImageName","LOAD,*")) + ( + &RAMLoad=TRUE() + &ImageName=STR.CUT("&ImageName",5) + ) + else + &RAMLoad=FALSE() + + // Parse &ImageName the easy way + if (STR.CP("&ImageName","*ALL*")) + ( + &BBStage=TRUE() + &VERStage=TRUE() + &ROMStage=TRUE() + &QCLStage=TRUE() + &RAMStage=TRUE() + ;&BL31Stage=TRUE() + &DCStage=TRUE() + ) + else + ( + &BBStage=STRING.CP("&ImageName","*BB*") + &VERStage=STRING.CP("&ImageName","*VER*") + &ROMStage=STRING.CP("&ImageName","*ROM*") + &QCLStage=STRING.CP("&ImageName","*QCL*") + &RAMStage=STRING.CP("&ImageName","*RAM*") + ;&BL31Stage=STRING.CP("&ImageName","*BL31*") + &DCStage=STRING.CP("&ImageName","*DC*") + ) + + PRINT %String "Debug Script: debug_chroot_common.cmm" + PRINT %String "Images to debug: &ImageName" + PRINT %String "RAMLoad Requested: &RAMLoad" + PRINT %String "BootBlock Entry Addr: &BBEntryAddr" + PRINT %String "VerStage Entry Addr: &VEREntryAddr" + PRINT %String "RomStage Entry Addr: &ROMEntryAddr" + PRINT %String "QCLStage Entry Addr: &QCLEntryAddr" + PRINT %String "RamStage Entry Addr: &RAMEntryAddr" + PRINT %String "BL31 Entry Addr: &BL31EntryAddr" + PRINT %String "DepthCharge Entry Addr: &DCEntryAddr" + PRINT %String "Kernel Entry Addr: &KernelEntryAddr" + PRINT %String "PreRamCbfsCache: &PreRamCbfsCache" + PRINT %String "PreRamConsoleAddr: &PreRamConsoleAddr" + PRINT %String "VBoot2Work: &VBoot2Work" + PRINT %String "Stack: &Stack" + PRINT %String "Ttb: &Ttb" + PRINT %String "Timestamp &Timestamp" + PRINT %String "RamConsoleAddr &RamConsoleAddr" + PRINT %String "CbmemTop &CbmemTop" + PRINT %String "PostRamCbfsCache &PostRamCbfsCache" + + // HW at BB entry, first stop: bootblock + //////////////////////////////////////// + + if &BBStage + ( + &imgpath="build-trogdor\cbfs\fallback\bootblock.raw.elf" + if (&RAMLoad) + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath + else + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath /nocode + + d.l + + print %String "Now the control is in BootBlock, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + + go &VEREntryAddr + wait !run() + + if &VERStage + ( + &imgpath="build-trogdor\cbfs\fallback\verstage.elf" + if (&RAMLoad) + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath /noclear + else + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath /nocode /noclear + + print %String "Now the control is in VERStage, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + + go &ROMEntryAddr + wait !run() + + if &ROMStage + ( + &imgpath="build-trogdor\cbfs\fallback\romstage.elf" + if (&RAMLoad) + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath + else + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath /nocode + + print %String "Now the control is in ROMStage, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + +;;;; START OF COMMENTED OUT CODE TO SKIP QCLIB DEBUG +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; go &QCLEntryAddr +; wait !run() + +; if &QCLStage +; ( + +; if (&RAMLoad) +; d.load ...\QcLib.dll +; else +; d.load ...\QcLib.dll + + +; print %String "Now the control is in QCLStage, press enter after debugging to go to next stage" +; print %String "Press enter to go to next stage" +; enter +; ) + +;;;; END OF QCLIB COMMENTED OUT CODE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + go &RAMEntryAddr + wait !run() + + if &RAMStage + ( + &imgpath="build-trogdor\cbfs\fallback\ramstage.elf" + if (&RAMLoad) + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath + else + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath /nocode + + print %String "Now the control is in RAMStage, press enter after debugging to go to next stage" + print %String "Press enter to go to next stage" + enter + ) + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;;;;; BL31 DEBUG CODE WOULD BE ADDED HERE +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + go &DCEntryAddr + wait !run() + + if &DCStage + ( + &srcpath="..\..\..\depthcharge-9999\work\depthcharge-9999\src" + &imgpath="..\..\..\depthcharge-9999\work\depthcharge-9999\trogdor\depthcharge.elf" + symbol.sourcepath.setbasedir &srcpath + if (&RAMLoad) + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath + else + d.load.elf &imgpath /strippart 9 /sourcepath &srcpath /nocode + + print %String "Now the control is in depthcharge, end of script" + d.l + ;b.s main + ;Execute this command in T32 if you start debugging vboot code, e.g. vboot_select_and_load_kernel() + ;y.spath.sbd 3rdparty\vboot\firmware + ) + + enddo diff --git a/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm b/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm new file mode 100644 index 0000000000..d93a4c0374 --- /dev/null +++ b/util/qualcomm/scripts/cmm/debug_chroot_trogdor.cmm @@ -0,0 +1,131 @@ +;============================================================================ +;## +;## This file is part of the coreboot project. +;## +;## Copyright (C) 2019, The Linux Foundation. All rights reserved. +;## +;## This program is free software; you can redistribute it and/or modify +;## it under the terms of the GNU General Public License version 2 and +;## only version 2 as published by the Free Software Foundation. +;## +;## This program is distributed in the hope that it will be useful, +;## but WITHOUT ANY WARRANTY; without even the implied warranty of +;## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;## GNU General Public License for more details. +;## +;============================================================================ +; Name: +; debug_chroot_trogdor.cmm +; +; Description: +; Debug coreboot trogdor front-end (in chroot environment) +;============================================================================ + +;============================================================================ +; CMM script variables +;============================================================================ + +LOCAL &TargetPkg + +GLOBAL &BBEntryAddr // Bootblock Entry +GLOBAL &BBExitAddr // Bootblock Exit to Xbl-Sec +GLOBAL &VEREntryAddr // Verstage Entry +GLOBAL &ROMEntryAddr // Romstage Entry +GLOBAL &QCLEntryAddr // QCLstage Entry +GLOBAL &RAMEntryAddr // Ramstage Entry +GLOBAL &BL31EntryAddr // BL31 Entry +GLOBAL &DCEntryAddr // Depthcharge Entry + +GLOBAL &PreRamConsoleAddr +GLOBAL &RamConsoleAddr +GLOBAL &PreRamCbfsCache +GLOBAL &VBoot2Work +GLOBAL &Stack +GLOBAL &Ttb +GLOBAL &Timestamp +GLOBAL &CbmemTop +GLOBAL &PostRamCbfsCache + +GLOBAL &CBTablePtr + +;============================================================================ + +;--------------------------------------------------- +; Entry point +;--------------------------------------------------- +ENTRY &ImageName &RegAddress + + // Later these can be parameterized + &TargetPkg="trogdorPkg" + + // These settings come from .../src/soc/qualcomm/sc7180/include/soc/memlayout.ld + &BBEntryAddr=0x14815000 + &VEREntryAddr=0x14680000 + &ROMEntryAddr=0x14680000 + &QCLEntryAddr=0x1486c950 + &RAMEntryAddr=0xA0800000 + &BL31EntryAddr=0x80C00000 + &DCEntryAddr=0xF1000000 + &KernelEntryAddr=0xD0000000 + + &PreRamConsoleAddr=0x14830800 + &VBoot2Work=0x1484B000 + &Stack=0x14847000 + &Ttb=0x14839000 + &Timestamp=0x14838800 + &PreRamCbfsCache=0x1481F000 + &CbmemTop=0x280000000 + &PostRamCbfsCache=0x9F800000 + // End of memlayout.ld settings + + // Common commands irrespective of &Mode + PATH + &CwDir=os.pwd() + PATH + &CwDir + + // position at top of coreboot tree + // find depth count for source loading + cd ..\..\..\..\..\..\..\chroot\build\trogdor\tmp\portage\sys-boot\coreboot-9999\work\coreboot-9999 + &srcpath=os.pwd() + + +;--------------------------------------------------- +; Setup area and log +;--------------------------------------------------- + area.clear + area.reset + area.create CB_Logs 1000. 8192. + area.select CB_Logs + + area.view CB_Logs + + PRINT %String "Source Path: &srcpath" + + symbol.sourcepath.setbasedir &srcpath\src + + // Make parsing simple, upper-case parameters + &ImageName=STRING.UPR("&ImageName") + if (STR.CP("&ImageName","0X*")) + ( + &RegAddress=&ImageName + &ImageName="" + ) + &RegAddress=STRING.UPR("&RegAddress") + + PRINT %String "ImageName: &ImageName" + PRINT %String "RegAddress: &RegAddress" + + sys.d + sys.up + b.d + y.reset + + if (STR.CP("&RegAddress","0X*")) + D.S EZAXI:&RegAddress %LE %Long 0x80000000 + + go &BBEntryAddr + wait !run() + + DO debug_chroot_common.cmm &TargetPkg &srcpath &xblsrcpath &ImageName + + enddo diff --git a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm b/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm deleted file mode 100644 index bebf85d1c4..0000000000 --- a/util/qualcomm/scripts/cmm/pbl32_to_bootblock64_jump.cmm +++ /dev/null @@ -1,15 +0,0 @@ -PER.Set.simple SPR:0x36100 %Long 00c5183C -D.S AZSD:0x8600034 %LE %Long 0x8600000 -D.S AZSD:0x8600000 %LE %Long 0x1400000 -d.a 0x8600004 ldr r0,0x8600034 -d.a 0x8600008 mcr p15,0x0,r0,c12,c0,1 -d.a 0x860000c dsb -d.a 0x8600010 isb -d.a 0x8600014 mrc p15,0x0,r1,c12,c0,2 -d.a 0x8600018 orr r1,r1,0x3 -d.a 0x860001c mcr p15,0x0,r1,c12,c0,2 -d.a 0x8600020 isb -d.a 0x8600024 wfi -r.s pc 0x8600004 -go -b From eae254efb324e89d30d0f6abd3e40d6e951abba9 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Mon, 6 Jan 2020 17:44:10 +0800 Subject: [PATCH 086/151] mb/google/hatch: Add noise mitigation setting for dratini/jinlon Enable acoustic noise mitigation, the slow slew rates are fast time divided by 8 and disable Fast PKG C State Ramp (IA, GT, SA). BRANCH=hatch BUG=b:143501884 TEST=build and verify that noise reduce. Change-Id: I65f47288a7b1da98296fdba87ab5ca0c3a567aaf Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/38212 Reviewed-by: Paul Menzel Reviewed-by: Tim Wawrzynczak Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- .../google/hatch/variants/dratini/overridetree.cb | 9 +++++++++ .../google/hatch/variants/jinlon/overridetree.cb | 9 +++++++++ 2 files changed, 18 insertions(+) diff --git a/src/mainboard/google/hatch/variants/dratini/overridetree.cb b/src/mainboard/google/hatch/variants/dratini/overridetree.cb index f820629198..5c30a5a93f 100644 --- a/src/mainboard/google/hatch/variants/dratini/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dratini/overridetree.cb @@ -17,6 +17,15 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb index c9613d2677..f3f6c3b949 100644 --- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb +++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb @@ -17,6 +17,15 @@ chip soc/intel/cannonlake [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | From 7354605f869b60a9f3bf3495dee4ccdceb0da0a4 Mon Sep 17 00:00:00 2001 From: Piotr Kleinschmidt Date: Wed, 9 Oct 2019 11:47:03 +0200 Subject: [PATCH 087/151] mb/pcengines/apu2: use AGESA 1.0.0.4 with adjusted AGESA header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PC Engines apu2 platform uses AGESA 1.0.0.4, because upstream AGESA 1.0.0.A doesn't work on apu2 - the platform doesn't boot. To properly utilize AGESA 1.0.0.4 we need to adjust AGESA header to state, which is compatible with AGESA 1.0.0.4 version. Cut out the changes introduced in CB:11225 exclusively for apu2 board. TEST=boot PC Engines apu2 and launch Debian Linux Change-Id: I3d85ee14e35dae8079e8d552b6530a3867f65876 Signed-off-by: Piotr Kleinschmidt Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/35906 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/pcengines/apu2/Kconfig | 10 ++++++++++ src/vendorcode/amd/pi/00730F01/AGESA.h | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 8c713e5f67..501d583c68 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -114,4 +114,14 @@ config DIMM_SPD_SIZE int default 128 +config AGESA_USE_1_0_0_4_HEADER + bool + default y + help + Due to a bug in AGESA 1.0.0.A affecting boards without UMA, it is + impossible to use the newest blob. Using an older 1.0.0.4 blob + workarounds the problem, however some headers changes between blob + revisions. This option removes the changes in headers introduced + with AGESA 1.0.0.A to fit the 1.0.0.4 revision. + endif # BOARD_PCENGINES_APU2 diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h index c25b631cb2..5a3ee5b9f6 100644 --- a/src/vendorcode/amd/pi/00730F01/AGESA.h +++ b/src/vendorcode/amd/pi/00730F01/AGESA.h @@ -775,6 +775,7 @@ typedef enum { DP_VS_0_4V_9_5DB = 0x18 ///< 0x18 } DP_FIXED_VOLT_SWING_TYPE; +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) /// Alternative DRAM MAC typedef enum { MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC @@ -785,6 +786,7 @@ typedef enum { MAC_300k, ///< Assign 5 to 300k MAC_200k, ///< Assign 6 to 200k } DRAM_MAXIMUM_ACTIVATE_COUNT; +#endif // Macro for statically initializing various structures #define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} @@ -1547,7 +1549,9 @@ typedef struct _CH_TIMING_STRUCT { ///< 667 (MHz) ///< 800 (MHz) ///< and so on... +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) OUT UINT8 Mac; ///< Maximum Activate Count +#endif OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) OUT UINT8 Trcd; ///< DCT Trcd (busclocks) OUT UINT8 Trp; ///< DCT Trp (busclocks) @@ -1803,6 +1807,7 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) // Dram Mac Default IN UINT8 DramMacDefault; ///< Default Maximum Activate Count @@ -1818,6 +1823,7 @@ typedef struct _MEM_PARAMETER_STRUCT { ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE} // Extended temperature range +#endif // Online Spare IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. @@ -2721,8 +2727,10 @@ typedef struct { IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. +#if CONFIG(AGESA_USE_1_0_0_4_HEADER) IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range +#endif IN UINT32 CfgPowerDownMode; ///< Power Down Mode. IN BOOLEAN CfgOnlineSpare; ///< Online Spare. IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. From faa1118fc7d6d80d9c37bab8b9330325d8157466 Mon Sep 17 00:00:00 2001 From: Eugene Myers Date: Thu, 6 Feb 2020 10:37:01 -0500 Subject: [PATCH 088/151] cpu/x86: Put guard around align for smm_save_state_size The STM support aligns the smm_save_state_size. However, this creates issue for some platforms because of this value being hard coded to 0x400 Signed-off-by: Eugene D. Myers Change-Id: Ia584f7e9b86405a12eb6cbedc3a2615a8727f69e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38734 Reviewed-by: Patrick Rudolph Reviewed-by: Patrick Georgi Reviewed-by: ron minnich Tested-by: build bot (Jenkins) --- src/cpu/x86/mp_init.c | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 331f3b552a..c747207f7c 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1044,17 +1044,22 @@ static void fill_mp_state(struct mp_state *state, const struct mp_ops *ops) /* * Make sure there is enough room for the SMM descriptor */ - if (CONFIG(STM)) + if (CONFIG(STM)) { state->smm_save_state_size += sizeof(TXT_PROCESSOR_SMM_DESCRIPTOR); - /* Currently, the CPU SMM save state size is based on a simplistic - * algorithm. (align on 4K) - * note: In the future, this will need to handle newer x86 processors - * that require alignment of the save state on 32K boundaries. - */ - state->smm_save_state_size = - ALIGN_UP(state->smm_save_state_size, 0x1000); + /* Currently, the CPU SMM save state size is based on a simplistic + * algorithm. (align on 4K) + * note: In the future, this will need to handle newer x86 processors + * that require alignment of the save state on 32K boundaries. + * The alignment is done here because coreboot has a hard coded + * value of 0x400 for this value. + * Also, this alignment only works on CPUs less than 5 threads + */ + if (CONFIG(STM)) + state->smm_save_state_size = + ALIGN_UP(state->smm_save_state_size, 0x1000); + } /* * Default to smm_initiate_relocation() if trigger callback isn't From 2806ec971e11cccee86927ddde6ace3a34319cfb Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Feb 2020 10:51:46 -0600 Subject: [PATCH 089/151] nb/intel/haswell: Fix type definition of dev in PCI_FUNC(dev) The type of dev in the PCI_FUNC(dev) is incorrect. Fix it using PCI_DEV2DEVFN() macro. Tested on a T440P, and necessary on this board to enable the dGPU. Change-Id: I3fb0f677cc98800f355f6af7d3172be3e59ce5c2 Signed-off-by: Chris Morgan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38722 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/northbridge/intel/haswell/early_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index 666bda28f8..6aad4a381f 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -101,7 +101,7 @@ static void start_peg2_link_training(const pci_devfn_t dev) } pci_update_config32(dev, 0xc24, ~(1 << 16), 1 << 5); - printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(dev)); + printk(BIOS_DEBUG, "Started PEG1%d link training.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); /* * The PEG device is hidden while the MRC runs. This is because the @@ -110,8 +110,8 @@ static void start_peg2_link_training(const pci_devfn_t dev) * to these configurations. */ pci_update_config32(PCI_DEV(0, 0, 0), DEVEN, ~mask, 0); - peg_hidden[PCI_FUNC(dev)] = true; - printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(dev)); + peg_hidden[PCI_FUNC(PCI_DEV2DEVFN(dev))] = true; + printk(BIOS_DEBUG, "Temporarily hiding PEG1%d.\n", PCI_FUNC(PCI_DEV2DEVFN(dev))); } void haswell_unhide_peg(void) From b40c6009141e2c6a6f886584ea6d5b7e4fe69347 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 20 Jan 2020 18:21:13 +1100 Subject: [PATCH 090/151] mainboard/hatch: Fix puff DP output on cold boots Wait for HPD DP unless HDMI is plugged. Some Type-C monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Similar to that of b:72387533 however our DP&HDMI are beind a MST. See commit d182b63347c744c on how this was done for mainboard/fizz. BUG=b:147992492 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I19d40056e58f1737f87fd07d62b07a723a63d610 Signed-off-by: Edward O'Callaghan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38475 Tested-by: build bot (Jenkins) Reviewed-by: Daisuke Nojiri --- .../google/hatch/variants/puff/mainboard.c | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/mainboard/google/hatch/variants/puff/mainboard.c b/src/mainboard/google/hatch/variants/puff/mainboard.c index 9c2b5fb033..7354ce92cc 100644 --- a/src/mainboard/google/hatch/variants/puff/mainboard.c +++ b/src/mainboard/google/hatch/variants/puff/mainboard.c @@ -15,8 +15,50 @@ #include #include +#include #include #include +#include +#include + +#define GPIO_HDMI_HPD GPP_E13 +#define GPIO_DP_HPD GPP_E14 + +/* TODO: This can be moved to common directory */ +static void wait_for_hpd(gpio_t gpio, long timeout) +{ + struct stopwatch sw; + + printk(BIOS_INFO, "Waiting for HPD\n"); + stopwatch_init_msecs_expire(&sw, timeout); + while (!gpio_get(gpio)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "HPD not ready after %ldms. Abort.\n", timeout); + return; + } + mdelay(200); + } + printk(BIOS_INFO, "HPD ready after %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +void variant_ramstage_init(void) +{ + static const long display_timeout_ms = 3000; + + /* This is reconfigured back to whatever FSP-S expects by + gpio_configure_pads. */ + gpio_input(GPIO_HDMI_HPD); + gpio_input(GPIO_DP_HPD); + if (display_init_required() + && !gpio_get(GPIO_HDMI_HPD) + && !gpio_get(GPIO_DP_HPD)) { + /* This has to be done before FSP-S runs. */ + if (google_chromeec_wait_for_displayport(display_timeout_ms)) + wait_for_hpd(GPIO_DP_HPD, display_timeout_ms); + } +} /* * For type-C chargers, set PL2 to 90% of max power to account for From ec12bd011bda6c1364102b497fefbaf65c46880f Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Tue, 4 Feb 2020 17:36:49 +0800 Subject: [PATCH 091/151] security/vboot: relocate vb2ex_abort and vb2ex_printf Enabling an assertion in vb2_member_of() results in coreboot linking vb2ex_abort() and vb2ex_printf() in ramstage. Move these two functions from vboot_logic.c to vboot_lib.c, which is should be enabled in all stages if CONFIG_VBOOT_LIB is enabled. Note that CONFIG_VBOOT_LIB is implied by CONFIG_VBOOT. Relevant vboot_reference commit: CL:2037263. BUG=b:124141368, chromium:1005700 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ica0103c5684b3d50ba7dc1b4c39559cb192efa81 Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/38706 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/security/vboot/Makefile.inc | 6 ++++ src/security/vboot/vboot_lib.c | 29 +++++++++++++++++++ src/security/vboot/vboot_logic.c | 21 -------------- .../eltan/security/verified_boot/Makefile.inc | 2 +- 4 files changed, 36 insertions(+), 22 deletions(-) create mode 100644 src/security/vboot/vboot_lib.c diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index a700e0051a..2fe2d92900 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -16,6 +16,12 @@ ifeq ($(CONFIG_VBOOT_LIB),y) +bootblock-y += vboot_lib.c +verstage-y += vboot_lib.c +romstage-y += vboot_lib.c +ramstage-y += vboot_lib.c +postcar-y += vboot_lib.c + vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ $(patsubst $(src)/%.h,$(top)/$(src)/%.h,\ $(filter-out -I$(obj),$(1)))) diff --git a/src/security/vboot/vboot_lib.c b/src/security/vboot/vboot_lib.c new file mode 100644 index 0000000000..b2303c0295 --- /dev/null +++ b/src/security/vboot/vboot_lib.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include + +/* + * vboot callbacks implemented by coreboot -- necessary for making general API + * calls when CONFIG_VBOOT_LIB is enabled. For callbacks specific to verstage + * (CONFIG_VBOOT), please see vboot_logic.c. + */ + +void vb2ex_printf(const char *func, const char *fmt, ...) +{ + va_list args; + + if (func) + printk(BIOS_INFO, "VB2:%s() ", func); + + va_start(args, fmt); + vprintk(BIOS_INFO, fmt, args); + va_end(args); +} + +void vb2ex_abort(void) +{ + die("vboot has aborted execution; exit\n"); +} diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 1d17a17657..182128c547 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -17,8 +17,6 @@ #include #include #include -#include -#include #include #include #include @@ -37,20 +35,6 @@ /* exports */ -void vb2ex_printf(const char *func, const char *fmt, ...) -{ - va_list args; - - if (func) - printk(BIOS_INFO, "VB2:%s() ", func); - - va_start(args, fmt); - vprintk(BIOS_INFO, fmt, args); - va_end(args); - - return; -} - vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, enum vb2_resource_index index, uint32_t offset, @@ -83,11 +67,6 @@ vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, return VB2_SUCCESS; } -void vb2ex_abort(void) -{ - die("vboot has aborted execution; exit\n"); -} - /* No-op stubs that can be overridden by SoCs with hardware crypto support. */ __weak vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, uint32_t data_size) diff --git a/src/vendorcode/eltan/security/verified_boot/Makefile.inc b/src/vendorcode/eltan/security/verified_boot/Makefile.inc index 827535b963..2acad84367 100644 --- a/src/vendorcode/eltan/security/verified_boot/Makefile.inc +++ b/src/vendorcode/eltan/security/verified_boot/Makefile.inc @@ -17,7 +17,7 @@ ifneq ($(filter y,$(CONFIG_VENDORCODE_ELTAN_VBOOT) $(CONFIG_VENDORCODE_ELTAN_MBO CPPFLAGS_common += -I$(src)/security/vboot -bootblock-y += ../../../../security/vboot/vboot_logic.c +bootblock-y += ../../../../security/vboot/vboot_lib.c bootblock-y += vboot_check.c postcar-y += vboot_check.c romstage-y += vboot_check.c From 01bfa53f772a1a5cf7caa95abc62e35579022024 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 3 Feb 2020 15:59:07 +0100 Subject: [PATCH 092/151] util/docker/coreboot-sdk: Add packages required to build LinuxBoot Add golang and libelf-dev so LinuxBoot can be built from the coreboot-sdk docker container. BUG=N/A TEST=build Change-Id: I7a156fc24a6040d73467e06c16139bf298a29740 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38751 Tested-by: Martin Roth Reviewed-by: Martin Roth --- util/docker/coreboot-sdk/Dockerfile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index 2e8fe38ccc..7c87056a7b 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -35,10 +35,12 @@ RUN \ gcc \ git \ gnat \ + golang \ graphviz \ libcrypto++-dev \ libcurl4 \ libcurl4-openssl-dev \ + libelf-dev \ libfreetype6-dev \ libftdi-dev \ libftdi1-dev \ From bcd62f5737f5022b1bbe0041d4222575851b3cb9 Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Wed, 7 Aug 2019 14:26:32 -0700 Subject: [PATCH 093/151] trogdor: support mbn_version 6 with python build scripts Developer/Reviewer, be aware of this patch from Mistral: https://review.coreboot.org/c/coreboot/+/33425/18 Change-Id: I020d1e4d4f5c948948e1b39dd18af1d0e860c279 Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/coreboot/+/35506 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- util/qualcomm/createxbl.py | 49 ++++++++------ util/qualcomm/mbn_tools.py | 131 +++++++++++++++++++++++-------------- util/qualcomm/qgpt.py | 2 +- 3 files changed, 112 insertions(+), 70 deletions(-) diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py index 4a218544c0..861cec9110 100755 --- a/util/qualcomm/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -44,11 +44,13 @@ # # when who what, where, why # -------- --- ------------------------------------------------------ +# 05/21/19 rissha Added --mbn_version to add MBN header accordingly # 03/26/18 tv Added -e to enable extended MBNV5 support # 09/04/15 et Added -x and -d to embed xbl_sec ELF # 02/11/15 ck Fixed missing elf type check in ZI OOB feature # 11/04/14 ck Updated calls to mbn_tools functions -# 10/22/14 ck Added -z option to remove out of bounds ZI segments when converting from 64 to 32 +# 10/22/14 ck Added -z option to remove out of bounds ZI segments when +# converting from 64 to 32 # 10/10/14 ck Added -c option and logic to enable elf type swapping # 09/12/14 ck Added single file logic # 08/29/14 ck Added no_hash option @@ -119,6 +121,10 @@ def main(): help="Removes ZI segments that have addresses greater" + \ " than 32 bits when converting from a 64 to 32 bit ELF") + parser.add_option("--mbn_version", + action="store", type="int", dest="mbn_version", + help="Add mbn header in elf image. '3', '5' or '6'") + (options, args) = parser.parse_args() if not options.elf_inp_file1: @@ -206,11 +212,13 @@ def main(): else: zi_oob_enabled = True - if options.elf_inp_xbl_sec: - is_ext_mbn_v5 = True - else: - is_ext_mbn_v5 = False + header_version = 3 + if options.elf_inp_xbl_sec: + header_version = 5 + + if options.mbn_version: + header_version = options.mbn_version mbn_type = 'elf' header_format = 'reg' @@ -244,7 +252,7 @@ def main(): is_elf_xbl_sec_64_bit, is_out_elf_64_bit, zi_oob_enabled, - is_ext_mbn_v5) + header_version) # Hash the image if user did not explicitly say not to @@ -259,7 +267,8 @@ def main(): source_elf, target_hash, elf_out_file_name = target_phdr_elf, - secure_type = image_header_secflag) + secure_type = image_header_secflag, + header_version = header_version ) if rv: raise RuntimeError, "Failed to run pboot_gen_elf" @@ -269,8 +278,8 @@ def main(): target_hash, target_hash_hd, image_header_secflag, - is_ext_mbn_v5, - elf_file_name = source_elf) + elf_file_name = source_elf, + header_version = header_version) if rv: raise RuntimeError, "Failed to create image header for hash segment" @@ -305,7 +314,7 @@ def merge_elfs(env, is_elf_xbl_sec_64_bit, is_out_elf_64_bit, zi_oob_enabled, - is_ext_mbn_v5): + header_version): [elf_header1, phdr_table1] = \ mbn_tools.preprocess_elf_file(elf_in_file_name1) @@ -663,12 +672,12 @@ def merge_elfs(env, new_phdr.p_paddr = phys_virt_addr new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz - if is_ext_mbn_v5 == True: - new_phdr.p_flags = (0x5 | - (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << - mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); + if header_version >= 5: + new_phdr.p_flags = (0x5 | + (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << + mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); else: - new_phdr.p_flags = 0x5 + new_phdr.p_flags = 0x5 new_phdr.p_align = 0x1000 else: # Converting from 64 to 32 elf requires data size validation @@ -677,12 +686,12 @@ def merge_elfs(env, new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) new_phdr.p_type = 0x1 # new_phdr.p_offset = segment_offset - if is_ext_mbn_v5 == True: - new_phdr.p_flags = (0x5 | - (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << - mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); + if header_version >= 5: + new_phdr.p_flags = (0x5 | + (mbn_tools.MI_PBT_XBL_SEC_SEGMENT << + mbn_tools.MI_PBT_FLAG_SEGMENT_TYPE_SHIFT)); else: - new_phdr.p_flags = 0x5 + new_phdr.p_flags = 0x5 new_phdr.p_align = 0x1000 if phys_virt_addr > 0xFFFFFFFF: diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py index 12dc210cac..6008da5d82 100755 --- a/util/qualcomm/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -41,6 +41,7 @@ # # when who what, where, why # -------- --- --------------------------------------------------------- +# 05/21/18 rissha Added support for extended MBNV6 and Add support for hashing elf segments with SHA384 # 03/22/18 thiru Added support for extended MBNV5. # 06/06/13 yliong CR 497042: Signed and encrypted image is corrupted. MRC features. # 03/18/13 dhaval Add support for hashing elf segments with SHA256 and @@ -64,23 +65,21 @@ import hashlib #---------------------------------------------------------------------------- # GLOBAL VARIABLES BEGIN #---------------------------------------------------------------------------- -PAD_BYTE_1 = 255 # Padding byte 1s -PAD_BYTE_0 = 0 # Padding byte 0s -SHA256_SIGNATURE_SIZE = 256 # Support SHA256 -MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates -MI_BOOT_IMG_HDR_SIZE = 40 # sizeof(mi_boot_image_header_type) -MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) -BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements -SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements -FLASH_PARTI_VERSION = 3 # Flash Partition Version Number -MAX_PHDR_COUNT = 100 # Maximum allowable program headers -CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root -VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON -MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE -MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature +PAD_BYTE_1 = 255 # Padding byte 1s +PAD_BYTE_0 = 0 # Padding byte 0s +SHA256_SIGNATURE_SIZE = 256 # Support SHA256 +MAX_NUM_ROOT_CERTS = 4 # Maximum number of OEM root certificates +MI_BOOT_SBL_HDR_SIZE = 80 # sizeof(sbl_header) +BOOT_HEADER_LENGTH = 20 # Boot Header Number of Elements +SBL_HEADER_LENGTH = 20 # SBL Header Number of Elements +MAX_PHDR_COUNT = 100 # Maximum allowable program headers +CERT_CHAIN_ONEROOT_MAXSIZE = 6*1024 # Default Cert Chain Max Size for one root +VIRTUAL_BLOCK_SIZE = 131072 # Virtual block size for MCs insertion in SBL1 if ENABLE_VIRTUAL_BLK ON +MAGIC_COOKIE_LENGTH = 12 # Length of magic Cookie inserted per VIRTUAL_BLOCK_SIZE +MIN_IMAGE_SIZE_WITH_PAD = 256*1024 # Minimum image size for sbl1 Nand based OTA feature -SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image -SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image +SBL_AARCH64 = 0xF # Indicate that SBL is a Aarch64 image +SBL_AARCH32 = 0x0 # Indicate that SBL is a Aarch32 image # Magic numbers filled in for boot headers FLASH_CODE_WORD = 0x844BDCD1 @@ -150,7 +149,6 @@ values. MI_PBT_FLAGS_MASK = 0x0FF00000 # Helper defines to help parse ELF program headers -MI_PROG_BOOT_DIGEST_SIZE = 20 MI_PBT_FLAG_SEGMENT_TYPE_MASK = 0x07000000 MI_PBT_FLAG_SEGMENT_TYPE_SHIFT = 0x18 MI_PBT_FLAG_PAGE_MODE_MASK = 0x00100000 @@ -528,7 +526,7 @@ class SegmentInfo: class Boot_Hdr: def __init__(self, init_val): self.image_id = ImageType.NONE_IMG - self.flash_parti_ver = FLASH_PARTI_VERSION + self.flash_parti_ver = 3 self.image_src = init_val self.image_dest_ptr = init_val self.image_size = init_val @@ -573,6 +571,10 @@ class Boot_Hdr: self.reserved_2, self.reserved_3 ] + if self.flash_parti_ver >= 6: + values.insert(10, self.metadata_size_qti) + values.insert(11, self.metadata_size) + if self.image_dest_ptr >= 0x100000000: values[3] = 0xFFFFFFFF @@ -584,8 +586,12 @@ class Boot_Hdr: # Write 10 entries(40B) or 20 entries(80B) of boot header if write_full_hdr is False: - s = struct.Struct('I'* 10) - values = values[:10] + if self.flash_parti_ver >= 6: + s = struct.Struct('I'* 12) + values = values[:12] + else: + s = struct.Struct('I'* 10) + values = values[:10] else: s = struct.Struct('I' * self.getLength()) @@ -904,7 +910,6 @@ def image_header(env, gen_dict, code_file_name, output_file_name, secure_type, - is_ext_mbn_v5, header_format = 'reg', requires_preamble = False, preamble_file_name = None, @@ -912,7 +917,8 @@ def image_header(env, gen_dict, write_full_hdr = False, in_code_size = None, cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, - num_of_pages = None): + num_of_pages = None, + header_version = None): # Preliminary checks if (requires_preamble is True) and (preamble_file_name is None): @@ -945,9 +951,12 @@ def image_header(env, gen_dict, cert_chain_size = 0 image_size = code_size + if header_version: + assert header_version in [3, 5, 6], 'Not a valid MBN header version' + # For ELF or hashed images, image destination will be determined from an ELF input file if gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf': - image_dest = get_hash_address(elf_file_name) + MI_BOOT_IMG_HDR_SIZE + image_dest = get_hash_address(elf_file_name) + (header_size(header_version)) elif gen_dict['IMAGE_KEY_MBN_TYPE'] == 'bin': image_dest = gen_dict['IMAGE_KEY_IMAGE_DEST'] image_source = gen_dict['IMAGE_KEY_IMAGE_SOURCE'] @@ -991,12 +1000,15 @@ def image_header(env, gen_dict, boot_header.sig_size = signature_size boot_header.cert_chain_ptr = image_dest + code_size + signature_size boot_header.cert_chain_size = cert_chain_size + boot_header.flash_parti_ver = header_version # version - if is_ext_mbn_v5 == True: - # If platform image integrity check is enabled - boot_header.flash_parti_ver = 5 # version - boot_header.image_src = 0 # sig_size_qc - boot_header.image_dest_ptr = 0 # cert_chain_size_qc + if header_version >= 5: + boot_header.image_src = 0 # sig_size_qc + boot_header.image_dest_ptr = 0 # cert_chain_size_qc + + if header_version >= 6: + boot_header.metadata_size_qti = 0 # qti_metadata size + boot_header.metadata_size = 0 # oem_metadata size # If preamble is required, output the preamble file and update the boot_header if requires_preamble is True: @@ -1021,12 +1033,22 @@ def pboot_gen_elf(env, elf_in_file_name, last_phys_addr = None, append_xml_hdr = False, is_sha256_algo = True, - cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE): - global MI_PROG_BOOT_DIGEST_SIZE - if (is_sha256_algo is True): - MI_PROG_BOOT_DIGEST_SIZE = 32 + cert_chain_size_in = CERT_CHAIN_ONEROOT_MAXSIZE, + header_version = None): + sha_algo = 'SHA1' + if is_sha256_algo: + sha_algo = 'SHA256' + + if header_version >= 6: + sha_algo = 'SHA384' + image_header_size = header_size(header_version) + + if (sha_algo == 'SHA384'): + mi_prog_boot_digest_size = 48 + elif sha_algo == 'SHA256': + mi_prog_boot_digest_size = 32 else: - MI_PROG_BOOT_DIGEST_SIZE = 20 + mi_prog_boot_digest_size = 20 # Open Files elf_in_fp = OPEN(elf_in_file_name, "rb") @@ -1052,7 +1074,7 @@ def pboot_gen_elf(env, elf_in_file_name, elf_header_size = ELF32_HDR_SIZE is_elf64 = False - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + hash = '\0' * mi_prog_boot_digest_size phdr_start = 0 bytes_to_pad = 0 hash_seg_end = 0 @@ -1071,12 +1093,12 @@ def pboot_gen_elf(env, elf_in_file_name, elf_header.e_phnum += 2 # Create an empty hash entry for PHDR_TYPE - hash_out_fp.write('\0' * MI_PROG_BOOT_DIGEST_SIZE) - hashtable_size += MI_PROG_BOOT_DIGEST_SIZE + hash_out_fp.write('\0' * mi_prog_boot_digest_size) + hashtable_size += mi_prog_boot_digest_size # Create an empty hash entry for the hash segment itself - hash_out_fp.write('\0' * MI_PROG_BOOT_DIGEST_SIZE) - hashtable_size += MI_PROG_BOOT_DIGEST_SIZE + hash_out_fp.write('\0' * mi_prog_boot_digest_size) + hashtable_size += mi_prog_boot_digest_size # Begin hash table generation for i in range(num_phdrs): @@ -1110,14 +1132,14 @@ def pboot_gen_elf(env, elf_in_file_name, fbuf = elf_in_fp.read(hash_size) if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: - hash = generate_hash(fbuf, is_sha256_algo) + hash = generate_hash(fbuf, sha_algo) else: - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + hash = '\0' * mi_prog_boot_digest_size # Write hash to file hash_out_fp.write(hash) - hashtable_size += MI_PROG_BOOT_DIGEST_SIZE + hashtable_size += mi_prog_boot_digest_size seg_offset += ELF_BLOCK_ALIGN # Copy the hash entry for all that are PAGED segments and those that are not the PHDR type. This is for @@ -1129,14 +1151,14 @@ def pboot_gen_elf(env, elf_in_file_name, file_buff = elf_in_fp.read(data_len) if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0): - hash = generate_hash(file_buff, is_sha256_algo) + hash = generate_hash(file_buff, sha_algo) else: - hash = '\0' * MI_PROG_BOOT_DIGEST_SIZE + hash = '\0' * mi_prog_boot_digest_size # Write hash to file hash_out_fp.write(hash) - hashtable_size += MI_PROG_BOOT_DIGEST_SIZE + hashtable_size += mi_prog_boot_digest_size # End hash table generation # Generate the rest of the ELF output file if specified @@ -1151,7 +1173,7 @@ def pboot_gen_elf(env, elf_in_file_name, # Initialize the hash table program header [hash_Phdr, pad_hash_segment, hash_tbl_end_addr, hash_tbl_offset] = \ - initialize_hash_phdr(elf_in_file_name, hashtable_size, MI_BOOT_IMG_HDR_SIZE, ELF_BLOCK_ALIGN, is_elf64) + initialize_hash_phdr(elf_in_file_name, hashtable_size, image_header_size, ELF_BLOCK_ALIGN, is_elf64) # Check if hash segment max size parameter was passed if (hash_seg_max_size is not None): @@ -1252,7 +1274,7 @@ def pboot_gen_elf(env, elf_in_file_name, # Read the program header and compute hash proghdr_buff = elf_out_fp.read(elf_header.e_phnum * phdr_size) - hash = generate_hash(elfhdr_buff + proghdr_buff, is_sha256_algo) + hash = generate_hash(elfhdr_buff + proghdr_buff, sha_algo) # Write hash to file as first hash table entry hash_out_fp.seek(0) @@ -1592,7 +1614,7 @@ def generate_code_hash(env, elf_in_file_name): page = page + elf_in_fp.read(bytes_in_page - len(page)) if (len(page) < DP_PAGE_SIZE): page = page + (struct.pack('b', 0) * (DP_PAGE_SIZE - len(page))) - hashes = hashes + [generate_hash(page, True)] + hashes = hashes + [generate_hash(page, 'SHA256')] bytes_left -= bytes_in_page # And write them to the hash segment @@ -2101,9 +2123,20 @@ def file_copy_offset(in_fp, in_off, out_fp, out_off, num_bytes): #---------------------------------------------------------------------------- # sha1/sha256 hash routine wrapper #---------------------------------------------------------------------------- -def generate_hash(in_buf, is_sha256_algo): +def header_size(header_version): + if header_version >= 6: + return 48 + else: + return 40 + +#---------------------------------------------------------------------------- +# sha1/sha256 hash routine wrapper +#---------------------------------------------------------------------------- +def generate_hash(in_buf, sha_algo): # Initialize a SHA1 object from the Python hash library - if (is_sha256_algo is True): + if sha_algo == 'SHA384': + m = hashlib.sha384() + elif sha_algo == 'SHA256': m = hashlib.sha256() else: m = hashlib.sha1() diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py index 476ca5ca76..0b096b9cf5 100755 --- a/util/qualcomm/qgpt.py +++ b/util/qualcomm/qgpt.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python2 #============================================================================ # #/** @file qgpt.py From 91dc1e74a52ec33dc7f5c33dca73f02c5fe54cf0 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Thu, 19 Dec 2019 16:41:02 +0530 Subject: [PATCH 094/151] sc7180: clock: Fix QUP DFSR configuration for perf levels Update the QUP DFSR cmd to clear the SW control and also update the perf registers when M is set. While at it also update the d_2 values. Tested: validated DFSR clock configuration and M/N/D values. Change-Id: I6bba1c6f99810963aaa607885ef400c523c0e905 Signed-off-by: Taniya Das Reviewed-on: https://review.coreboot.org/c/coreboot/+/38389 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- src/soc/qualcomm/sc7180/clock.c | 14 ++++++++------ src/soc/qualcomm/sc7180/include/soc/clock.h | 1 + 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/soc/qualcomm/sc7180/clock.c b/src/soc/qualcomm/sc7180/clock.c index b447a54487..213c37ff3c 100644 --- a/src/soc/qualcomm/sc7180/clock.c +++ b/src/soc/qualcomm/sc7180/clock.c @@ -72,7 +72,7 @@ struct clock_config qup_wrap_cfg[] = { .div = DIV(1), .m = 8, .n = 75, - .d_2 = 150, + .d_2 = 75, }, { .hz = 48 * MHz, @@ -80,7 +80,7 @@ struct clock_config qup_wrap_cfg[] = { .div = DIV(1), .m = 4, .n = 25, - .d_2 = 50, + .d_2 = 25, }, { .hz = 64 * MHz, @@ -88,7 +88,7 @@ struct clock_config qup_wrap_cfg[] = { .div = DIV(1), .m = 16, .n = 75, - .d_2 = 150, + .d_2 = 75, }, { .hz = 96 * MHz, @@ -96,7 +96,7 @@ struct clock_config qup_wrap_cfg[] = { .div = DIV(1), .m = 8, .n = 25, - .d_2 = 50, + .d_2 = 25, }, { .hz = 100 * MHz, @@ -236,7 +236,9 @@ void clock_configure_dfsr(int qup) struct sc7180_qupv3_clock *qup_clk = qup < QUP_WRAP1_S0 ? &gcc->qup_wrap0_s[s] : &gcc->qup_wrap1_s[s]; - setbits32(&qup_clk->dfsr_clk.cmd_dfsr, BIT(CLK_CTL_CMD_DFSR_SHFT)); + clrsetbits32(&qup_clk->dfsr_clk.cmd_dfsr, + BIT(CLK_CTL_CMD_RCG_SW_CTL_SHFT), + BIT(CLK_CTL_CMD_DFSR_SHFT)); for (idx = 0; idx < ARRAY_SIZE(qup_wrap_cfg); idx++) { reg_val = (qup_wrap_cfg[idx].src << CLK_CTL_CFG_SRC_SEL_SHFT) | @@ -247,7 +249,7 @@ void clock_configure_dfsr(int qup) if (qup_wrap_cfg[idx].m == 0) continue; - setbits32(&qup_clk->dfsr_clk.cmd_dfsr, + setbits32(&qup_clk->dfsr_clk.perf_dfsr[idx], RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT); reg_val = qup_wrap_cfg[idx].m & CLK_CTL_RCG_MND_BMSK; diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index 2e44b60623..383e6d7be2 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -187,6 +187,7 @@ enum clk_ctl_bcr { enum clk_ctl_dfsr { CLK_CTL_CMD_DFSR_BMSK = 0x1, CLK_CTL_CMD_DFSR_SHFT = 0, + CLK_CTL_CMD_RCG_SW_CTL_SHFT = 15, }; enum clk_qup { From 466ca2c1adbf2fc97dd559a3b69fcf0c7fe5d472 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 22 Oct 2019 02:02:24 +0000 Subject: [PATCH 095/151] Add configurable ramstage support for minimal PCI scanning This CL has changes that allow us to enable a configurable ramstage, and one change that allows us to minimize PCI scanning. Minimal scanning is a frequently requested feature. To enable it, we add two new variables to src/Kconfig CONFIGURABLE_RAMSTAGE is the overall variable controlling other options for minimizing the ramstage. MINIMAL_PCI_SCANNING is how we indicate we wish to enable minimal PCI scanning. Some devices must be scanned in all cases, such as 0:0.0. To indicate which devices we must scan, we add a new mandatory keyword to sconfig It is used in place of on, off, or hidden, and indicates a device is enabled and mandatory. Mandatory devices are always scanned. When MINIMAL_PCI_SCANNING is enabled, ONLY mandatory devices are scanned. We further add support in src/device/pci_device.c to manage both MINIMAL_PCI_SCANNING and mandatory devices. Finally, to show how this works in practice, we add mandatory keywords to 3 devices on the qemu-q35. TEST= 1. This is tested and working on the qemu-q35 target. 2. On CML-Hatch Before CL: Total Boot time: ~685ms After CL: Total Boot time: ~615ms Change-Id: I2073d9f8e9297c2b02530821ebb634ea2a5c758e Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/c/coreboot/+/36221 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- src/Kconfig | 15 + src/device/pci_device.c | 6 + src/include/device/device.h | 5 +- .../emulation/qemu-q35/devicetree.cb | 4 +- util/sconfig/lex.yy.c_shipped | 493 +++++++++--------- util/sconfig/main.c | 2 + util/sconfig/sconfig.h | 2 + util/sconfig/sconfig.l | 3 +- util/sconfig/sconfig.tab.c_shipped | 141 ++--- util/sconfig/sconfig.tab.h_shipped | 67 +-- util/sconfig/sconfig.y | 4 +- 11 files changed, 387 insertions(+), 355 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f538a1cc18..3742c04675 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -354,6 +354,21 @@ config RAMPAYLOAD Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI). +config CONFIGURABLE_RAMSTAGE + bool "Enable a configurable ramstage." + default y if ARCH_X86 + help + A configurable ramstage allows you to select which parts of the ramstage + to run. Currently, we can only select a minimal PCI scanning step. + The minimal PCI scanning will only check those parts that are enabled + in the devicetree.cb. By convention none of those devices should be bridges. + +config MINIMAL_PCI_SCANNING + bool "Enable minimal PCI scanning" + depends on CONFIGURABLE_RAMSTAGE + help + If this option is enabled, coreboot will scan only devices + marked as mandatory in devicetree.cb endmenu menu "Mainboard" diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 47c0e9f2d2..b1e88a6896 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1195,6 +1195,12 @@ void pci_scan_bus(struct bus *bus, unsigned int min_devfn, * non-existence and single function devices. */ for (devfn = min_devfn; devfn <= max_devfn; devfn++) { + if (CONFIG(MINIMAL_PCI_SCANNING)) { + dev = pcidev_path_behind(bus, devfn); + if (!dev || !dev->mandatory) + continue; + } + /* First thing setup the device structure. */ dev = pci_scan_get_dev(bus, devfn); diff --git a/src/include/device/device.h b/src/include/device/device.h index c3a1106023..333ac5d404 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -119,7 +119,10 @@ struct device { unsigned int initialized : 1; /* 1 if we have initialized the device */ unsigned int on_mainboard : 1; unsigned int disable_pcie_aspm : 1; - unsigned int hidden : 1; /* set if we should hide from UI */ + /* set if we should hide from UI */ + unsigned int hidden : 1; + /* set if this device is used even in minimum PCI cases */ + unsigned int mandatory : 1; u8 command; uint16_t hotplug_buses; /* Number of hotplug buses to allocate */ diff --git a/src/mainboard/emulation/qemu-q35/devicetree.cb b/src/mainboard/emulation/qemu-q35/devicetree.cb index 671a2d631d..c032606e67 100644 --- a/src/mainboard/emulation/qemu-q35/devicetree.cb +++ b/src/mainboard/emulation/qemu-q35/devicetree.cb @@ -5,10 +5,10 @@ chip mainboard/emulation/qemu-q35 end end device domain 0 on - device pci 0.0 on end # northbridge (q35) + device pci 0.0 mandatory end # northbridge (q35) chip southbridge/intel/i82801ix # present unconditionally - device pci 1f.0 on end # LPC + device pci 1f.0 mandatory end # LPC device pci 1f.2 on end # SATA device pci 1f.3 on end # SMBus diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 14ffeff9a2..63297732fa 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -6,7 +6,7 @@ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 #define YY_FLEX_MINOR_VERSION 6 -#define YY_FLEX_SUBMINOR_VERSION 1 +#define YY_FLEX_SUBMINOR_VERSION 4 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif @@ -81,10 +81,16 @@ typedef unsigned int flex_uint32_t; #define UINT32_MAX (4294967295U) #endif +#ifndef SIZE_MAX +#define SIZE_MAX (~(size_t)0) +#endif + #endif /* ! C99 */ #endif /* ! FLEXINT_H */ +/* begin standard C++ headers. */ + /* TODO: this is always defined, so inline it */ #define yyconst const @@ -97,32 +103,26 @@ typedef unsigned int flex_uint32_t; /* Returned upon end-of-file. */ #define YY_NULL 0 -/* Promotes a possibly negative, possibly signed char to an unsigned - * integer for use as an array index. If the signed char is negative, - * we want to instead treat it as an 8-bit unsigned char, hence the - * double cast. +/* Promotes a possibly negative, possibly signed char to an + * integer in range [0..255] for use as an array index. */ -#define YY_SC_TO_UI(c) ((unsigned int) (unsigned char) c) +#define YY_SC_TO_UI(c) ((YY_CHAR) (c)) /* Enter a start condition. This macro really ought to take a parameter, * but we do it the disgusting crufty way forced on us by the ()-less * definition of BEGIN. */ #define BEGIN (yy_start) = 1 + 2 * - /* Translate the current start state into a value that can be later handed * to BEGIN to return to the state. The YYSTATE alias is for lex * compatibility. */ #define YY_START (((yy_start) - 1) / 2) #define YYSTATE YY_START - /* Action number for EOF rule of a given start state. */ #define YY_STATE_EOF(state) (YY_END_OF_BUFFER + state + 1) - /* Special action meaning "start processing a new file". */ -#define YY_NEW_FILE yyrestart(yyin ) - +#define YY_NEW_FILE yyrestart( yyin ) #define YY_END_OF_BUFFER_CHAR 0 /* Size of default input buffer. */ @@ -159,16 +159,14 @@ extern FILE *yyin, *yyout; #define EOB_ACT_CONTINUE_SCAN 0 #define EOB_ACT_END_OF_FILE 1 #define EOB_ACT_LAST_MATCH 2 - #define YY_LESS_LINENO(n) #define YY_LINENO_REWIND_TO(ptr) - /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ do \ { \ /* Undo effects of setting up yytext. */ \ - yy_size_t yyless_macro_arg = (n); \ + int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ *yy_cp = (yy_hold_char); \ YY_RESTORE_YY_MORE_OFFSET \ @@ -176,7 +174,6 @@ extern FILE *yyin, *yyout; YY_DO_BEFORE_ACTION; /* set up yytext again */ \ } \ while ( 0 ) - #define unput(c) yyunput( c, (yytext_ptr) ) #ifndef YY_STRUCT_YY_BUFFER_STATE @@ -258,7 +255,6 @@ static YY_BUFFER_STATE * yy_buffer_stack = NULL; /**< Stack as an array. */ #define YY_CURRENT_BUFFER ( (yy_buffer_stack) \ ? (yy_buffer_stack)[(yy_buffer_stack_top)] \ : NULL) - /* Same as previous macro, but useful when we know that the buffer stack is not * NULL or when we need an lvalue. For internal use only. */ @@ -279,62 +275,56 @@ static int yy_start = 0; /* start state number */ */ static int yy_did_buffer_switch_on_eof; -void yyrestart (FILE *input_file ); -void yy_switch_to_buffer (YY_BUFFER_STATE new_buffer ); -YY_BUFFER_STATE yy_create_buffer (FILE *file,int size ); -void yy_delete_buffer (YY_BUFFER_STATE b ); -void yy_flush_buffer (YY_BUFFER_STATE b ); -void yypush_buffer_state (YY_BUFFER_STATE new_buffer ); -void yypop_buffer_state (void ); +void yyrestart ( FILE *input_file ); +void yy_switch_to_buffer ( YY_BUFFER_STATE new_buffer ); +YY_BUFFER_STATE yy_create_buffer ( FILE *file, int size ); +void yy_delete_buffer ( YY_BUFFER_STATE b ); +void yy_flush_buffer ( YY_BUFFER_STATE b ); +void yypush_buffer_state ( YY_BUFFER_STATE new_buffer ); +void yypop_buffer_state ( void ); -static void yyensure_buffer_stack (void ); -static void yy_load_buffer_state (void ); -static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file ); +static void yyensure_buffer_stack ( void ); +static void yy_load_buffer_state ( void ); +static void yy_init_buffer ( YY_BUFFER_STATE b, FILE *file ); +#define YY_FLUSH_BUFFER yy_flush_buffer( YY_CURRENT_BUFFER ) -#define YY_FLUSH_BUFFER yy_flush_buffer(YY_CURRENT_BUFFER ) +YY_BUFFER_STATE yy_scan_buffer ( char *base, yy_size_t size ); +YY_BUFFER_STATE yy_scan_string ( const char *yy_str ); +YY_BUFFER_STATE yy_scan_bytes ( const char *bytes, int len ); -YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size ); -YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str ); -YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len ); - -void *yyalloc (yy_size_t ); -void *yyrealloc (void *,yy_size_t ); -void yyfree (void * ); +void *yyalloc ( yy_size_t ); +void *yyrealloc ( void *, yy_size_t ); +void yyfree ( void * ); #define yy_new_buffer yy_create_buffer - #define yy_set_interactive(is_interactive) \ { \ if ( ! YY_CURRENT_BUFFER ){ \ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ - yy_create_buffer(yyin,YY_BUF_SIZE ); \ + yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_is_interactive = is_interactive; \ } - #define yy_set_bol(at_bol) \ { \ if ( ! YY_CURRENT_BUFFER ){\ yyensure_buffer_stack (); \ YY_CURRENT_BUFFER_LVALUE = \ - yy_create_buffer(yyin,YY_BUF_SIZE ); \ + yy_create_buffer( yyin, YY_BUF_SIZE ); \ } \ YY_CURRENT_BUFFER_LVALUE->yy_at_bol = at_bol; \ } - #define YY_AT_BOL() (YY_CURRENT_BUFFER_LVALUE->yy_at_bol) /* Begin user sect3 */ - -typedef unsigned char YY_CHAR; +typedef flex_uint8_t YY_CHAR; FILE *yyin = NULL, *yyout = NULL; typedef int yy_state_type; extern int yylineno; - int yylineno = 1; extern char *yytext; @@ -343,10 +333,10 @@ extern char *yytext; #endif #define yytext_ptr yytext -static yy_state_type yy_get_previous_state (void ); -static yy_state_type yy_try_NUL_trans (yy_state_type current_state ); -static int yy_get_next_buffer (void ); -static void yynoreturn yy_fatal_error (yyconst char* msg ); +static yy_state_type yy_get_previous_state ( void ); +static yy_state_type yy_try_NUL_trans ( yy_state_type current_state ); +static int yy_get_next_buffer ( void ); +static void yynoreturn yy_fatal_error ( const char* msg ); /* Done after the current pattern has been matched and before the * corresponding action - sets up yytext. @@ -357,9 +347,8 @@ static void yynoreturn yy_fatal_error (yyconst char* msg ); (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; - -#define YY_NUM_RULES 38 -#define YY_END_OF_BUFFER 39 +#define YY_NUM_RULES 39 +#define YY_END_OF_BUFFER 40 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -367,28 +356,29 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static yyconst flex_int16_t yy_accept[160] = +static const flex_int16_t yy_accept[168] = { 0, - 0, 0, 39, 37, 1, 3, 37, 37, 37, 32, - 32, 30, 33, 37, 33, 33, 33, 37, 37, 37, - 37, 37, 37, 37, 37, 37, 37, 37, 1, 3, - 37, 0, 37, 37, 0, 2, 32, 33, 37, 37, - 37, 37, 33, 37, 37, 37, 37, 37, 37, 37, - 24, 37, 37, 37, 37, 7, 37, 37, 37, 37, - 37, 37, 37, 36, 36, 37, 0, 31, 37, 37, - 16, 37, 37, 23, 28, 37, 37, 13, 37, 37, - 22, 37, 37, 8, 10, 12, 37, 37, 20, 37, - 21, 37, 0, 34, 4, 37, 37, 37, 37, 37, + 0, 0, 40, 38, 1, 3, 38, 38, 38, 33, + 33, 31, 34, 38, 34, 34, 34, 38, 38, 38, + 38, 38, 38, 38, 38, 38, 38, 38, 1, 3, + 38, 0, 38, 38, 0, 2, 33, 34, 38, 38, + 38, 38, 34, 38, 38, 38, 38, 38, 38, 38, + 25, 38, 38, 38, 38, 38, 7, 38, 38, 38, + 38, 38, 38, 38, 37, 37, 38, 0, 32, 38, + 38, 17, 38, 38, 24, 29, 38, 38, 14, 38, + 38, 23, 38, 38, 38, 8, 11, 13, 38, 38, + 21, 38, 22, 38, 0, 35, 4, 38, 38, 38, - 37, 37, 37, 19, 37, 37, 37, 35, 35, 37, - 37, 37, 37, 37, 37, 37, 14, 37, 37, 37, - 37, 5, 17, 37, 9, 37, 11, 37, 37, 37, - 37, 18, 26, 37, 37, 37, 37, 37, 37, 6, - 37, 37, 37, 37, 37, 37, 37, 25, 37, 37, - 15, 37, 27, 37, 37, 37, 37, 29, 0 + 38, 38, 38, 38, 38, 38, 20, 38, 38, 38, + 36, 36, 38, 38, 38, 38, 38, 38, 38, 15, + 38, 38, 38, 38, 38, 5, 18, 38, 9, 38, + 12, 38, 38, 38, 38, 38, 19, 27, 38, 38, + 38, 38, 38, 38, 38, 38, 6, 38, 38, 38, + 38, 10, 38, 38, 38, 26, 38, 38, 16, 38, + 28, 38, 38, 38, 38, 30, 0 } ; -static yyconst YY_CHAR yy_ec[256] = +static const YY_CHAR yy_ec[256] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 3, 1, 1, 4, 1, 1, 1, 1, 1, 1, 1, @@ -420,7 +410,7 @@ static yyconst YY_CHAR yy_ec[256] = 1, 1, 1, 1, 1 } ; -static yyconst YY_CHAR yy_meta[39] = +static const YY_CHAR yy_meta[39] = { 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -428,114 +418,118 @@ static yyconst YY_CHAR yy_meta[39] = 1, 1, 1, 1, 1, 1, 1, 1 } ; -static yyconst flex_uint16_t yy_base[167] = +static const flex_int16_t yy_base[175] = { 0, - 0, 0, 227, 0, 224, 228, 222, 37, 41, 38, - 187, 0, 44, 209, 54, 78, 60, 201, 196, 45, - 203, 192, 42, 47, 197, 62, 184, 0, 214, 228, - 77, 210, 88, 69, 211, 228, 0, 87, 104, 198, - 187, 176, 93, 183, 178, 188, 179, 186, 186, 180, - 186, 171, 171, 175, 177, 0, 173, 167, 173, 177, - 169, 175, 174, 0, 228, 101, 186, 0, 179, 159, - 172, 162, 169, 0, 0, 164, 164, 0, 162, 152, - 0, 156, 151, 0, 0, 0, 154, 153, 0, 144, - 0, 171, 170, 0, 0, 155, 154, 147, 139, 149, + 0, 0, 235, 0, 232, 236, 230, 37, 41, 38, + 195, 0, 44, 217, 54, 78, 60, 209, 204, 45, + 211, 48, 42, 52, 206, 62, 193, 0, 223, 236, + 88, 219, 93, 79, 220, 236, 0, 93, 104, 207, + 196, 185, 96, 192, 187, 197, 188, 195, 195, 189, + 195, 180, 180, 181, 183, 185, 0, 181, 175, 181, + 185, 177, 183, 182, 0, 236, 115, 194, 0, 187, + 167, 180, 170, 177, 0, 0, 172, 172, 0, 170, + 160, 0, 164, 168, 158, 0, 0, 0, 161, 160, + 0, 151, 0, 178, 177, 0, 0, 162, 161, 154, - 137, 143, 148, 0, 133, 136, 126, 0, 228, 137, - 141, 133, 135, 131, 133, 138, 0, 122, 122, 121, - 118, 0, 0, 133, 0, 117, 134, 128, 132, 113, - 113, 0, 0, 120, 112, 110, 121, 94, 95, 0, - 94, 92, 97, 86, 85, 84, 76, 0, 71, 78, - 0, 67, 0, 61, 55, 32, 29, 0, 228, 40, - 129, 131, 133, 135, 137, 139 + 146, 156, 144, 150, 155, 156, 0, 139, 142, 132, + 0, 236, 143, 147, 139, 141, 137, 139, 144, 0, + 128, 127, 127, 126, 123, 0, 0, 138, 0, 122, + 139, 125, 132, 136, 117, 117, 0, 0, 124, 116, + 115, 113, 124, 97, 98, 91, 0, 102, 100, 98, + 83, 0, 80, 83, 74, 0, 60, 63, 0, 63, + 0, 56, 51, 33, 29, 0, 236, 40, 132, 134, + 136, 138, 140, 142 } ; -static yyconst flex_int16_t yy_def[167] = +static const flex_int16_t yy_def[175] = { 0, - 159, 1, 159, 160, 159, 159, 160, 161, 162, 160, - 10, 160, 10, 160, 10, 10, 10, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 159, 159, - 161, 163, 164, 162, 165, 159, 10, 10, 10, 160, - 160, 160, 10, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 159, 164, 166, 39, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 159, 160, 160, 160, 160, 160, 160, 160, + 167, 1, 167, 168, 167, 167, 168, 169, 170, 168, + 10, 168, 10, 168, 10, 10, 10, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 167, 167, + 169, 171, 172, 170, 173, 167, 10, 10, 10, 168, + 168, 168, 10, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 167, 172, 174, 39, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 167, 168, 168, 168, 168, 168, - 160, 160, 160, 160, 160, 160, 160, 160, 159, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 160, 160, - 160, 160, 160, 160, 160, 160, 160, 160, 0, 159, - 159, 159, 159, 159, 159, 159 + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 167, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 168, 168, 168, 168, + 168, 168, 168, 168, 168, 168, 0, 167, 167, 167, + 167, 167, 167, 167 } ; -static yyconst flex_uint16_t yy_nxt[267] = +static const flex_int16_t yy_nxt[275] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 158, 38, 38, + 28, 33, 35, 36, 37, 37, 37, 166, 38, 38, 38, 38, 38, 49, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 55, 157, 57, 38, 38, 38, 56, - 35, 36, 50, 51, 58, 156, 52, 41, 32, 32, - 155, 64, 154, 42, 38, 38, 38, 46, 60, 67, - 67, 61, 28, 38, 38, 38, 62, 153, 43, 38, + 38, 38, 38, 56, 54, 165, 38, 38, 38, 57, + 58, 164, 50, 51, 55, 163, 52, 41, 162, 59, + 35, 36, 161, 42, 38, 38, 38, 46, 61, 32, + 32, 62, 65, 160, 68, 68, 63, 28, 43, 38, - 38, 38, 67, 67, 152, 92, 44, 151, 150, 45, - 68, 68, 68, 149, 68, 68, 148, 147, 146, 145, - 68, 68, 68, 68, 68, 68, 144, 143, 72, 31, - 31, 34, 34, 32, 32, 66, 66, 35, 35, 67, - 67, 142, 141, 140, 139, 138, 137, 136, 135, 134, + 38, 38, 38, 38, 38, 159, 44, 158, 157, 45, + 69, 69, 69, 156, 69, 69, 68, 68, 155, 94, + 69, 69, 69, 69, 69, 69, 154, 153, 152, 151, + 150, 73, 31, 31, 34, 34, 32, 32, 67, 67, + 35, 35, 68, 68, 149, 148, 147, 146, 145, 144, + 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, 131, 130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, 111, 110, 109, 108, 107, 106, 105, 104, - 103, 102, 101, 100, 99, 98, 97, 96, 95, 94, - 93, 91, 90, 89, 88, 87, 86, 85, 84, 83, + 103, 102, 101, 100, 99, 98, 97, 96, 95, 93, - 82, 81, 80, 79, 78, 77, 76, 75, 74, 73, - 71, 70, 69, 36, 65, 29, 63, 59, 54, 53, - 48, 47, 40, 39, 30, 29, 159, 3, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159 + 92, 91, 90, 89, 88, 87, 86, 85, 84, 83, + 82, 81, 80, 79, 78, 77, 76, 75, 74, 72, + 71, 70, 36, 66, 29, 64, 60, 53, 48, 47, + 40, 39, 30, 29, 167, 3, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167 } ; -static yyconst flex_int16_t yy_chk[267] = +static const flex_int16_t yy_chk[275] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 160, 8, 9, 9, 10, 10, 10, 157, 10, 10, + 168, 8, 9, 9, 10, 10, 10, 165, 10, 10, 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 23, 156, 24, 17, 17, 17, 23, - 34, 34, 20, 20, 24, 155, 20, 15, 31, 31, - 154, 31, 152, 15, 16, 16, 16, 17, 26, 33, - 33, 26, 33, 38, 38, 38, 26, 150, 16, 43, + 15, 15, 15, 23, 22, 164, 17, 17, 17, 23, + 24, 163, 20, 20, 22, 162, 20, 15, 160, 24, + 34, 34, 158, 15, 16, 16, 16, 17, 26, 31, + 31, 26, 31, 157, 33, 33, 26, 33, 16, 38, - 43, 43, 66, 66, 149, 66, 16, 147, 146, 16, - 39, 39, 39, 145, 39, 39, 144, 143, 142, 141, - 39, 39, 39, 39, 39, 39, 139, 138, 43, 161, - 161, 162, 162, 163, 163, 164, 164, 165, 165, 166, - 166, 137, 136, 135, 134, 131, 130, 129, 128, 127, - 126, 124, 121, 120, 119, 118, 116, 115, 114, 113, - 112, 111, 110, 107, 106, 105, 103, 102, 101, 100, - 99, 98, 97, 96, 93, 92, 90, 88, 87, 83, - 82, 80, 79, 77, 76, 73, 72, 71, 70, 69, - 67, 63, 62, 61, 60, 59, 58, 57, 55, 54, + 38, 38, 43, 43, 43, 155, 16, 154, 153, 16, + 39, 39, 39, 151, 39, 39, 67, 67, 150, 67, + 39, 39, 39, 39, 39, 39, 149, 148, 146, 145, + 144, 43, 169, 169, 170, 170, 171, 171, 172, 172, + 173, 173, 174, 174, 143, 142, 141, 140, 139, 136, + 135, 134, 133, 132, 131, 130, 128, 125, 124, 123, + 122, 121, 119, 118, 117, 116, 115, 114, 113, 110, + 109, 108, 106, 105, 104, 103, 102, 101, 100, 99, + 98, 95, 94, 92, 90, 89, 85, 84, 83, 81, + 80, 78, 77, 74, 73, 72, 71, 70, 68, 64, - 53, 52, 51, 50, 49, 48, 47, 46, 45, 44, - 42, 41, 40, 35, 32, 29, 27, 25, 22, 21, - 19, 18, 14, 11, 7, 5, 3, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159, 159, 159, 159, 159, - 159, 159, 159, 159, 159, 159 + 63, 62, 61, 60, 59, 58, 56, 55, 54, 53, + 52, 51, 50, 49, 48, 47, 46, 45, 44, 42, + 41, 40, 35, 32, 29, 27, 25, 21, 19, 18, + 14, 11, 7, 5, 3, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167, 167, 167, 167, 167, 167, 167, + 167, 167, 167, 167 } ; static yy_state_type yy_last_accepting_state; @@ -586,36 +580,36 @@ int linenum = 0; #define YY_EXTRA_TYPE void * #endif -static int yy_init_globals (void ); +static int yy_init_globals ( void ); /* Accessor methods to globals. These are made visible to non-reentrant scanners for convenience. */ -int yylex_destroy (void ); +int yylex_destroy ( void ); -int yyget_debug (void ); +int yyget_debug ( void ); -void yyset_debug (int debug_flag ); +void yyset_debug ( int debug_flag ); -YY_EXTRA_TYPE yyget_extra (void ); +YY_EXTRA_TYPE yyget_extra ( void ); -void yyset_extra (YY_EXTRA_TYPE user_defined ); +void yyset_extra ( YY_EXTRA_TYPE user_defined ); -FILE *yyget_in (void ); +FILE *yyget_in ( void ); -void yyset_in (FILE * _in_str ); +void yyset_in ( FILE * _in_str ); -FILE *yyget_out (void ); +FILE *yyget_out ( void ); -void yyset_out (FILE * _out_str ); +void yyset_out ( FILE * _out_str ); - int yyget_leng (void ); + int yyget_leng ( void ); -char *yyget_text (void ); +char *yyget_text ( void ); -int yyget_lineno (void ); +int yyget_lineno ( void ); -void yyset_lineno (int _line_number ); +void yyset_lineno ( int _line_number ); /* Macros after this point can all be overridden by user definitions in * section 1. @@ -623,32 +617,31 @@ void yyset_lineno (int _line_number ); #ifndef YY_SKIP_YYWRAP #ifdef __cplusplus -extern "C" int yywrap (void ); +extern "C" int yywrap ( void ); #else -extern int yywrap (void ); +extern int yywrap ( void ); #endif #endif #ifndef YY_NO_UNPUT - static void yyunput (int c,char *buf_ptr ); + static void yyunput ( int c, char *buf_ptr ); #endif #ifndef yytext_ptr -static void yy_flex_strncpy (char *,yyconst char *,int ); +static void yy_flex_strncpy ( char *, const char *, int ); #endif #ifdef YY_NEED_STRLEN -static int yy_flex_strlen (yyconst char * ); +static int yy_flex_strlen ( const char * ); #endif #ifndef YY_NO_INPUT - #ifdef __cplusplus -static int yyinput (void ); +static int yyinput ( void ); #else -static int input (void ); +static int input ( void ); #endif #endif @@ -781,10 +774,10 @@ YY_DECL if ( ! YY_CURRENT_BUFFER ) { yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = - yy_create_buffer(yyin,YY_BUF_SIZE ); + yy_create_buffer( yyin, YY_BUF_SIZE ); } - yy_load_buffer_state( ); + yy_load_buffer_state( ); } { @@ -814,13 +807,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 160 ) - yy_c = yy_meta[(unsigned int) yy_c]; + if ( yy_current_state >= 168 ) + yy_c = yy_meta[yy_c]; } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; + yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 228 ); + while ( yy_base[yy_current_state] != 236 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -880,95 +873,95 @@ YY_RULE_SETUP YY_BREAK case 9: YY_RULE_SETUP -{yylval.number=3; return(HIDDEN);} +{yylval.number=3; return(STATUS);} YY_BREAK case 10: YY_RULE_SETUP -{yylval.number=PCI; return(BUS);} +{yylval.number=5; return(STATUS);} YY_BREAK case 11: YY_RULE_SETUP -{yylval.number=IOAPIC; return(BUS);} +{yylval.number=PCI; return(BUS);} YY_BREAK case 12: YY_RULE_SETUP -{yylval.number=PNP; return(BUS);} +{yylval.number=IOAPIC; return(BUS);} YY_BREAK case 13: YY_RULE_SETUP -{yylval.number=I2C; return(BUS);} +{yylval.number=PNP; return(BUS);} YY_BREAK case 14: YY_RULE_SETUP -{yylval.number=APIC; return(BUS);} +{yylval.number=I2C; return(BUS);} YY_BREAK case 15: YY_RULE_SETUP -{yylval.number=CPU_CLUSTER; return(BUS);} +{yylval.number=APIC; return(BUS);} YY_BREAK case 16: YY_RULE_SETUP -{yylval.number=CPU; return(BUS);} +{yylval.number=CPU_CLUSTER; return(BUS);} YY_BREAK case 17: YY_RULE_SETUP -{yylval.number=DOMAIN; return(BUS);} +{yylval.number=CPU; return(BUS);} YY_BREAK case 18: YY_RULE_SETUP -{yylval.number=GENERIC; return(BUS);} +{yylval.number=DOMAIN; return(BUS);} YY_BREAK case 19: YY_RULE_SETUP -{yylval.number=MMIO; return(BUS);} +{yylval.number=GENERIC; return(BUS);} YY_BREAK case 20: YY_RULE_SETUP -{yylval.number=SPI; return(BUS);} +{yylval.number=MMIO; return(BUS);} YY_BREAK case 21: YY_RULE_SETUP -{yylval.number=USB; return(BUS);} +{yylval.number=SPI; return(BUS);} YY_BREAK case 22: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=USB; return(BUS);} YY_BREAK case 23: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 24: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 25: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 26: YY_RULE_SETUP -{return(INHERIT);} +{return(IOAPIC_IRQ);} YY_BREAK case 27: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{return(INHERIT);} YY_BREAK case 28: YY_RULE_SETUP -{return(END);} +{return(SUBSYSTEMID);} YY_BREAK case 29: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(END);} YY_BREAK case 30: YY_RULE_SETUP -{return(EQUALS);} +{return(SLOT_DESC);} YY_BREAK case 31: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(EQUALS);} YY_BREAK case 32: YY_RULE_SETUP @@ -980,12 +973,11 @@ YY_RULE_SETUP YY_BREAK case 34: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 35: -/* rule 35 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} YY_BREAK case 36: /* rule 36 can match eol */ @@ -993,10 +985,15 @@ YY_RULE_SETUP {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 37: +/* rule 37 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 38: YY_RULE_SETUP {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK -case 38: +case 39: YY_RULE_SETUP ECHO; YY_BREAK @@ -1077,7 +1074,7 @@ case YY_STATE_EOF(INITIAL): { (yy_did_buffer_switch_on_eof) = 0; - if ( yywrap( ) ) + if ( yywrap( ) ) { /* Note: because we've taken care in * yy_get_next_buffer() to have set up @@ -1144,7 +1141,7 @@ static int yy_get_next_buffer (void) { char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf; char *source = (yytext_ptr); - yy_size_t number_to_move, i; + int number_to_move, i; int ret_val; if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] ) @@ -1173,7 +1170,7 @@ static int yy_get_next_buffer (void) /* Try to read more data. */ /* First move last chars to start of buffer. */ - number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1; + number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr) - 1); for ( i = 0; i < number_to_move; ++i ) *(dest++) = *(source++); @@ -1209,7 +1206,8 @@ static int yy_get_next_buffer (void) b->yy_ch_buf = (char *) /* Include room in for 2 EOB chars. */ - yyrealloc((void *) b->yy_ch_buf,(yy_size_t) (b->yy_buf_size + 2) ); + yyrealloc( (void *) b->yy_ch_buf, + (yy_size_t) (b->yy_buf_size + 2) ); } else /* Can't grow it, we don't own it. */ @@ -1241,7 +1239,7 @@ static int yy_get_next_buffer (void) if ( number_to_move == YY_MORE_ADJ ) { ret_val = EOB_ACT_END_OF_FILE; - yyrestart(yyin ); + yyrestart( yyin ); } else @@ -1255,12 +1253,15 @@ static int yy_get_next_buffer (void) else ret_val = EOB_ACT_CONTINUE_SCAN; - if ((int) ((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { + if (((yy_n_chars) + number_to_move) > YY_CURRENT_BUFFER_LVALUE->yy_buf_size) { /* Extend the array by 50%, plus the number we really need. */ int new_size = (yy_n_chars) + number_to_move + ((yy_n_chars) >> 1); - YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc((void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf,(yy_size_t) new_size ); + YY_CURRENT_BUFFER_LVALUE->yy_ch_buf = (char *) yyrealloc( + (void *) YY_CURRENT_BUFFER_LVALUE->yy_ch_buf, (yy_size_t) new_size ); if ( ! YY_CURRENT_BUFFER_LVALUE->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_get_next_buffer()" ); + /* "- 2" to take care of EOB's */ + YY_CURRENT_BUFFER_LVALUE->yy_buf_size = (int) (new_size - 2); } (yy_n_chars) += number_to_move; @@ -1292,10 +1293,10 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 160 ) - yy_c = yy_meta[(unsigned int) yy_c]; + if ( yy_current_state >= 168 ) + yy_c = yy_meta[yy_c]; } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; + yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; } return yy_current_state; @@ -1320,11 +1321,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 160 ) - yy_c = yy_meta[(unsigned int) yy_c]; + if ( yy_current_state >= 168 ) + yy_c = yy_meta[yy_c]; } - yy_current_state = yy_nxt[yy_base[yy_current_state] + (flex_int16_t) yy_c]; - yy_is_jam = (yy_current_state == 159); + yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; + yy_is_jam = (yy_current_state == 167); return yy_is_jam ? 0 : yy_current_state; } @@ -1394,7 +1395,7 @@ static int yy_get_next_buffer (void) else { /* need more input */ - int offset = (yy_c_buf_p) - (yytext_ptr); + int offset = (int) ((yy_c_buf_p) - (yytext_ptr)); ++(yy_c_buf_p); switch ( yy_get_next_buffer( ) ) @@ -1411,13 +1412,13 @@ static int yy_get_next_buffer (void) */ /* Reset buffer status. */ - yyrestart(yyin ); + yyrestart( yyin ); /*FALLTHROUGH*/ case EOB_ACT_END_OF_FILE: { - if ( yywrap( ) ) + if ( yywrap( ) ) return 0; if ( ! (yy_did_buffer_switch_on_eof) ) @@ -1455,11 +1456,11 @@ static int yy_get_next_buffer (void) if ( ! YY_CURRENT_BUFFER ){ yyensure_buffer_stack (); YY_CURRENT_BUFFER_LVALUE = - yy_create_buffer(yyin,YY_BUF_SIZE ); + yy_create_buffer( yyin, YY_BUF_SIZE ); } - yy_init_buffer(YY_CURRENT_BUFFER,input_file ); - yy_load_buffer_state( ); + yy_init_buffer( YY_CURRENT_BUFFER, input_file ); + yy_load_buffer_state( ); } /** Switch to a different input buffer. @@ -1487,7 +1488,7 @@ static int yy_get_next_buffer (void) } YY_CURRENT_BUFFER_LVALUE = new_buffer; - yy_load_buffer_state( ); + yy_load_buffer_state( ); /* We don't actually know whether we did this switch during * EOF (yywrap()) processing, but the only time this flag @@ -1515,7 +1516,7 @@ static void yy_load_buffer_state (void) { YY_BUFFER_STATE b; - b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); + b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); @@ -1524,13 +1525,13 @@ static void yy_load_buffer_state (void) /* yy_ch_buf has to be 2 characters longer than the size given because * we need to put in 2 end-of-buffer characters. */ - b->yy_ch_buf = (char *) yyalloc((yy_size_t) (b->yy_buf_size + 2) ); + b->yy_ch_buf = (char *) yyalloc( (yy_size_t) (b->yy_buf_size + 2) ); if ( ! b->yy_ch_buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" ); b->yy_is_our_buffer = 1; - yy_init_buffer(b,file ); + yy_init_buffer( b, file ); return b; } @@ -1549,9 +1550,9 @@ static void yy_load_buffer_state (void) YY_CURRENT_BUFFER_LVALUE = (YY_BUFFER_STATE) 0; if ( b->yy_is_our_buffer ) - yyfree((void *) b->yy_ch_buf ); + yyfree( (void *) b->yy_ch_buf ); - yyfree((void *) b ); + yyfree( (void *) b ); } /* Initializes or reinitializes a buffer. @@ -1563,7 +1564,7 @@ static void yy_load_buffer_state (void) { int oerrno = errno; - yy_flush_buffer(b ); + yy_flush_buffer( b ); b->yy_input_file = file; b->yy_fill_buffer = 1; @@ -1606,7 +1607,7 @@ static void yy_load_buffer_state (void) b->yy_buffer_status = YY_BUFFER_NEW; if ( b == YY_CURRENT_BUFFER ) - yy_load_buffer_state( ); + yy_load_buffer_state( ); } /** Pushes the new state onto the stack. The new state becomes @@ -1637,7 +1638,7 @@ void yypush_buffer_state (YY_BUFFER_STATE new_buffer ) YY_CURRENT_BUFFER_LVALUE = new_buffer; /* copied from yy_switch_to_buffer. */ - yy_load_buffer_state( ); + yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } @@ -1656,7 +1657,7 @@ void yypop_buffer_state (void) --(yy_buffer_stack_top); if (YY_CURRENT_BUFFER) { - yy_load_buffer_state( ); + yy_load_buffer_state( ); (yy_did_buffer_switch_on_eof) = 1; } } @@ -1666,7 +1667,7 @@ void yypop_buffer_state (void) */ static void yyensure_buffer_stack (void) { - int num_to_alloc; + yy_size_t num_to_alloc; if (!(yy_buffer_stack)) { @@ -1723,7 +1724,7 @@ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) /* They forgot to leave room for the EOB's. */ return NULL; - b = (YY_BUFFER_STATE) yyalloc(sizeof( struct yy_buffer_state ) ); + b = (YY_BUFFER_STATE) yyalloc( sizeof( struct yy_buffer_state ) ); if ( ! b ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_buffer()" ); @@ -1737,7 +1738,7 @@ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) b->yy_fill_buffer = 0; b->yy_buffer_status = YY_BUFFER_NEW; - yy_switch_to_buffer(b ); + yy_switch_to_buffer( b ); return b; } @@ -1750,10 +1751,10 @@ YY_BUFFER_STATE yy_scan_buffer (char * base, yy_size_t size ) * @note If you want to scan bytes that may contain NUL values, then use * yy_scan_bytes() instead. */ -YY_BUFFER_STATE yy_scan_string (yyconst char * yystr ) +YY_BUFFER_STATE yy_scan_string (const char * yystr ) { - return yy_scan_bytes(yystr,(int) strlen(yystr) ); + return yy_scan_bytes( yystr, (int) strlen(yystr) ); } /** Setup the input buffer state to scan the given bytes. The next call to yylex() will @@ -1763,7 +1764,7 @@ YY_BUFFER_STATE yy_scan_string (yyconst char * yystr ) * * @return the newly allocated buffer state object. */ -YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) +YY_BUFFER_STATE yy_scan_bytes (const char * yybytes, int _yybytes_len ) { YY_BUFFER_STATE b; char *buf; @@ -1772,7 +1773,7 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) /* Get memory for full buffer, including space for trailing EOB's. */ n = (yy_size_t) (_yybytes_len + 2); - buf = (char *) yyalloc(n ); + buf = (char *) yyalloc( n ); if ( ! buf ) YY_FATAL_ERROR( "out of dynamic memory in yy_scan_bytes()" ); @@ -1781,7 +1782,7 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) buf[_yybytes_len] = buf[_yybytes_len+1] = YY_END_OF_BUFFER_CHAR; - b = yy_scan_buffer(buf,n ); + b = yy_scan_buffer( buf, n ); if ( ! b ) YY_FATAL_ERROR( "bad buffer in yy_scan_bytes()" ); @@ -1797,9 +1798,9 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) #define YY_EXIT_FAILURE 2 #endif -static void yynoreturn yy_fatal_error (yyconst char* msg ) +static void yynoreturn yy_fatal_error (const char* msg ) { - (void) fprintf( stderr, "%s\n", msg ); + fprintf( stderr, "%s\n", msg ); exit( YY_EXIT_FAILURE ); } @@ -1810,7 +1811,7 @@ static void yynoreturn yy_fatal_error (yyconst char* msg ) do \ { \ /* Undo effects of setting up yytext. */ \ - yy_size_t yyless_macro_arg = (n); \ + int yyless_macro_arg = (n); \ YY_LESS_LINENO(yyless_macro_arg);\ yytext[yyleng] = (yy_hold_char); \ (yy_c_buf_p) = yytext + yyless_macro_arg; \ @@ -1934,7 +1935,7 @@ int yylex_destroy (void) /* Pop the buffer stack, destroying each element. */ while(YY_CURRENT_BUFFER){ - yy_delete_buffer(YY_CURRENT_BUFFER ); + yy_delete_buffer( YY_CURRENT_BUFFER ); YY_CURRENT_BUFFER_LVALUE = NULL; yypop_buffer_state(); } @@ -1955,7 +1956,7 @@ int yylex_destroy (void) */ #ifndef yytext_ptr -static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) +static void yy_flex_strncpy (char* s1, const char * s2, int n ) { int i; @@ -1965,7 +1966,7 @@ static void yy_flex_strncpy (char* s1, yyconst char * s2, int n ) #endif #ifdef YY_NEED_STRLEN -static int yy_flex_strlen (yyconst char * s ) +static int yy_flex_strlen (const char * s ) { int n; for ( n = 0; s[n]; ++n ) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 3b60e2a87f..d784642ae2 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -516,6 +516,7 @@ struct device *new_device(struct bus *parent, new_d->enabled = status & 0x01; new_d->hidden = (status >> 1) & 0x01; + new_d->mandatory = (status >> 2) & 0x01; new_d->chip_instance = chip_instance; chip_instance->ref_count++; @@ -810,6 +811,7 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next fprintf(fil, "},\n"); fprintf(fil, "\t.enabled = %d,\n", ptr->enabled); fprintf(fil, "\t.hidden = %d,\n", ptr->hidden); + fprintf(fil, "\t.mandatory = %d,\n", ptr->mandatory); fprintf(fil, "\t.on_mainboard = 1,\n"); if (ptr->subsystem_vendor > 0) fprintf(fil, "\t.subsystem_vendor = 0x%04x,\n", diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index eea2a14e40..60842f12a1 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -104,6 +104,8 @@ struct device { /* Indicates device status (enabled / hidden or not). */ int enabled; int hidden; + /* non-zero if the device should be included in all cases */ + int mandatory; /* Subsystem IDs for the device. */ int subsystem_vendor; diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 87de6e2763..14eb965bdb 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -29,7 +29,8 @@ device {return(DEVICE);} register {return(REGISTER);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} -hidden {yylval.number=3; return(HIDDEN);} +hidden {yylval.number=3; return(STATUS);} +mandatory {yylval.number=5; return(STATUS);} pci {yylval.number=PCI; return(BUS);} ioapic {yylval.number=IOAPIC; return(BUS);} pnp {yylval.number=PNP; return(BUS);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 8e1e57de54..f4335c79ad 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.5. */ +/* A Bison parser, made by GNU Bison 3.0.4. */ /* Bison implementation for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -44,7 +44,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.0.5" +#define YYBISON_VERSION "3.0.4" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -109,8 +109,8 @@ static struct chip_instance *cur_chip_instance; /* In a future release of Bison, this section will be replaced by #include "sconfig.tab.h_shipped". */ -#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -128,34 +128,35 @@ extern int yydebug; DEVICE = 259, REGISTER = 260, BOOL = 261, - HIDDEN = 262, - BUS = 263, - RESOURCE = 264, - END = 265, - EQUALS = 266, - HEX = 267, - STRING = 268, - PCI = 269, - PNP = 270, - I2C = 271, - APIC = 272, - CPU_CLUSTER = 273, - CPU = 274, - DOMAIN = 275, - IRQ = 276, - DRQ = 277, - SLOT_DESC = 278, - IO = 279, - NUMBER = 280, - SUBSYSTEMID = 281, - INHERIT = 282, - IOAPIC_IRQ = 283, - IOAPIC = 284, - PCIINT = 285, - GENERIC = 286, - SPI = 287, - USB = 288, - MMIO = 289 + STATUS = 262, + MANDATORY = 263, + BUS = 264, + RESOURCE = 265, + END = 266, + EQUALS = 267, + HEX = 268, + STRING = 269, + PCI = 270, + PNP = 271, + I2C = 272, + APIC = 273, + CPU_CLUSTER = 274, + CPU = 275, + DOMAIN = 276, + IRQ = 277, + DRQ = 278, + SLOT_DESC = 279, + IO = 280, + NUMBER = 281, + SUBSYSTEMID = 282, + INHERIT = 283, + IOAPIC_IRQ = 284, + IOAPIC = 285, + PCIINT = 286, + GENERIC = 287, + SPI = 288, + USB = 289, + MMIO = 290 }; #endif @@ -184,7 +185,7 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ /* Copy the second part of user declarations. */ @@ -430,10 +431,10 @@ union yyalloc /* YYFINAL -- State number of the termination state. */ #define YYFINAL 3 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 43 +#define YYLAST 40 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 35 +#define YYNTOKENS 36 /* YYNNTS -- Number of nonterminals. */ #define YYNNTS 15 /* YYNRULES -- Number of rules. */ @@ -444,7 +445,7 @@ union yyalloc /* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 -#define YYMAXUTOK 289 +#define YYMAXUTOK 290 #define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) @@ -481,7 +482,8 @@ static const yytype_uint8 yytranslate[] = 2, 2, 2, 2, 2, 2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, - 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 + 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, + 35 }; #if YYDEBUG @@ -500,12 +502,12 @@ static const yytype_uint8 yyrline[] = static const char *const yytname[] = { "$end", "error", "$undefined", "CHIP", "DEVICE", "REGISTER", "BOOL", - "HIDDEN", "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", - "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", - "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", - "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "$accept", - "devtree", "$@1", "chipchildren", "devicechildren", "chip", "@2", - "device", "@3", "status", "resource", "registers", "subsystemid", + "STATUS", "MANDATORY", "BUS", "RESOURCE", "END", "EQUALS", "HEX", + "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", + "IRQ", "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", + "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", + "$accept", "devtree", "$@1", "chipchildren", "devicechildren", "chip", + "@2", "device", "@3", "status", "resource", "registers", "subsystemid", "ioapic_irq", "smbios_slot_desc", YY_NULLPTR }; #endif @@ -518,7 +520,7 @@ static const yytype_uint16 yytoknum[] = 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289 + 285, 286, 287, 288, 289, 290 }; # endif @@ -536,11 +538,11 @@ static const yytype_uint16 yytoknum[] = STATE-NUM. */ static const yytype_int8 yypact[] = { - -12, 11, 9, -12, 1, -12, -12, -12, 0, 5, - 3, -12, -12, -12, -12, -10, 6, 2, 8, -12, - -12, -12, -12, -12, -3, -1, -12, 13, 4, 7, - -12, -12, -12, -12, -12, -12, 16, 15, 10, -11, - 12, 17, -5, 14, -12, 18, -12, -12, -12 + -12, 6, 9, -12, -1, -12, -12, -12, 0, 5, + 1, -12, -12, -12, -12, -10, 7, 3, 8, -12, + -12, -12, -12, -12, -3, -9, -12, 11, 2, 4, + -12, -12, -12, -12, -12, -12, 15, 17, 10, -11, + 12, 18, -5, 13, -12, 19, -12, -12, -12 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -558,7 +560,7 @@ static const yytype_uint8 yydefact[] = /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -12, -12, -12, -12, -12, -6, -12, 19, -12, -12, + -12, -12, -12, -12, -12, -6, -12, 16, -12, -12, -12, -12, -12, -12, -12 }; @@ -574,39 +576,39 @@ static const yytype_int8 yydefgoto[] = number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_uint8 yytable[] = { - 4, 9, 12, 4, 9, 10, 25, 26, 19, 20, - 11, 3, 4, 15, 6, 17, 16, 18, 30, 43, - 27, 22, 46, 28, 36, 29, 37, 40, 41, 38, - 45, 48, 39, 0, 0, 42, 0, 44, 0, 47, - 0, 0, 0, 31 + 4, 9, 12, 4, 9, 10, 3, 25, 26, 19, + 20, 11, 4, 6, 15, 16, 17, 36, 30, 18, + 43, 27, 22, 46, 28, 37, 29, 40, 38, 0, + 39, 41, 45, 48, 0, 0, 42, 0, 44, 47, + 31 }; static const yytype_int8 yycheck[] = { - 3, 4, 8, 3, 4, 5, 9, 10, 6, 7, - 10, 0, 3, 8, 13, 25, 13, 11, 24, 30, - 23, 13, 27, 26, 25, 28, 13, 11, 13, 25, - 13, 13, 25, -1, -1, 25, -1, 25, -1, 25, - -1, -1, -1, 24 + 3, 4, 8, 3, 4, 5, 0, 10, 11, 6, + 7, 11, 3, 14, 9, 14, 26, 26, 24, 12, + 31, 24, 14, 28, 27, 14, 29, 12, 26, -1, + 26, 14, 14, 14, -1, -1, 26, -1, 26, 26, + 24 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_uint8 yystos[] = { - 0, 36, 37, 0, 3, 40, 13, 41, 38, 4, - 5, 10, 40, 42, 46, 8, 13, 25, 11, 6, - 7, 44, 13, 43, 39, 9, 10, 23, 26, 28, - 40, 42, 45, 47, 48, 49, 25, 13, 25, 25, - 11, 13, 25, 30, 25, 13, 27, 25, 13 + 0, 37, 38, 0, 3, 41, 14, 42, 39, 4, + 5, 11, 41, 43, 47, 9, 14, 26, 12, 6, + 7, 45, 14, 44, 40, 10, 11, 24, 27, 29, + 41, 43, 46, 48, 49, 50, 26, 14, 26, 26, + 12, 14, 26, 31, 26, 14, 28, 26, 14 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_uint8 yyr1[] = { - 0, 35, 37, 36, 38, 38, 38, 38, 39, 39, - 39, 39, 39, 39, 39, 41, 40, 43, 42, 44, - 44, 45, 46, 47, 47, 48, 49, 49, 49 + 0, 36, 38, 37, 39, 39, 39, 39, 40, 40, + 40, 40, 40, 40, 40, 42, 41, 44, 43, 45, + 45, 46, 47, 48, 48, 49, 50, 50, 50 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ @@ -975,7 +977,6 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, case N: \ yyformat = S; \ break - default: /* Avoid compiler warnings. */ YYCASE_(0, YY_("syntax error")); YYCASE_(1, YY_("syntax error, unexpected %s")); YYCASE_(2, YY_("syntax error, unexpected %s, expecting %s")); diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index bcbd644b01..272f651222 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,8 +1,8 @@ -/* A Bison parser, made by GNU Bison 3.0.5. */ +/* A Bison parser, made by GNU Bison 3.0.4. */ /* Bison interface for Yacc-like parsers in C - Copyright (C) 1984, 1989-1990, 2000-2015, 2018 Free Software Foundation, Inc. + Copyright (C) 1984, 1989-1990, 2000-2015 Free Software Foundation, Inc. This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -30,8 +30,8 @@ This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ -#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -49,34 +49,35 @@ extern int yydebug; DEVICE = 259, REGISTER = 260, BOOL = 261, - HIDDEN = 262, - BUS = 263, - RESOURCE = 264, - END = 265, - EQUALS = 266, - HEX = 267, - STRING = 268, - PCI = 269, - PNP = 270, - I2C = 271, - APIC = 272, - CPU_CLUSTER = 273, - CPU = 274, - DOMAIN = 275, - IRQ = 276, - DRQ = 277, - SLOT_DESC = 278, - IO = 279, - NUMBER = 280, - SUBSYSTEMID = 281, - INHERIT = 282, - IOAPIC_IRQ = 283, - IOAPIC = 284, - PCIINT = 285, - GENERIC = 286, - SPI = 287, - USB = 288, - MMIO = 289 + STATUS = 262, + MANDATORY = 263, + BUS = 264, + RESOURCE = 265, + END = 266, + EQUALS = 267, + HEX = 268, + STRING = 269, + PCI = 270, + PNP = 271, + I2C = 272, + APIC = 273, + CPU_CLUSTER = 274, + CPU = 275, + DOMAIN = 276, + IRQ = 277, + DRQ = 278, + SLOT_DESC = 279, + IO = 280, + NUMBER = 281, + SUBSYSTEMID = 282, + INHERIT = 283, + IOAPIC_IRQ = 284, + IOAPIC = 285, + PCIINT = 286, + GENERIC = 287, + SPI = 288, + USB = 289, + MMIO = 290 }; #endif @@ -105,4 +106,4 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_HOME_RMINNICH_PROJECTS_LINUXBOOT_COREBOOTNERF_GITHUBCOREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 0d894a9e35..d55b18bda9 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -31,7 +31,7 @@ static struct chip_instance *cur_chip_instance; int number; } -%token CHIP DEVICE REGISTER BOOL HIDDEN BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO +%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO %% devtree: { cur_parent = root_parent; } chip; @@ -56,7 +56,7 @@ device: DEVICE BUS NUMBER /* == devnum */ status { cur_parent = $5->parent; }; -status: BOOL | HIDDEN; +status: BOOL | STATUS ; resource: RESOURCE NUMBER /* == resnum */ EQUALS NUMBER /* == resval */ { add_resource(cur_parent, $1, strtol($2, NULL, 0), strtol($4, NULL, 0)); } ; From fbdd18b650c321c0cdb54862243a572e897e6d11 Mon Sep 17 00:00:00 2001 From: Pavel Sayekat Date: Sun, 9 Feb 2020 10:54:54 +0600 Subject: [PATCH 096/151] superio/nuvoton/nct5539d/acpi: fix # comment in superio.asl Change-Id: Ic2ba1f9b744014f97d318671bf86468f4d6c6469 Signed-off-by: Pavel Sayekat Reviewed-on: https://review.coreboot.org/c/coreboot/+/38782 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/superio/nuvoton/nct5539d/acpi/superio.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/nuvoton/nct5539d/acpi/superio.asl b/src/superio/nuvoton/nct5539d/acpi/superio.asl index 70a84a28a7..6f494210fc 100644 --- a/src/superio/nuvoton/nct5539d/acpi/superio.asl +++ b/src/superio/nuvoton/nct5539d/acpi/superio.asl @@ -1,5 +1,5 @@ -# SPDX-License-Identifier: GPL-2.0-only -# This file is part of the coreboot project. +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ /* * Include this file into a mainboard's DSDT _SB device tree and it will From 6d5f007813f6a2ffbdd6a633f31d207672eee2e1 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 7 Feb 2020 17:11:40 +0100 Subject: [PATCH 097/151] cpu/x86/smm: Add overflow check Rather bail out than run into undefined behavior. Change-Id: Ife26a0abed0ce6bcafe1e7cd8f499618631c4df4 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38763 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons Reviewed-by: --- src/cpu/x86/smm/smm_module_loader.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index a421436893..81020a460a 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -202,6 +202,8 @@ static int smm_module_setup_stub(void *smbase, struct smm_loader_params *params, /* Adjust remaining size to account for save state. */ total_save_state_size = params->per_cpu_save_state_size * params->num_concurrent_save_states; + if (total_save_state_size > size) + return -1; size -= total_save_state_size; /* The save state size encroached over the first SMM entry point. */ From 8e4654527ef5fec658ca5aacad0612653d3dcf30 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Mon, 23 Sep 2019 20:59:38 +0530 Subject: [PATCH 098/151] soc/intel/{common,skl,cnl,icl,apl,tgl}: Move HFSTS1 register definition to SoC Below changes are implemented: 1. Move HFSTS1 register definition to SoC since HFSTS1 register definition is specific to a SoC. Moving structure back to SoC specific to avoid unnecessay SoC specific macros in the common code. 2. Define a set of APIs in common code since CSE operation modes and working states are same across SoCs. cse_is_hfs1_com_normal(void) cse_is_hfs1_com_secover_mei_msg(void) cse_is_hfs1_com_soft_temp_disable(void) cse_is_hfs1_cws_normal(void) 3. Modify existing code to use callbacks to get data of me_hfs1 structure. TEST=Build and Boot hatch, soraka, tglrvp, bobba and iclrvp boards. Change-Id: If7ea6043d7b5473d0c16e83d7b2d4b620c125652 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/35546 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/apollolake/include/soc/me.h | 43 +++++++++++++++++ src/soc/intel/cannonlake/include/soc/me.h | 28 +++++++++++ src/soc/intel/common/block/cse/cse.c | 44 +++++++++++------ .../common/block/include/intelblocks/cse.h | 48 +++++++++---------- src/soc/intel/icelake/include/soc/me.h | 43 +++++++++++++++++ src/soc/intel/skylake/include/soc/me.h | 24 ++++++++++ src/soc/intel/tigerlake/include/soc/me.h | 43 +++++++++++++++++ 7 files changed, 235 insertions(+), 38 deletions(-) create mode 100644 src/soc/intel/apollolake/include/soc/me.h create mode 100644 src/soc/intel/icelake/include/soc/me.h create mode 100644 src/soc/intel/tigerlake/include/soc/me.h diff --git a/src/soc/intel/apollolake/include/soc/me.h b/src/soc/intel/apollolake/include/soc/me.h new file mode 100644 index 0000000000..7ac4deecfa --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/me.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _APOLLOLAKE_ME_H_ +#define _APOLLOLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 bist_finished: 1; + u32 hw_bist_passed: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +#endif /* _APOLLOLAKE_ME_H_ */ diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 5b411d3621..041769b19a 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -16,6 +16,34 @@ #ifndef _CANNONLAKE_ME_H_ #define _CANNONLAKE_ME_H_ +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; +#if CONFIG(SOC_INTEL_COMETLAKE) + u32 invoke_enhance_dbg_mode:1; +#else + u32 reserved0: 1; +#endif + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved1: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + void dump_me_status(void *unused); #endif /* _CANNONLAKE_ME_H_ */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 4b9d1a4030..440b59b819 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -24,6 +24,7 @@ #include #include #include +#include #include #include @@ -238,17 +239,35 @@ static int cse_ready(void) return csr & CSR_READY; } -/* - * Checks if CSE is in ME_HFS1_COM_SECOVER_MEI_MSG operation mode. This is the mode where - * CSE will allow reflashing of CSE region. - */ -static uint8_t check_cse_sec_override_mode(void) +static bool cse_check_hfs1_com(int mode) { union me_hfsts1 hfs1; hfs1.data = me_read_config32(PCI_ME_HFSTS1); - if (hfs1.fields.operation_mode == ME_HFS1_COM_SECOVER_MEI_MSG) - return 1; - return 0; + return hfs1.fields.operation_mode == mode; +} + +bool cse_is_hfs1_cws_normal(void) +{ + union me_hfsts1 hfs1; + hfs1.data = me_read_config32(PCI_ME_HFSTS1); + if (hfs1.fields.working_state == ME_HFS1_CWS_NORMAL) + return true; + return false; +} + +bool cse_is_hfs1_com_normal(void) +{ + return cse_check_hfs1_com(ME_HFS1_COM_NORMAL); +} + +bool cse_is_hfs1_com_secover_mei_msg(void) +{ + return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); +} + +bool cse_is_hfs1_com_soft_temp_disable(void) +{ + return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); } /* Makes the host ready to communicate with CSE */ @@ -266,7 +285,7 @@ uint8_t wait_cse_sec_override_mode(void) { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); - while (!check_cse_sec_override_mode()) { + while (!cse_is_hfs1_com_secover_mei_msg()) { udelay(HECI_DELAY); if (stopwatch_expired(&sw)) return 0; @@ -632,18 +651,15 @@ int send_hmrfpo_enable_msg(void) struct hmrfpo_enable_resp resp; size_t resp_size = sizeof(struct hmrfpo_enable_resp); - union me_hfsts1 hfs1; printk(BIOS_DEBUG, "HECI: Send HMRFPO Enable Command\n"); - hfs1.data = me_read_config32(PCI_ME_HFSTS1); /* * This command can be run only if: * - Working state is normal and * - Operation mode is normal or temporary disable mode. */ - if (hfs1.fields.working_state != ME_HFS1_CWS_NORMAL || - (hfs1.fields.operation_mode != ME_HFS1_COM_NORMAL && - hfs1.fields.operation_mode != ME_HFS1_COM_SOFT_TEMP_DISABLE)) { + if (!cse_is_hfs1_cws_normal() || + (!cse_is_hfs1_com_normal() && !cse_is_hfs1_com_soft_temp_disable())) { printk(BIOS_ERR, "HECI: ME not in required Mode\n"); goto failed; } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 515f1a47d5..46730707c8 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -51,30 +51,6 @@ enum { PCI_ME_HFSTS6 = 0x6C, }; -/* ME Host Firmware Status register 1 */ -union me_hfsts1 { - u32 data; - struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 reserved1: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 d3_support_valid: 1; - u32 d0i3_support_valid: 1; - } __packed fields; -}; - /* HECI Message Header */ struct mkhi_hdr { uint8_t group_id; @@ -172,4 +148,28 @@ int send_hmrfpo_get_status_msg(void); #define MKHI_HMRFPO_LOCKED 1 #define MKHI_HMRFPO_ENABLED 2 +/* + * Checks current working operation state is normal or not. + * Returns true if CSE's current working state is normal, otherwise false. + */ +bool cse_is_hfs1_cws_normal(void); + +/* + * Checks CSE's current operation mode is normal or not. + * Returns true if CSE's current operation mode is normal, otherwise false. + */ +bool cse_is_hfs1_com_normal(void); + +/* + * Checks CSE's current operation mode is SECOVER_MEI_MSG or not. + * Returns true if CSE's current operation mode is SECOVER_MEI_MSG, otherwise false. + */ +bool cse_is_hfs1_com_secover_mei_msg(void); + +/* + * Checks CSE's current operation mode is Soft Disable Mode or not. + * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false. + */ +bool cse_is_hfs1_com_soft_temp_disable(void); + #endif // SOC_INTEL_COMMON_CSE_H diff --git a/src/soc/intel/icelake/include/soc/me.h b/src/soc/intel/icelake/include/soc/me.h new file mode 100644 index 0000000000..b1646a2716 --- /dev/null +++ b/src/soc/intel/icelake/include/soc/me.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ICELAKE_ME_H_ +#define _ICELAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 reserved1: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +#endif /* _ICELAKE_ME_H_ */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index c1fdc8154a..30de2197f5 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -123,6 +123,30 @@ #define ME_HFS2_PMEVENT_CM3_CM3PG 0xe #define ME_HFS2_PMEVENT_CM0PG_CM0 0xf +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 mfg_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 reserved1: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 d3_support_valid: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + union me_hfs2 { u32 data; struct { diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h new file mode 100644 index 0000000000..3baa0045bd --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _TIGERLAKE_ME_H_ +#define _TIGERLAKE_ME_H_ + +/* ME Host Firmware Status register 1 */ +union me_hfsts1 { + u32 data; + struct { + u32 working_state: 4; + u32 spi_protection_mode: 1; + u32 fpt_bad: 1; + u32 operation_state: 3; + u32 fw_init_complete: 1; + u32 ft_bup_ld_flr: 1; + u32 update_in_progress: 1; + u32 error_code: 4; + u32 operation_mode: 4; + u32 reset_count: 4; + u32 boot_options_present: 1; + u32 invoke_enhance_dbg_mode: 1; + u32 bist_test_state: 1; + u32 bist_reset_request: 1; + u32 current_power_source: 2; + u32 reserved: 1; + u32 d0i3_support_valid: 1; + } __packed fields; +}; + +#endif /* _TIGERLAKE_ME_H_ */ From ff072e6ebfb4f3cf5736e317688930e588a62ec2 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 27 Nov 2019 14:55:16 +0530 Subject: [PATCH 099/151] soc/intel/common: Rename functions for consistent naming Below changes are done: 1. Rename below functions to have consistent naming: set_host_ready() -> cse_set_host_ready() wait_cse_sec_override_mode() -> cse_wait_sec_override_mode() send_hmrfpo_enable_msg() -> cse_hmrfpo_enable() send_hmrfpo_get_status_msg() -> cse_hmrfpo_get_status() 2. Additional debug messages are added in cse_wait_sec_override_mode(). TEST=Build and Boot hatch board. Change-Id: Icfcf1631cc37faacdea9ad84be55f5710104bad5 Signed-off-by: Rizwan Qureshi Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/37282 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/cse/cse.c | 19 +++++++++++-------- .../common/block/include/intelblocks/cse.h | 12 ++++++------ 2 files changed, 17 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 440b59b819..8fbaba5a2c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -271,7 +271,7 @@ bool cse_is_hfs1_com_soft_temp_disable(void) } /* Makes the host ready to communicate with CSE */ -void set_host_ready(void) +void cse_set_host_ready(void) { uint32_t csr; csr = read_host_csr(); @@ -280,17 +280,20 @@ void set_host_ready(void) write_host_csr(csr); } -/* Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds */ -uint8_t wait_cse_sec_override_mode(void) +/* Polls for ME mode ME_HFS1_COM_SECOVER_MEI_MSG for 15 seconds */ +uint8_t cse_wait_sec_override_mode(void) { struct stopwatch sw; stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); while (!cse_is_hfs1_com_secover_mei_msg()) { udelay(HECI_DELAY); - if (stopwatch_expired(&sw)) + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: Timed out waiting for SEC_OVERRIDE mode!\n"); return 0; + } } - + printk(BIOS_DEBUG, "HECI: CSE took %lu ms to enter security override mode\n", + stopwatch_duration_msecs(&sw)); return 1; } @@ -544,7 +547,7 @@ int heci_reset(void) if (wait_heci_ready()) { /* Device is back on its imaginary feet, clear reset */ - set_host_ready(); + cse_set_host_ready(); return 1; } @@ -622,7 +625,7 @@ int send_heci_reset_req_message(uint8_t rst_type) } /* Sends HMRFPO Enable command to CSE */ -int send_hmrfpo_enable_msg(void) +int cse_hmrfpo_enable(void) { struct hmrfpo_enable_msg { struct mkhi_hdr hdr; @@ -682,7 +685,7 @@ failed: * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. * The status can be DISABLES/LOCKED/ENABLED */ -int send_hmrfpo_get_status_msg(void) +int cse_hmrfpo_get_status(void) { struct hmrfpo_get_status_msg { struct mkhi_hdr hdr; diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 46730707c8..6233f7d193 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -51,7 +51,7 @@ enum { PCI_ME_HFSTS6 = 0x6C, }; -/* HECI Message Header */ +/* MKHI Message Header */ struct mkhi_hdr { uint8_t group_id; uint8_t command:7; @@ -103,14 +103,14 @@ uint32_t me_read_config32(int offset); */ bool is_cse_enabled(void); -/* Makes the host ready to communicate with CSE*/ -void set_host_ready(void); +/* Makes the host ready to communicate with CSE */ +void cse_set_host_ready(void); /* * Polls for ME state 'HECI_OP_MODE_SEC_OVERRIDE' for 15 seconds. * Returns 0 on failure and 1 on success. */ -uint8_t wait_cse_sec_override_mode(void); +uint8_t cse_wait_sec_override_mode(void); /* * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be @@ -123,14 +123,14 @@ int send_heci_reset_req_message(uint8_t rst_type); * Send HMRFPO_ENABLE command. * returns 0 on failure and 1 on success. */ -int send_hmrfpo_enable_msg(void); +int cse_hmrfpo_enable(void); /* * Send HMRFPO_GET_STATUS command. * returns -1 on failure and 0 (DISABLED)/ 1 (LOCKED)/ 2 (ENABLED) * on success. */ -int send_hmrfpo_get_status_msg(void); +int cse_hmrfpo_get_status(void); /* Fixed Address MEI Header's Host Address field value */ #define BIOS_HOST_ADDR 0x00 From 63be9181cba7b05e3ed3578415cbb589ffa9d4c2 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sun, 19 Jan 2020 12:38:56 +0530 Subject: [PATCH 100/151] soc/intel/common: Add description to HMRFPO status Below changes are implemented: 1. Fix typos. 2. Rename 'padding' field of hmrfpo_get_status_resp struct to 'reserved' to match with ME BWG Guide. 3. Add documentation for HMRFPO Status. TEST=Build and boot hatch Change-Id: I4db9bdf7386c48e17ed0373cf334ccff358d1951 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38480 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/cse/cse.c | 4 ++-- src/soc/intel/common/block/include/intelblocks/cse.h | 8 ++++++++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 8fbaba5a2c..d323c76b74 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -683,7 +683,7 @@ failed: /* * Sends HMRFPO Get Status command to CSE to get the HMRFPO status. - * The status can be DISABLES/LOCKED/ENABLED + * The status can be DISABLED/LOCKED/ENABLED */ int cse_hmrfpo_get_status(void) { @@ -694,7 +694,7 @@ int cse_hmrfpo_get_status(void) struct hmrfpo_get_status_resp { struct mkhi_hdr hdr; uint8_t status; - uint8_t padding[3]; + uint8_t reserved[3]; } __packed; struct hmrfpo_get_status_msg msg = { diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 6233f7d193..1377bd43fb 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -144,8 +144,16 @@ int cse_hmrfpo_get_status(void); #define CSE_RESET_ONLY 3 /* HMRFPO Status types */ +/* Host can't access ME region */ #define MKHI_HMRFPO_DISABLED 0 + +/* + * ME Firmware locked down HMRFPO Feature. + * Host can't access ME region. + */ #define MKHI_HMRFPO_LOCKED 1 + +/* Host can access ME region */ #define MKHI_HMRFPO_ENABLED 2 /* From f2eb687d19fb5ad6a74f1e938344b6d177765528 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 5 Dec 2019 19:54:16 +0530 Subject: [PATCH 101/151] soc/intel/{cnl,icl,skl,tgl,common}: Make changes to send_heci_reset_req_message() Below changes have been implemented in send_heci_reset_req_message(): 1. Modify return values to align with other functions in the same file. 2. Add additional logging. 3. Replace macro definitions of reset types with ENUM. 4. Make changes to caller functions to sync with new return values. 5. Rename send_heci_reset_req_message() to cse_request_global_reset(). Test=Verified on hatch board. Change-Id: I979b169a5bb3a5d4028ef030bcef2b8eeffe86e3 Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/37584 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/reset.c | 2 +- src/soc/intel/common/block/cse/cse.c | 22 +++++++++---------- .../common/block/include/intelblocks/cse.h | 19 ++++++++-------- src/soc/intel/icelake/reset.c | 2 +- src/soc/intel/skylake/me.c | 2 +- src/soc/intel/skylake/reset.c | 2 +- src/soc/intel/tigerlake/reset.c | 2 +- 7 files changed, 25 insertions(+), 26 deletions(-) diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index 4758faf7c5..28211e37ef 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -24,7 +24,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_req_message(GLOBAL_RESET)) + if (cse_request_global_reset(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index d323c76b74..c82f3bdc7a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -582,7 +582,7 @@ uint32_t me_read_config32(int offset) * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be GLOBAL_RESET/ * HOST_RESET_ONLY/CSE_RESET_ONLY. */ -int send_heci_reset_req_message(uint8_t rst_type) +int cse_request_global_reset(enum rst_req_type rst_type) { int status; struct mkhi_hdr reply; @@ -601,27 +601,25 @@ int send_heci_reset_req_message(uint8_t rst_type) }; size_t reply_size; + printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); if (!((rst_type == GLOBAL_RESET) || - (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) - return -1; + (rst_type == HOST_RESET_ONLY) || (rst_type == CSE_RESET_ONLY))) { + printk(BIOS_ERR, "HECI: Unsupported reset type is requested\n"); + return 0; + } heci_reset(); reply_size = sizeof(reply); memset(&reply, 0, reply_size); - printk(BIOS_DEBUG, "HECI: Global Reset(Type:%d) Command\n", rst_type); if (rst_type == CSE_RESET_ONLY) - status = heci_send_receive(&msg, sizeof(msg), NULL, 0); + status = heci_send(&msg, sizeof(msg), BIOS_HOST_ADDR, HECI_MKHI_ADDR); else - status = heci_send_receive(&msg, sizeof(msg), &reply, - &reply_size); + status = heci_send_receive(&msg, sizeof(msg), &reply, &reply_size); - if (status != 1) - return -1; - - printk(BIOS_DEBUG, "HECI: Global Reset success!\n"); - return 0; + printk(BIOS_DEBUG, "HECI: Global Reset %s!\n", status ? "success" : "failure"); + return status; } /* Sends HMRFPO Enable command to CSE */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 1377bd43fb..aff330a815 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -112,12 +112,18 @@ void cse_set_host_ready(void); */ uint8_t cse_wait_sec_override_mode(void); +enum rst_req_type { + GLOBAL_RESET = 1, + HOST_RESET_ONLY = 2, + CSE_RESET_ONLY = 3, +}; + /* - * Sends GLOBAL_RESET_REQ cmd to CSE.The reset type can be - * GLOBAL_RESET/HOST_RESET_ONLY/CSE_RESET_ONLY. - * Returns -1 on failure and 0 on success. + * Sends GLOBAL_RESET_REQ cmd to CSE. + * The reset type can be one of the above defined reset type. + * Returns 0 on failure and 1 on success. */ -int send_heci_reset_req_message(uint8_t rst_type); +int cse_request_global_reset(enum rst_req_type rst_type); /* * Send HMRFPO_ENABLE command. @@ -138,11 +144,6 @@ int cse_hmrfpo_get_status(void); /* Fixed Address MEI Header's ME Address field value */ #define HECI_MKHI_ADDR 0x07 -/* Command GLOBAL_RESET_REQ Reset Types */ -#define GLOBAL_RESET 1 -#define HOST_RESET_ONLY 2 -#define CSE_RESET_ONLY 3 - /* HMRFPO Status types */ /* Host can't access ME region */ #define MKHI_HMRFPO_DISABLED 0 diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 5526a42545..d79ae455b0 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -24,7 +24,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_req_message(GLOBAL_RESET)) + if (cse_request_global_reset(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index d53d91ebdb..17a66bc618 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -441,7 +441,7 @@ int send_global_reset(void) goto ret; /* ME should be in Normal Mode for this command */ - status = send_heci_reset_req_message(GLOBAL_RESET); + status = cse_request_global_reset(GLOBAL_RESET); ret: return status; } diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index 8f5bf30946..b16e11c923 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -37,7 +37,7 @@ static void do_force_global_reset(void) void do_global_reset(void) { - if (send_global_reset() != 0) { + if (!send_global_reset()) { /* If ME unable to reset platform then * force global reset using PMC CF9GR register*/ do_force_global_reset(); diff --git a/src/soc/intel/tigerlake/reset.c b/src/soc/intel/tigerlake/reset.c index 674cf68dcc..11e411da48 100644 --- a/src/soc/intel/tigerlake/reset.c +++ b/src/soc/intel/tigerlake/reset.c @@ -24,7 +24,7 @@ void do_global_reset(void) { /* Ask CSE to do the global reset */ - if (!send_heci_reset_req_message(GLOBAL_RESET)) + if (cse_request_global_reset(GLOBAL_RESET)) return; /* global reset if CSE fail to reset */ From 6f9a77851b9cf71bd3fdee3a424e779171613851 Mon Sep 17 00:00:00 2001 From: Marcello Sylvester Bauer Date: Tue, 4 Feb 2020 17:20:50 +0100 Subject: [PATCH 102/151] util/ifdtool: Support modification of single Flash Descriptor Add the capability to update the Flash Descriptor directly instead of raising a Segmentation Fault. In this way it will be possible to add a Kconfig options to modify the ifd descriptor at build-time. Change-Id: Id3db09291af2bd2e759c283e316afd5da1fb4ca7 Signed-off-by: Marcello Sylvester Bauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/38711 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- util/ifdtool/ifdtool.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index 0b6b210647..2bf2f4d266 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -1336,11 +1336,18 @@ static void new_layout(const char *filename, char *image, int size, new_extent = new_regions[i].limit; } - new_extent = next_pow2(new_extent - 1); - if (new_extent != size) { - printf("The image has changed in size.\n"); - printf("The old image is %d bytes.\n", size); - printf("The new image is %d bytes.\n", new_extent); + /* check if the image is actually a Flash Descriptor region */ + if (size == new_regions[0].size) { + printf("The image is a single Flash Descriptor:\n"); + printf(" Only the descriptor will be modified\n"); + new_extent = size; + } else { + new_extent = next_pow2(new_extent - 1); + if (new_extent != size) { + printf("The image has changed in size.\n"); + printf("The old image is %d bytes.\n", size); + printf("The new image is %d bytes.\n", new_extent); + } } /* copy regions to a new image */ @@ -1367,6 +1374,12 @@ static void new_layout(const char *filename, char *image, int size, offset_current = current->size - new->size; } + if (size < current->base + offset_current + copy_size) { + printf("Skip descriptor %d (%s) (region missing in the old image)\n", i, + region_name(i)); + continue; + }; + printf("Copy Descriptor %d (%s) (%d bytes)\n", i, region_name(i), copy_size); printf(" from %08x+%08x:%08x (%10d)\n", current->base, @@ -1384,6 +1397,7 @@ static void new_layout(const char *filename, char *image, int size, if (!frba) exit(EXIT_FAILURE); + printf("Modify Flash Descriptor regions\n"); for (i = 1; i < max_regions; i++) set_region(frba, i, &new_regions[i]); From f9bb6756907c52564eabe8867ee4fdd1cf50c6ed Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Wed, 5 Feb 2020 13:29:37 +0800 Subject: [PATCH 103/151] mb/google/octopus: Override VBT selection for Bloog Since most of Bloog series SKUs need to disable DRRS support. If Bloog and Unprovisioned SKUs then return vbt.bin to enable DRRS support, return vbt_blooguard.bin for other SKUs to disable DRRS support. Bipship follow blooguard to disable DRRS support. BUG=b:148892903, b:147021309 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage check i915_drrs_status shows DRRS supported NO when SKU ID is bipship. Change-Id: I61f12d4ddea17a05255751fde2a5ce822dd2e782 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/38716 Tested-by: build bot (Jenkins) Reviewed-by: Marco Chen Reviewed-by: Karthik Ramasubramanian --- .../google/octopus/variants/bloog/variant.c | 42 +++++++++++-------- 1 file changed, 25 insertions(+), 17 deletions(-) diff --git a/src/mainboard/google/octopus/variants/bloog/variant.c b/src/mainboard/google/octopus/variants/bloog/variant.c index 18f44b955a..699385ef09 100644 --- a/src/mainboard/google/octopus/variants/bloog/variant.c +++ b/src/mainboard/google/octopus/variants/bloog/variant.c @@ -30,29 +30,34 @@ enum { SKU_50_BLOOGUARD = 50, /* kb blit, USI Stylus */ SKU_51_BLOOGUARD = 51, /* no kb blit, no USI Stylus */ SKU_52_BLOOGUARD = 52, /* no kb blit, USI Stylus */ + SKU_53_BIPSHIP = 53, /* no kb blit, TS, 360, no Stylus, no rare-cam */ + SKU_54_BIPSHIP = 54, /* kb blit, TS, 360, no Stylus, no rare-cam */ SKU_65_BLOOGLET = 65, /* TS, kb blit */ SKU_66_BLOOGLET = 66, /* TS, no kb blit */ SKU_67_BLOOGLET = 67, /* non-TS, kb blit */ SKU_68_BLOOGLET = 68, /* non-TS, no kb blit */ + SKU_255_UNPROVISIONED = 255, }; const char *get_wifi_sar_cbfs_filename(void) { const char *filename = NULL; - uint32_t sku_id; - sku_id = get_board_sku(); + uint32_t sku_id = get_board_sku(); - if (sku_id == SKU_UNKNOWN) - return NULL; - - if (sku_id == SKU_33_BLOOG || sku_id == SKU_34_BLOOG || - sku_id == SKU_35_BLOOG || sku_id == SKU_36_BLOOG) + switch (sku_id) { + case SKU_33_BLOOG: + case SKU_34_BLOOG: + case SKU_35_BLOOG: + case SKU_36_BLOOG: filename = "wifi_sar-bloog.hex"; - - if (sku_id == SKU_49_BLOOGUARD || sku_id == SKU_50_BLOOGUARD || - sku_id == SKU_51_BLOOGUARD || sku_id == SKU_52_BLOOGUARD) + break; + case SKU_49_BLOOGUARD: + case SKU_50_BLOOGUARD: + case SKU_51_BLOOGUARD: + case SKU_52_BLOOGUARD: filename = "wifi_sar-blooguard.hex"; - + break; + } return filename; } @@ -62,11 +67,14 @@ const char *mainboard_vbt_filename(void) sku_id = get_board_sku(); - if (sku_id == SKU_49_BLOOGUARD || sku_id == SKU_50_BLOOGUARD || - sku_id == SKU_51_BLOOGUARD || sku_id == SKU_52_BLOOGUARD || - sku_id == SKU_65_BLOOGLET || sku_id == SKU_66_BLOOGLET || - sku_id == SKU_67_BLOOGLET || sku_id == SKU_68_BLOOGLET) + switch (sku_id) { + case SKU_33_BLOOG: + case SKU_34_BLOOG: + case SKU_35_BLOOG: + case SKU_36_BLOOG: + case SKU_255_UNPROVISIONED: + return "vbt.bin"; + default: return "vbt_blooguard.bin"; - - return "vbt.bin"; + } } From cedd4525f27694d55014c7d8df540fe409e9677f Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 5 Feb 2020 16:36:49 +0100 Subject: [PATCH 104/151] Documentation: Indent code blocks instead of using ``` Both versions are correct, but especially for one liners indenting them with four spaces instead of using ``` blocks helps readability of the source file. Change-Id: Ie2543c8c4cccefd74e966f784e651ed7dc3a9252 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38720 Reviewed-by: Peter Lemenkov Tested-by: build bot (Jenkins) --- .../mainboard/lenovo/ivb_internal_flashing.md | 343 +++++++++--------- 1 file changed, 166 insertions(+), 177 deletions(-) diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md index d0ac3cdd79..355cf98448 100644 --- a/Documentation/mainboard/lenovo/ivb_internal_flashing.md +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -63,55 +63,51 @@ directly. Therefore you need to modify the bootable CD image you just downloaded. Extract an El Torito image: -``` -geteltorito -o ./bios.img g1uj41us.iso -``` + + geteltorito -o ./bios.img g1uj41us.iso + Mount the partition in that image: -``` -sudo mount -t vfat ./bios.img /mnt -o loop,offset=16384 -``` + + sudo mount -t vfat ./bios.img /mnt -o loop,offset=16384 + List files, find the `AUTOEXEC.BAT` file and the `FLASH` directory: -``` -ls /mnt -ls /mnt/FLASH -``` + + ls /mnt + ls /mnt/FLASH Inside the `FLASH` directory, there should be a directory called `G1ET93WW` or similar (exact name depends on your ThinkPad model and BIOS version). See what's inside: -``` -ls /mnt/FLASH/G1ET93WW -``` + + ls /mnt/FLASH/G1ET93WW + There must be a file with `.FL1` extension called `$01D2000.FL1` or something similar. Now open the `AUTOEXEC.BAT` file: -``` -sudo vim /mnt/AUTOEXEC.BAT -``` + + sudo vim /mnt/AUTOEXEC.BAT + You will see a list of commands: -``` -@ECHO OFF -PROMPT $p$g -cd c:\flash -command.com -``` + + @ECHO OFF + PROMPT $p$g + cd c:\flash + command.com + Replace the last line (`command.com`) with this (change path to the `.FL1` file according to yours): -``` -dosflash.exe /sd /file G1ET93WW\$01D2000.FL1 -``` + + dosflash.exe /sd /file G1ET93WW\$01D2000.FL1 Save the file, then unmount the partition: -``` -sudo unmount /mnt -``` + + sudo unmount /mnt Write this image to a USB drive (replace `/dev/sdX` with your USB drive device name): -``` -sudo dd if=./bios.img of=/dev/sdX bs=1M -``` + + sudo dd if=./bios.img of=/dev/sdX bs=1M Now reboot and press F1 to enter BIOS settings. Open the **Startup** tab and set the startup mode to **Legacy** (or **Both**/**Legacy First**): @@ -167,69 +163,66 @@ To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or SPI protected ranges (PRx) to have a WP bit set to 0. Let's see what we have. Examine HSFS register: -``` -sudo chipsec_main -m chipsec.modules.common.spi_lock -``` + + sudo chipsec_main -m chipsec.modules.common.spi_lock + You should see that FLOCKDN=1: -``` -[x][ ======================================================================= -[x][ Module: SPI Flash Controller Configuration Locks -[x][ ======================================================================= -[*] HSFS = 0xE009 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) - [00] FDONE = 1 << Flash Cycle Done - [01] FCERR = 0 << Flash Cycle Error - [02] AEL = 0 << Access Error Log - [03] BERASE = 1 << Block/Sector Erase Size - [05] SCIP = 0 << SPI cycle in progress - [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status - [14] FDV = 1 << Flash Descriptor Valid - [15] FLOCKDN = 1 << Flash Configuration Lock-Down -``` + + [x][ ======================================================================= + [x][ Module: SPI Flash Controller Configuration Locks + [x][ ======================================================================= + [*] HSFS = 0xE009 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) + [00] FDONE = 1 << Flash Cycle Done + [01] FCERR = 0 << Flash Cycle Error + [02] AEL = 0 << Access Error Log + [03] BERASE = 1 << Block/Sector Erase Size + [05] SCIP = 0 << SPI cycle in progress + [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status + [14] FDV = 1 << Flash Descriptor Valid + [15] FLOCKDN = 1 << Flash Configuration Lock-Down Then check BIOS_CNTL and PR0-PR4: -``` -sudo chipsec_main -m common.bios_wp -``` + + sudo chipsec_main -m common.bios_wp + Good news: on old BIOS versions, SMM_BWP=0 and BLE=0. Bad news: there are 4 write protected SPI ranges: -``` -[x][ ======================================================================= -[x][ Module: BIOS Region Write Protection -[x][ ======================================================================= -[*] BC = 0x 8 << BIOS Control (b:d.f 00:31.0 + 0xDC) - [00] BIOSWE = 0 << BIOS Write Enable - [01] BLE = 0 << BIOS Lock Enable - [02] SRC = 2 << SPI Read Configuration - [04] TSS = 0 << Top Swap Status - [05] SMM_BWP = 0 << SMM BIOS Write Protection -[-] BIOS region write protection is disabled! + [x][ ======================================================================= + [x][ Module: BIOS Region Write Protection + [x][ ======================================================================= + [*] BC = 0x 8 << BIOS Control (b:d.f 00:31.0 + 0xDC) + [00] BIOSWE = 0 << BIOS Write Enable + [01] BLE = 0 << BIOS Lock Enable + [02] SRC = 2 << SPI Read Configuration + [04] TSS = 0 << Top Swap Status + [05] SMM_BWP = 0 << SMM BIOS Write Protection + [-] BIOS region write protection is disabled! -[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF -SPI Protected Ranges ------------------------------------------------------------- -PRx (offset) | Value | Base | Limit | WP? | RP? ------------------------------------------------------------- -PR0 (74) | 00000000 | 00000000 | 00000000 | 0 | 0 -PR1 (78) | 8BFF0B40 | 00B40000 | 00BFFFFF | 1 | 0 -PR2 (7C) | 8B100B10 | 00B10000 | 00B10FFF | 1 | 0 -PR3 (80) | 8ADE0AD0 | 00AD0000 | 00ADEFFF | 1 | 0 -PR4 (84) | 8AAF0800 | 00800000 | 00AAFFFF | 1 | 0 -``` + [*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF + SPI Protected Ranges + ------------------------------------------------------------ + PRx (offset) | Value | Base | Limit | WP? | RP? + ------------------------------------------------------------ + PR0 (74) | 00000000 | 00000000 | 00000000 | 0 | 0 + PR1 (78) | 8BFF0B40 | 00B40000 | 00BFFFFF | 1 | 0 + PR2 (7C) | 8B100B10 | 00B10000 | 00B10FFF | 1 | 0 + PR3 (80) | 8ADE0AD0 | 00AD0000 | 00ADEFFF | 1 | 0 + PR4 (84) | 8AAF0800 | 00800000 | 00AAFFFF | 1 | 0 Other way to examine SPI configuration registers is to just dump SPIBAR: -``` -sudo chipsec_util mmio dump SPIBAR -``` + + sudo chipsec_util mmio dump SPIBAR + You will see SPIBAR address (0xFED1F800) and registers (for example, 00000004 is HSFS): -``` -[mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]: -+00000000: 0BFF0500 -+00000004: 0004E009 -... -``` + + [mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]: + +00000000: 0BFF0500 + +00000004: 0004E009 + ... + As you can see, the only thing we need is to unset WP bit on PR0-PR4. But that cannot be done once FLOCKDN is set to 1. @@ -239,23 +232,23 @@ FLOCKDN may only be cleared by a hardware reset, which includes S3 state. On S3 resume boot path, the chipset configuration has to be restored and it's done by executing so-called S3 Boot Scripts. You can dump these scripts by executing: -``` -sudo chipsec_util uefi s3bootscript -``` + + sudo chipsec_util uefi s3bootscript + There are many entries. Along them, you can find instructions to write to HSFS (remember, we know that SPIBAR is 0xFED1F800): -``` -Entry at offset 0x2B8F (len = 0x17, header len = 0x0): -Data: -02 00 17 02 00 00 00 01 00 00 00 04 f8 d1 fe 00 | -00 00 00 09 e0 04 00 | -Decoded: - Opcode : S3_BOOTSCRIPT_MEM_WRITE (0x0002) - Width : 0x02 (4 bytes) - Address: 0xFED1F804 - Count : 0x1 - Values : 0x0004E009 -``` + + Entry at offset 0x2B8F (len = 0x17, header len = 0x0): + Data: + 02 00 17 02 00 00 00 01 00 00 00 04 f8 d1 fe 00 | + 00 00 00 09 e0 04 00 | + Decoded: + Opcode : S3_BOOTSCRIPT_MEM_WRITE (0x0002) + Width : 0x02 (4 bytes) + Address: 0xFED1F804 + Count : 0x1 + Values : 0x0004E009 + These scripts are stored in memory. The vulnerability is that we can overwrite this memory, change these instructions and they will be executed on S3 resume. Once we patch that instruction to not set FLOCKDN @@ -268,14 +261,13 @@ in case something goes wrong, you'll be able to flash it back externally. The `me` region is locked, so an attempt to create a full dump will fail. But you can back up the `bios`: -``` -sudo flashrom -p internal -r bios_backup.rom --ifd -i bios -``` + + sudo flashrom -p internal -r bios_backup.rom --ifd -i bios If you will ever need to flash it back, use `--ifd -i bios` as well: -``` -sudo flashrom -p -w bios_backup.rom --ifd -i bios -``` + + sudo flashrom -p -w bios_backup.rom --ifd -i bios + **Caution:** if you will omit `--ifd -i bios` for flashing, you will brick your machine, because your backup has `FF`s in place of `fd` and `me` regions. Flash only `bios` region! @@ -284,83 +276,80 @@ brick your machine, because your backup has `FF`s in place of `fd` and The original boot script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so let's write 0x6009 instead: -``` -sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2 -``` + + sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2 + You will get a lot of output and in the end you should see something like this: -``` -[*] Modifying S3 boot script entry at address 0x00000000DAF49B8F.. -[mem] 0x00000000DAF49B8F -[*] Original entry: - 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | - 0 0 0 9 e0 4 0 | -[mem] buffer len = 0x17 to PA = 0x00000000DAF49B8F - 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | - 0 0 0 9 60 0 0 | ` -[mem] 0x00000000DAF49B8F -[*] Modified entry: - 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | - 0 0 0 9 60 0 0 | ` -[*] After sleep/resume, check the value of register 0xFED1F804 is 0x6009 -[+] PASSED: The script has been modified. Go to sleep.. -``` -Now go to S3, then resume and check FLOCKDN. It should be 0: -``` -sudo chipsec_main -m chipsec.modules.common.spi_lock -``` -``` -... -[x][ ======================================================================= -[x][ Module: SPI Flash Controller Configuration Locks -[x][ ======================================================================= -[*] HSFS = 0x6008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) - [00] FDONE = 0 << Flash Cycle Done - [01] FCERR = 0 << Flash Cycle Error - [02] AEL = 0 << Access Error Log - [03] BERASE = 1 << Block/Sector Erase Size - [05] SCIP = 0 << SPI cycle in progress - [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status - [14] FDV = 1 << Flash Descriptor Valid - [15] FLOCKDN = 0 << Flash Configuration Lock-Down -[-] SPI Flash Controller configuration is not locked -[-] FAILED: SPI Flash Controller not locked correctly. -... -``` -Remove WP from protected ranges: -``` -sudo chipsec_util mmio write SPIBAR 0x74 0x4 0xAAF0800 -sudo chipsec_util mmio write SPIBAR 0x78 0x4 0xADE0AD0 -sudo chipsec_util mmio write SPIBAR 0x7C 0x4 0xB100B10 -sudo chipsec_util mmio write SPIBAR 0x80 0x4 0xBFF0B40 -``` -Verify that it worked: -``` -sudo chipsec_main -m common.bios_wp -``` -``` -[x][ ======================================================================= -[x][ Module: BIOS Region Write Protection -[x][ ======================================================================= -[*] BC = 0x 9 << BIOS Control (b:d.f 00:31.0 + 0xDC) - [00] BIOSWE = 1 << BIOS Write Enable - [01] BLE = 0 << BIOS Lock Enable - [02] SRC = 2 << SPI Read Configuration - [04] TSS = 0 << Top Swap Status - [05] SMM_BWP = 0 << SMM BIOS Write Protection -[-] BIOS region write protection is disabled! -[*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF -SPI Protected Ranges ------------------------------------------------------------- -PRx (offset) | Value | Base | Limit | WP? | RP? ------------------------------------------------------------- -PR0 (74) | 0AAF0800 | 00800000 | 00AAF000 | 0 | 0 -PR1 (78) | 0ADE0AD0 | 00AD0000 | 00ADE000 | 0 | 0 -PR2 (7C) | 0B100B10 | 00B10000 | 00B10000 | 0 | 0 -PR3 (80) | 0BFF0B40 | 00B40000 | 00BFF000 | 0 | 0 -PR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0 -``` + [*] Modifying S3 boot script entry at address 0x00000000DAF49B8F.. + [mem] 0x00000000DAF49B8F + [*] Original entry: + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 e0 4 0 | + [mem] buffer len = 0x17 to PA = 0x00000000DAF49B8F + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 60 0 0 | ` + [mem] 0x00000000DAF49B8F + [*] Modified entry: + 2 0 17 2 0 0 0 1 0 0 0 4 f8 d1 fe 0 | + 0 0 0 9 60 0 0 | ` + [*] After sleep/resume, check the value of register 0xFED1F804 is 0x6009 + [+] PASSED: The script has been modified. Go to sleep.. + +Now go to S3, then resume and check FLOCKDN. It should be 0: + + sudo chipsec_main -m chipsec.modules.common.spi_lock + + ... + [x][ ======================================================================= + [x][ Module: SPI Flash Controller Configuration Locks + [x][ ======================================================================= + [*] HSFS = 0x6008 << Hardware Sequencing Flash Status Register (SPIBAR + 0x4) + [00] FDONE = 0 << Flash Cycle Done + [01] FCERR = 0 << Flash Cycle Error + [02] AEL = 0 << Access Error Log + [03] BERASE = 1 << Block/Sector Erase Size + [05] SCIP = 0 << SPI cycle in progress + [13] FDOPSS = 1 << Flash Descriptor Override Pin-Strap Status + [14] FDV = 1 << Flash Descriptor Valid + [15] FLOCKDN = 0 << Flash Configuration Lock-Down + [-] SPI Flash Controller configuration is not locked + [-] FAILED: SPI Flash Controller not locked correctly. + ... + +Remove WP from protected ranges: + + sudo chipsec_util mmio write SPIBAR 0x74 0x4 0xAAF0800 + sudo chipsec_util mmio write SPIBAR 0x78 0x4 0xADE0AD0 + sudo chipsec_util mmio write SPIBAR 0x7C 0x4 0xB100B10 + sudo chipsec_util mmio write SPIBAR 0x80 0x4 0xBFF0B40 + +Verify that it worked: + + sudo chipsec_main -m common.bios_wp + + [x][ ======================================================================= + [x][ Module: BIOS Region Write Protection + [x][ ======================================================================= + [*] BC = 0x 9 << BIOS Control (b:d.f 00:31.0 + 0xDC) + [00] BIOSWE = 1 << BIOS Write Enable + [01] BLE = 0 << BIOS Lock Enable + [02] SRC = 2 << SPI Read Configuration + [04] TSS = 0 << Top Swap Status + [05] SMM_BWP = 0 << SMM BIOS Write Protection + [-] BIOS region write protection is disabled! + + [*] BIOS Region: Base = 0x00500000, Limit = 0x00BFFFFF + SPI Protected Ranges + ------------------------------------------------------------ + PRx (offset) | Value | Base | Limit | WP? | RP? + ------------------------------------------------------------ + PR0 (74) | 0AAF0800 | 00800000 | 00AAF000 | 0 | 0 + PR1 (78) | 0ADE0AD0 | 00AD0000 | 00ADE000 | 0 | 0 + PR2 (7C) | 0B100B10 | 00B10000 | 00B10000 | 0 | 0 + PR3 (80) | 0BFF0B40 | 00B40000 | 00BFF000 | 0 | 0 + PR4 (84) | 00000000 | 00000000 | 00000000 | 0 | 0 Bingo! From 75372e5a7541a897b7d41d062957d045a1021ff9 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Wed, 5 Feb 2020 16:42:48 +0100 Subject: [PATCH 105/151] Documentation: Mark up register names as code Change-Id: I708385bca8edcd74b0d4c0a3ecc181b6ccd30c2b Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38721 Reviewed-by: Peter Lemenkov Tested-by: build bot (Jenkins) --- .../mainboard/lenovo/ivb_internal_flashing.md | 30 +++++++++---------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/Documentation/mainboard/lenovo/ivb_internal_flashing.md b/Documentation/mainboard/lenovo/ivb_internal_flashing.md index 355cf98448..e6b597b284 100644 --- a/Documentation/mainboard/lenovo/ivb_internal_flashing.md +++ b/Documentation/mainboard/lenovo/ivb_internal_flashing.md @@ -5,9 +5,9 @@ Old versions of stock BIOS for these models have several security issues. In order to flash coreboot internally, two of them are of interest. -**First** is the fact the SMM_BWP and BLE are not enabled in BIOS +**First** is the fact the `SMM_BWP` and `BLE` are not enabled in BIOS versions released before 2014. We have tested many versions on T430 and -X230 and found out that SMM_BWP=1 only since the update, the changelog +X230 and found out that `SMM_BWP=1` only since the update, the changelog of which contains following line: > (New) Improved the UEFI BIOS security feature. @@ -159,14 +159,14 @@ chip: Configuration Registers. When set to 1, PR0-PR4 registers cannot be written. Once set to 1, cannot be changed anymore. -To be able to flash, we need SMM_BWP=0, BIOSWE=1, BLE=0, FLOCKDN=0 or +To be able to flash, we need `SMM_BWP=0`, `BIOSWE=1`, `BLE=0`, `FLOCKDN=0` or SPI protected ranges (PRx) to have a WP bit set to 0. -Let's see what we have. Examine HSFS register: +Let's see what we have. Examine `HSFS` register: sudo chipsec_main -m chipsec.modules.common.spi_lock -You should see that FLOCKDN=1: +You should see that `FLOCKDN=1`: [x][ ======================================================================= [x][ Module: SPI Flash Controller Configuration Locks @@ -181,11 +181,11 @@ You should see that FLOCKDN=1: [14] FDV = 1 << Flash Descriptor Valid [15] FLOCKDN = 1 << Flash Configuration Lock-Down -Then check BIOS_CNTL and PR0-PR4: +Then check `BIOS_CNTL` and PR0-PR4: sudo chipsec_main -m common.bios_wp -Good news: on old BIOS versions, SMM_BWP=0 and BLE=0. +Good news: on old BIOS versions, `SMM_BWP=0` and `BLE=0`. Bad news: there are 4 write protected SPI ranges: @@ -215,8 +215,8 @@ Other way to examine SPI configuration registers is to just dump SPIBAR: sudo chipsec_util mmio dump SPIBAR -You will see SPIBAR address (0xFED1F800) and registers (for example, -00000004 is HSFS): +You will see `SPIBAR` address (0xFED1F800) and registers (for example, +`00000004` is `HSFS`): [mmio] MMIO register range [0x00000000FED1F800:0x00000000FED1F800+00000200]: +00000000: 0BFF0500 @@ -224,11 +224,11 @@ You will see SPIBAR address (0xFED1F800) and registers (for example, ... As you can see, the only thing we need is to unset WP bit on PR0-PR4. -But that cannot be done once FLOCKDN is set to 1. +But that cannot be done once `FLOCKDN` is set to 1. Now the fun part! -FLOCKDN may only be cleared by a hardware reset, which includes S3 +`FLOCKDN` may only be cleared by a hardware reset, which includes S3 state. On S3 resume boot path, the chipset configuration has to be restored and it's done by executing so-called S3 Boot Scripts. You can dump these scripts by executing: @@ -236,7 +236,7 @@ dump these scripts by executing: sudo chipsec_util uefi s3bootscript There are many entries. Along them, you can find instructions to write -to HSFS (remember, we know that SPIBAR is 0xFED1F800): +to `HSFS` (remember, we know that `SPIBAR` is 0xFED1F800): Entry at offset 0x2B8F (len = 0x17, header len = 0x0): Data: @@ -251,7 +251,7 @@ to HSFS (remember, we know that SPIBAR is 0xFED1F800): These scripts are stored in memory. The vulnerability is that we can overwrite this memory, change these instructions and they will be -executed on S3 resume. Once we patch that instruction to not set FLOCKDN +executed on S3 resume. Once we patch that instruction to not set `FLOCKDN` bit, we will be able to write to PR0-PR4 registers. ## Creating a backup @@ -274,7 +274,7 @@ brick your machine, because your backup has `FF`s in place of `fd` and ## Removing protections (practice) -The original boot script writes 0xE009 to HSFS. FLOCKDN is 15th bit, so +The original boot script writes 0xE009 to `HSFS`. `FLOCKDN` is 15th bit, so let's write 0x6009 instead: sudo chipsec_main -m tools.uefi.s3script_modify -a replace_op,mmio_wr,0xFED1F804,0x6009,0x2 @@ -297,7 +297,7 @@ like this: [*] After sleep/resume, check the value of register 0xFED1F804 is 0x6009 [+] PASSED: The script has been modified. Go to sleep.. -Now go to S3, then resume and check FLOCKDN. It should be 0: +Now go to S3, then resume and check `FLOCKDN`. It should be 0: sudo chipsec_main -m chipsec.modules.common.spi_lock From f8a13d5a2292c08515e4970d3f9bf5a9d0bee7d1 Mon Sep 17 00:00:00 2001 From: Chris Morgan Date: Wed, 5 Feb 2020 12:38:48 -0600 Subject: [PATCH 106/151] mb/lenovo/t440p: Enable dGPU on Lenovo T440P Enable the dGPU on the Lenovo T440P. It uses the same code (roughly) of the T430S. By default, it is set to be disabled however it can be enabled via the nvram option enable_dual_graphics. Removed hybrid graphics options too as they are not valid for the T440p. Tested on a T440P with Ubuntu 18.04.4 with Kernel 5.3.0-29 (successful). Tested on same machine with Windows 10 1909 (machine check exception bluescreen). Change-Id: Idf8c2c0d1ae34bda8736448d3e350396e3cf7a93 Signed-off-by: Chris Morgan Reviewed-on: https://review.coreboot.org/c/coreboot/+/38723 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/lenovo/t440p/cmos.default | 1 + src/mainboard/lenovo/t440p/cmos.layout | 5 +---- src/mainboard/lenovo/t440p/romstage.c | 20 ++++++++++++++++++++ 3 files changed, 22 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/t440p/cmos.default b/src/mainboard/lenovo/t440p/cmos.default index 0949e7b13c..bb8626d48b 100644 --- a/src/mainboard/lenovo/t440p/cmos.default +++ b/src/mainboard/lenovo/t440p/cmos.default @@ -10,4 +10,5 @@ f1_to_f12_as_primary=Enable sticky_fn=Disable trackpoint=Enable backlight=Keyboard +enable_dual_graphics=Disable usb_always_on=Disable diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index f65933a715..9c09104d55 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -69,7 +69,7 @@ entries 424 1 e 1 f1_to_f12_as_primary # coreboot config options: northbridge -#435 2 e 12 hybrid_graphics_mode +435 1 e 1 enable_dual_graphics #437 3 r 0 unused 440 8 h 0 volume @@ -108,9 +108,6 @@ enumerations 10 1 Keyboard #10 2 Thinklight only 10 3 None -#12 0 Integrated Only -#12 1 Discrete Only -#12 2 Dual Graphics 13 0 Disable 13 1 AC and battery 13 2 AC only diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index c8c630bfde..283a52b460 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -22,6 +22,9 @@ #include #include #include +#include +#include +#include static const struct rcba_config_instruction rcba_config[] = { RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), @@ -100,4 +103,21 @@ void mainboard_romstage_entry(void) }; romstage_common(&romstage_params); + + u8 enable_peg; + if (get_option(&enable_peg, "enable_dual_graphics") != CB_SUCCESS) + enable_peg = 0; + + bool power_en = pmh7_dgpu_power_state(); + + if (enable_peg != power_en) + pmh7_dgpu_power_enable(!power_en); + + if (!enable_peg) { + // Hide disabled dGPU device + u32 reg32 = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + reg32 &= ~DEVEN_D1F0EN; + + pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32); + } } From 3fde8c997713488b79639bf0345ceb9ccb9dc923 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 4 Feb 2020 23:03:26 -0700 Subject: [PATCH 107/151] mb/google/dedede: Log mainboard events to elog BUG=b:148410914 TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I7dffa5c021787dca75786ead42164bd29ba56828 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38724 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- src/mainboard/google/dedede/smihandler.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/dedede/smihandler.c b/src/mainboard/google/dedede/smihandler.c index 2c2230f4e4..4e3c830384 100644 --- a/src/mainboard/google/dedede/smihandler.c +++ b/src/mainboard/google/dedede/smihandler.c @@ -8,7 +8,9 @@ #include #include +#include #include +#include #include #include @@ -35,3 +37,8 @@ int mainboard_smi_apmc(u8 apmc) MAINBOARD_EC_SMI_EVENTS); return 0; } + +void elog_gsmi_cb_mainboard_log_wake_source(void) +{ + google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS | MAINBOARD_EC_S0IX_WAKE_EVENTS); +} From bfe0948f7d2f3df3c0f72e3e688527f0440c6591 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 7 Feb 2020 21:29:30 +0800 Subject: [PATCH 108/151] mb/google/drallion: Tuning WWAN power sequence Change GPP_C10 from pltrst to deep to meet the warmboot power sequence. BUG=b:146935222 TEST=measure WWAN power sequence is meet spec Signed-off-by: Eric Lai Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- src/mainboard/google/drallion/variants/drallion/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 1c864caff7..85de17346a 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -88,7 +88,7 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_NC(GPP_C3, NONE), /* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), -/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_NC(GPP_C12, NONE), /* UART1_TXD */ PAD_NC(GPP_C13, NONE), From 7bac50e82428b3e94c08787a366d8230ec16c046 Mon Sep 17 00:00:00 2001 From: Ian Feng Date: Thu, 6 Feb 2020 18:42:31 +0800 Subject: [PATCH 109/151] mb/google/drallion: Add new SPD files for drallion Add new SPD files for drallion: 1. Hynix H5AN8G6NDJR-XNC 2. Samung K4AAG165WA-BCWE 3. Samung K4A8G165WC-BCWE BUG=b:148642500 TEST=Compile successfully and check SPD info in cbmem log. Signed-off-by: Ian Feng Change-Id: I0e9b444f6f1e0c7e1da197fbd2e70e686568ab47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38731 Reviewed-by: EricR Lai Reviewed-by: Mathew King Reviewed-by: Bora Guvendik Tested-by: build bot (Jenkins) --- .../spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex | 32 +++++++++++++++++++ .../spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex | 32 +++++++++++++++++++ .../spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex | 32 +++++++++++++++++++ .../drallion/variants/drallion/Makefile.inc | 3 ++ .../drallion/variants/drallion/memory.c | 4 +-- 5 files changed, 101 insertions(+), 2 deletions(-) create mode 100644 src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex create mode 100644 src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex create mode 100644 src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex diff --git a/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex new file mode 100644 index 0000000000..dec132b1d7 --- /dev/null +++ b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NDJR-XNC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B4 00 00 00 00 E7 00 75 20 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 +36 44 4A 52 36 4E 2D 58 4E 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex new file mode 100644 index 0000000000..2440c75773 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCWE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 02 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 14 98 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 38 47 31 36 +35 57 43 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex new file mode 100644 index 0000000000..8c98da1af5 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WA-BCWE.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 E8 F5 +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4B 34 41 41 47 31 36 +35 57 41 2D 42 43 57 45 20 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 954c9d59cf..b584a91a27 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -23,6 +23,9 @@ SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011 SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011 SPD_SOURCES += micron_dimm_MT40A1G16KD-062EE # 0b11010 +SPD_SOURCES += hynix_dimm_H5AN8G6NDJR-XNC # 0b01100 +SPD_SOURCES += samsung_dimm_K4AAG165WA-BCWE # 0b00000 +SPD_SOURCES += samsung_dimm_K4A8G165WC-BCWE # 0b00100 bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 9c4135dfdc..a56fb53a14 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -21,8 +21,8 @@ /* Use spd_index array to save mem_id */ static const int spd_index[32] = { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, + 10, 0, 0, 0, 11, 0, 0, 0, + 0, 0, 0, 0, 9, 0, 0, 0, 0, 4, 3, 6, 1, 0, 0, 0, 0, 5, 8, 7, 2, 0, 0, 0 }; From f978191b64bf0b4a512eb2872e044f1e030b7c8f Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 28 Jan 2020 18:43:28 -0800 Subject: [PATCH 110/151] mb/google/volteer: add volteer mainboard initial support Created a new Google baseboard named volteer from scratch. BUG=b:142961277 BRANCH=master TEST="emerge-volteer coreboot" compiles successfully. Change-Id: I03a13f3df4e819ab9cf63ad69867c807d2a1b651 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/38620 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/Kconfig | 71 +++ src/mainboard/google/volteer/Kconfig.name | 5 + src/mainboard/google/volteer/Makefile.inc | 28 ++ src/mainboard/google/volteer/board_info.txt | 6 + src/mainboard/google/volteer/bootblock.c | 19 + src/mainboard/google/volteer/chromeos.c | 41 ++ src/mainboard/google/volteer/chromeos.fmd | 47 ++ src/mainboard/google/volteer/dsdt.asl | 53 ++ src/mainboard/google/volteer/ec.c | 25 + src/mainboard/google/volteer/mainboard.c | 79 +++ src/mainboard/google/volteer/smihandler.c | 30 ++ src/mainboard/google/volteer/spd/Makefile.inc | 27 + .../spd/samsung-K4U6E3S4AA-MGCL.spd.hex | 32 ++ .../volteer/variants/baseboard/Makefile.inc | 13 + .../volteer/variants/baseboard/devicetree.cb | 346 +++++++++++++ .../google/volteer/variants/baseboard/gpio.c | 470 ++++++++++++++++++ .../variants/baseboard/include/baseboard/ec.h | 75 +++ .../baseboard/include/baseboard/gpio.h | 39 ++ .../baseboard/include/baseboard/variants.h | 28 ++ .../volteer/variants/volteer/Makefile.inc | 10 + .../volteer/include/variant/acpi/dptf.asl | 9 + .../variants/volteer/include/variant/ec.h | 14 + .../variants/volteer/include/variant/gpio.h | 14 + 23 files changed, 1481 insertions(+) create mode 100644 src/mainboard/google/volteer/Kconfig create mode 100644 src/mainboard/google/volteer/Kconfig.name create mode 100644 src/mainboard/google/volteer/Makefile.inc create mode 100644 src/mainboard/google/volteer/board_info.txt create mode 100644 src/mainboard/google/volteer/bootblock.c create mode 100644 src/mainboard/google/volteer/chromeos.c create mode 100644 src/mainboard/google/volteer/chromeos.fmd create mode 100644 src/mainboard/google/volteer/dsdt.asl create mode 100644 src/mainboard/google/volteer/ec.c create mode 100644 src/mainboard/google/volteer/mainboard.c create mode 100644 src/mainboard/google/volteer/smihandler.c create mode 100644 src/mainboard/google/volteer/spd/Makefile.inc create mode 100644 src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex create mode 100644 src/mainboard/google/volteer/variants/baseboard/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/baseboard/devicetree.cb create mode 100644 src/mainboard/google/volteer/variants/baseboard/gpio.c create mode 100644 src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h create mode 100644 src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h create mode 100644 src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h create mode 100644 src/mainboard/google/volteer/variants/volteer/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl create mode 100644 src/mainboard/google/volteer/variants/volteer/include/variant/ec.h create mode 100644 src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig new file mode 100644 index 0000000000..572a10020e --- /dev/null +++ b/src/mainboard/google/volteer/Kconfig @@ -0,0 +1,71 @@ +config BOARD_GOOGLE_BASEBOARD_VOLTEER + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_GENERIC + select DRIVERS_SPI_ACPI + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_LPC + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_SPI_TPM_CR50 + select MAINBOARD_HAS_TPM2 + select SOC_INTEL_TIGERLAKE + +if BOARD_GOOGLE_BASEBOARD_VOLTEER + +config CHROMEOS + bool + default y + select EC_GOOGLE_CHROMEEC_SWITCHES + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY + select HAS_RECOVERY_MRC_CACHE + select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN + select VBOOT_LID_SWITCH + +config DIMM_SPD_SIZE + int + default 512 + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_VOLTEER + +config DRIVER_TPM_SPI_BUS + default 0x1 + +config MAINBOARD_DIR + string + default "google/volteer" + +config MAINBOARD_FAMILY + string + default "Google_Volteer" if BOARD_GOOGLE_VOLTEER + +config MAINBOARD_PART_NUMBER + string + default "Volteer" if BOARD_GOOGLE_VOLTEER + +config MAX_CPUS + int + default 8 + +config TPM_TIS_ACPI_INTERRUPT + int + default 21 # GPE0_DW0_21 (GPP_C21) + +config VARIANT_DIR + string + default "volteer" if BOARD_GOOGLE_VOLTEER + +endif # BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Kconfig.name b/src/mainboard/google/volteer/Kconfig.name new file mode 100644 index 0000000000..a3fac9c74c --- /dev/null +++ b/src/mainboard/google/volteer/Kconfig.name @@ -0,0 +1,5 @@ +comment "Volteer" + +config BOARD_GOOGLE_VOLTEER + bool "-> Volteer" + select BOARD_GOOGLE_BASEBOARD_VOLTEER diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc new file mode 100644 index 0000000000..6b5c065e1e --- /dev/null +++ b/src/mainboard/google/volteer/Makefile.inc @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +bootblock-y += bootblock.c + +romstage-$(CONFIG_CHROMEOS) += chromeos.c + +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += ec.c +ramstage-y += mainboard.c + +smm-y += smihandler.c + +verstage-$(CONFIG_CHROMEOS) += chromeos.c + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR)) +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += spd diff --git a/src/mainboard/google/volteer/board_info.txt b/src/mainboard/google/volteer/board_info.txt new file mode 100644 index 0000000000..c41a04b66e --- /dev/null +++ b/src/mainboard/google/volteer/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Volteer Tigerlake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/volteer/bootblock.c b/src/mainboard/google/volteer/bootblock.c new file mode 100644 index 0000000000..8685fa776a --- /dev/null +++ b/src/mainboard/google/volteer/bootblock.c @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +void bootblock_mainboard_init(void) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_early_gpio_table(&num); + gpio_configure_pads(pads, num); +} diff --git a/src/mainboard/google/volteer/chromeos.c b/src/mainboard/google/volteer/chromeos.c new file mode 100644 index 0000000000..eca7e20652 --- /dev/null +++ b/src/mainboard/google/volteer/chromeos.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio chromeos_gpios[] = { + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, + {-1, ACTIVE_HIGH, 0, "power"}, + {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, + {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), + "EC in RW"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); +} + +int get_write_protect_state(void) +{ + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); +} + +void mainboard_chromeos_acpi_generate(void) +{ + const struct cros_gpio *gpios; + size_t num; + + gpios = variant_cros_gpios(&num); + chromeos_acpi_gpio_generate(gpios, num); +} diff --git a/src/mainboard/google/volteer/chromeos.fmd b/src/mainboard/google/volteer/chromeos.fmd new file mode 100644 index 0000000000..60ea3ded64 --- /dev/null +++ b/src/mainboard/google/volteer/chromeos.fmd @@ -0,0 +1,47 @@ +FLASH@0xfe000000 0x2000000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x4ff000 + } + SI_BIOS@0x500000 0x1b00000 { + # Place RW_LEGACY at the start of BIOS region such that the rest + # of BIOS regions start at 16MiB boundary. Since this is a 32MiB + # SPI flash only the top 16MiB actually gets memory mapped. + RW_LEGACY(CBFS)@0x0 0xf00000 + RW_SECTION_A@0xf00000 0x3e0000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x3cffc0 + RW_FWID_A@0x3dffc0 0x40 + } + RW_SECTION_B@0x12e0000 0x3e0000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x3cffc0 + RW_FWID_B@0x3dffc0 0x40 + } + RW_MISC@0x16c0000 0x40000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x20000 + } + RW_ELOG(PRESERVE)@0x30000 0x4000 + RW_SHARED@0x34000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x38000 0x2000 + RW_NVRAM(PRESERVE)@0x3a000 0x6000 + } + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x1700000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } + } +} diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl new file mode 100644 index 0000000000..489d2f0222 --- /dev/null +++ b/src/mainboard/google/volteer/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include "variant/ec.h" +#include "variant/gpio.h" + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chrome OS specific + #include + + // Chrome OS Embedded Controller + Scope (\_SB.PCI0.LPCB) + { + // ACPI code for EC SuperIO functions + #include + // ACPI code for EC functions + #include + } + + // Chipset specific sleep states + #include +} diff --git a/src/mainboard/google/volteer/ec.c b/src/mainboard/google/volteer/ec.c new file mode 100644 index 0000000000..568738dd0c --- /dev/null +++ b/src/mainboard/google/volteer/ec.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +void mainboard_ec_init(void) +{ + static const struct google_chromeec_event_info info = { + .log_events = MAINBOARD_EC_LOG_EVENTS, + .sci_events = MAINBOARD_EC_SCI_EVENTS, + .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS, + .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS, + .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS, + }; + + google_chromeec_events_init(&info, acpi_is_wakeup_s3()); +} diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c new file mode 100644 index 0000000000..51cbc40cfc --- /dev/null +++ b/src/mainboard/google/volteer/mainboard.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SKU_UNKNOWN 0xFFFFFFFF +#define SKU_MAX 0x7FFFFFFF + +static uint32_t get_board_sku(void) +{ + static uint32_t sku_id = SKU_UNKNOWN; + + if (sku_id != SKU_UNKNOWN) + return sku_id; + + if (google_chromeec_cbi_get_sku_id(&sku_id)) + sku_id = SKU_UNKNOWN; + + return sku_id; +} + +const char *smbios_system_sku(void) +{ + static char sku_str[14]; /* sku{0..2147483647} */ + uint32_t sku_id = get_board_sku(); + + if ((sku_id == SKU_UNKNOWN) || (sku_id > SKU_MAX)) { + printk(BIOS_ERR, "%s: Unexpected SKU ID %u\n", + __func__, sku_id); + return ""; + } + + snprintf(sku_str, sizeof(sku_str), "sku%u", sku_id); + + return sku_str; +} + +static void mainboard_init(struct device *dev) +{ + mainboard_ec_init(); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +static void mainboard_chip_init(void *chip_info) +{ + const struct pad_config *base_pads; + const struct pad_config *override_pads; + size_t base_num, override_num; + + base_pads = variant_base_gpio_table(&base_num); + override_pads = variant_override_gpio_table(&override_num); + + gpio_configure_pads_with_override(base_pads, base_num, + override_pads, override_num); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_chip_init, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/volteer/smihandler.c b/src/mainboard/google/volteer/smihandler.c new file mode 100644 index 0000000000..b44c2b57ea --- /dev/null +++ b/src/mainboard/google/volteer/smihandler.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} diff --git a/src/mainboard/google/volteer/spd/Makefile.inc b/src/mainboard/google/volteer/spd/Makefile.inc new file mode 100644 index 0000000000..c4b9e99afc --- /dev/null +++ b/src/mainboard/google/volteer/spd/Makefile.inc @@ -0,0 +1,27 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +SPD_BIN = $(obj)/spd.bin + +ifeq ($(SPD_SOURCES),) + SPD_DEPS := $(error SPD_SOURCES is not set. Variant must provide this) +else + SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) +endif + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex new file mode 100644 index 0000000000..e1f27fba56 --- /dev/null +++ b/src/mainboard/google/volteer/spd/samsung-K4U6E3S4AA-MGCL.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 19 95 08 00 40 00 00 02 21 00 00 +48 00 04 FF 92 55 00 00 8C 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 7F E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc new file mode 100644 index 0000000000..30f2b4605a --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc @@ -0,0 +1,13 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +bootblock-y += gpio.c + +ramstage-y += gpio.c + +smm-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..b9ed424158 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -0,0 +1,346 @@ +chip soc/intel/tigerlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_C" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + register "SaGv" = "SaGv_Disabled" + register "SmbusEnable" = "0" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Cl + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Co + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 Camera + + # Enable Pch iSCLK + register "pch_isclk" = "1" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + + # Enable NVMe PCIE 9 using clk 0 + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcUsage[0]" = "8" + register "PcieClkSrcClkReq[0]" = "0" + + # Enable SD Card PCIE 8 using clk 3 + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcUsage[3]" = "7" + register "PcieClkSrcClkReq[3]" = "3" + + # Enable WLAN PCIE 7 using clk 1 + register "PcieRpEnable[6]" = "1" + register "PcieClkSrcUsage[1]" = "6" + register "PcieClkSrcClkReq[1]" = "1" + + # Enable WWAN PCIE 6 using clk 2 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + + # Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality + register "PcieClkSrcUsage[4]" = "0xFF" + register "PcieClkSrcUsage[5]" = "0xFF" + register "PcieClkSrcUsage[6]" = "0xFF" + + # Enable SATA + register "SataEnable" = "1" + register "SataMode" = "0" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "0" + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[0]" = "0" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # DP port + register "DdiPortAConfig" = "1" # eDP + register "DdiPortBConfig" = "0" + + register "DdiPortAHpd" = "1" + register "DdiPortBHpd" = "1" + register "DdiPortCHpd" = "0" + register "DdiPort1Hpd" = "1" + register "DdiPort2Hpd" = "1" + register "DdiPort3Hpd" = "0" + register "DdiPort4Hpd" = "0" + + register "DdiPortADdc" = "0" + register "DdiPortBDdc" = "1" + register "DdiPortCDdc" = "0" + register "DdiPort1Ddc" = "0" + register "DdiPort2Ddc" = "0" + register "DdiPort3Ddc" = "0" + register "DdiPort4Ddc" = "0" + + # Disable PM to allow for shorter irq pulses + register "gpio_override_pm" = "1" + register "gpio_pm[0]" = "0" + register "gpio_pm[1]" = "0" + register "gpio_pm[2]" = "0" + register "gpio_pm[3]" = "0" + register "gpio_pm[4]" = "0" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable S0ix + register "s0ix_enable" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | Fingerprint MCU + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + #From EDS(575683) + device pci 00.0 on end # Host Bridge 0x9A14:U/0x9A12:Y + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF 0x9A03 + device pci 05.0 off end # IPU 0x9A19 + device pci 06.0 off end # PEG60 0x9A09 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 on end # TBT_PCIe2 0x9A27 + device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 08.0 on end # GNA 0x9A11 + device pci 09.0 off end # NPK 0x9A33 + device pci 0a.0 off end # Crash-log SRAM 0x9A0D + device pci 0d.0 on end # USB xHCI 0x9A13 + device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 + device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.3 off end # TBT DMA1 0x9A1D + device pci 0e.0 off end # VMD 0x9A0B + + # From PCH EDS(576591) + device pci 10.0 on end # I2C6 0xA0D8 + device pci 10.1 off end # I2C7 0xA0D9 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.6 off end # THC0 0xA0D0 + device pci 10.7 off end # THC1 0xA0D1 + + device pci 11.0 off end # UART3 0xA0DA + device pci 11.1 off end # UART4 0xA0DB + device pci 11.2 off end # UART5 0xA0DC + device pci 11.3 off end # UART6 0xA0DD + + device pci 12.0 off end # SensorHUB 0xA0FC + device pci 12.6 off end # GSPI2 0x34FB + + device pci 13.0 off end # GSPI3 0xA0FD + device pci 13.1 off end # GSPI4 0xA0FE + device pci 13.2 off end # GSPI5 0xA0DE + device pci 13.3 off end # GSPI6 0xA0DF + + device pci 14.0 on end # USB3.1 xHCI 0xA0ED + device pci 14.1 off end # USB3.1 xDCI 0xA0EE + device pci 14.2 on end # Shared RAM 0xA0EF + device pci 14.3 on end # CNVi: WiFi 0xA0F0 - A0F3 + + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq" = "ACPI_IRQ_EDGE_HIGH(GPP_F8_IRQ)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end # I2C #0 0xA0E8 + device pci 15.1 on end # I2C1 0xA0E9 + device pci 15.2 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR0 Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "0" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C2 0xA0EA + device pci 15.3 on end # I2C3 0xA0EB + + device pci 16.0 on end # HECI1 0xA0E0 + device pci 16.1 off end # HECI2 0xA0E1 + device pci 16.2 off end # CSME 0xA0E2 + device pci 16.3 off end # CSME 0xA0E3 + device pci 16.4 off end # HECI3 0xA0E4 + device pci 16.5 off end # HECI4 0xA0E5 + + device pci 17.0 on end # SATA 0xA0D3 + + device pci 19.0 on end # I2C4 0xA0C5 + device pci 19.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E15_IRQ)" + register "probed" = "1" + device i2c 15 on end + end + end # I2C5 0xA0C6 + device pci 19.2 off end # UART2 0xA0C7 + + device pci 1c.0 on end # RP1 0xA0B8 + device pci 1c.1 off end # RP2 0xA0B9 + device pci 1c.2 off end # RP3 0xA0BA + device pci 1c.3 off end # RP4 0xA0BB + device pci 1c.4 off end # RP5 0xA0BC + device pci 1c.5 on end # WWAN RP6 0xA0BD + device pci 1c.6 on end # RP7 0xA0BE + device pci 1c.7 on end # SD Card RP8 0xA0BF + + device pci 1d.0 on end # RP9 0xA0B0 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.3 off end # RP12 0xA0B3 + device pci 1d.4 off end # RP13 0xA0B4 + device pci 1d.5 off end # RP14 0xA0B5 + device pci 1d.6 off end # RP15 0xA0B6 + device pci 1d.7 off end # RP16 0xA0B7 + + device pci 1e.0 on end # UART0 0xA0A8 + device pci 1e.1 off end # UART1 0xA0A9 + device pci 1e.2 on + chip drivers/spi/acpi + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "compat_string" = ""google,cr50"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C21_IRQ)" + device spi 0 on end + end + end # GSPI0 0xA0AA + device pci 1e.3 on end # GSPI1 0xA0AB + + device pci 1f.0 on end # eSPI 0xA080 - A09F + device pci 1f.1 off end # P2SB 0xA0A0 + device pci 1f.2 on end # PMC 0xA0A1 + device pci 1f.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A10)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end # Intel HD audio 0xA0C8-A0CF + device pci 1f.4 off end # SMBus 0xA0A3 + device pci 1f.5 on end # SPI 0xA0A4 + device pci 1f.6 off end # GbE 0x15E1/0x15E2 + device pci 1f.7 off end # TH 0xA0A6 + end +end diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c new file mode 100644 index 0000000000..2dc340f17c --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -0,0 +1,470 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +/* Leave eSPI pins untouched from default settings */ +static const struct pad_config gpio_table[] = { + /* A0 thru A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_IO_0 */ + /* A1 : ESPI_IO1 ==> ESPI_IO_1 */ + /* A2 : ESPI_IO2 ==> ESPI_IO_2 */ + /* A3 : ESPI_IO3 ==> ESPI_IO_3 */ + /* A4 : ESPI_CS# ==> ESPI_CS_L */ + /* A5 : ESPI_CLK ==> ESPI_CLK */ + /* A6 : ESPI_RESET# ==> NC(TP764) */ + /* A7 : I2S2_SCLK ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_A7, 1, DEEP), + /* A8 : I2S2_SFRM ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : I2S2_TXD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_A9, NONE, DEEP), + /* A10 : I2S2_RXD ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_A10, 1, DEEP), + /* A11 : PMC_I2C_SDA ==> SSD_PERST_ODL */ + PAD_CFG_GPO(GPP_A11, 1, DEEP), + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> USB_A0_OC_ODL */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* A15 : USB_OC2# ==> USB_A1_OC_ODL */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + /* A23 : I2S1_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + + /* B0 : CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : VRALERT# ==> VRALERT_L */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* B3 : CPU_GP2 ==> PEN_DET_ODL */ + PAD_CFG_GPI(GPP_B3, NONE, DEEP), + /* B4 : CPU_GP3 ==> NC */ + PAD_NC(GPP_B4, NONE), + /* B5 : ISH_I2C0_CVF_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), + /* B6 : ISH_I2C0_CVF_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), + /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B12 : SLP_S0# ==> SLP_S0_L */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B22 : GSPI1_MOSI ==> PCH_GSPI1_GPMCU_MOSI */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, NONE), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C1 : SMBDATA ==> NOT USED */ + PAD_NC(GPP_C1, NONE), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : SML0CLK ==> USB4_SMB_SCL */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* C4 : SML0DATA ==> USB4_SMB_SDA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1CLK ==> EC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C8 : UART0_RXD ==> UART_PCH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), + /* C9 : UART0_TXD ==> UART_PCH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> CVF_LPSS_INT_L */ + PAD_CFG_GPI(GPP_C11, NONE, DEEP), + /* C12 : UART1_RXD ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_C12, NONE, DEEP), + /* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */ + PAD_CFG_GPO(GPP_C13, 1, DEEP), + /* C14 : UART1_RTS# ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_C14, NONE, DEEP), + /* C15 : UART1_CTS# ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_C15, NONE, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_C20, NONE, PLTRST, EDGE_SINGLE), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_NC(GPP_D0, NONE), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> ISH_ALS_RGB_INT_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> FCAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D5 : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* D6 : SRCCLKREQ1# ==> WLAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* D7 : SRCCLKREQ2# ==> WWAN_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* D9 : ISH_SPI_CS# ==> PCH_GSPI2_CVF_CS_L */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF7), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF7), + /* D11 : ISH_SPI_MISO ==> PCH_GSPI2_CVF_MISO */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_D15, NONE, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> EN_FCAM_PWR */ + PAD_CFG_GPO(GPP_D17, 1, DEEP), + /* D18 : ISH_GP5 ==> FCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_D18, 1, DEEP), + /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + + /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), + /* E1 : SPI1_IO2 ==> PEN_DET_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE), + /* E2 : SPI1_IO3 ==> WLAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E2, NONE, DEEP), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */ + PAD_NC(GPP_E4, NONE), + /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */ + PAD_NC(GPP_E6, NONE), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI(GPP_E7, NONE, DEEP), + /* E8 : SPI1_CS1# ==> SLP_S0IX */ + PAD_CFG_GPO(GPP_E8, 0, DEEP), + /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* E10 : SPI1_CS# ==> USB_C0_AUXP_DC */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), + /* E12 : SPI1_MISO_IO1 ==> NOT USED */ + PAD_NC(GPP_E12, NONE), + /* E13 : SPI1_MOSI_IO0 ==> USB_C0_AUXN_DC */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E15, NONE, PLTRST, LEVEL, INVERT), + /* E16 : ISH_GP7 ==> WWAN_SIM1_DET_OD */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* E17 : THC0_SPI1_INT# ==> WWAN_PERST_L */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */ + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4), + /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4), + /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : I2S2_RXD ==> CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + /* F6 : CNV_PA_BLANKING ==> WWAN_WLAN_COEX3 */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : I2S_MCLK2_INOUT ==> HP_INT_L */ + PAD_CFG_GPI_APIC(GPP_F8, UP_20K, DEEP, EDGE_BOTH, INVERT), + /* F9 : Reserved ==> NC */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPPF10_STRAP */ + PAD_NC(GPP_F10, DN_20K), + /* F11 : THC1_SPI2_CLK ==> EN_PP3300_WWAN */ + PAD_CFG_GPO(GPP_F11, 1, DEEP), + /* F12 : GSXDOUT ==> WWAN_RST_ODL */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F14 : GSXDIN ==> SAR0_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F14, NONE, PLTRST, EDGE_SINGLE), + /* F15 : GSXSRESET# ==> RCAM_RST_L */ + PAD_CFG_GPO(GPP_F15, 1, DEEP), + /* F16 : GSXCLK ==> WWAN_DPR_SAR_ODL */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_F17, 1, DEEP), + /* F18 : THC1_SPI2_INT# ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE), + /* F19 : SRCCLKREQ6# ==> WLAN_INT_L */ + PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE), + /* F20 : EXT_PWR_GATE# ==> EXT_PWR_GATE_L */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* F21 : EXT_PWR_GATE2# ==> EXT_PWR_GATE2_L */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + /* F22 : VNN_CTRL */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* F23 : V1P05_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H4 : I2C2_SDA ==> PCH_I2C2_MISC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C2_SCL ==> PCH_I2C2_MISC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H6 : I2C3_SDA ==> PCH_I2C3_CAM_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C3_SCL ==> PCH_I2C3_CAM_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : I2C4_SDA ==> WWAN_WLAN_COEX1 */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + /* H9 : I2C4_SCL ==> WWAN_WLAN_COEX2 */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), + /* H12 : M2_SKT2_CFG0 ==> WWAN_CONFIG0 */ + PAD_CFG_GPI(GPP_H12, NONE, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> WWAN_CONFIG1 */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H14 : M2_SKT2_CFG2 # ==> RCAM_SNRPWR_EN */ + PAD_CFG_GPO(GPP_H14, 1, DEEP), + /* H15 : M2_SKT2_CFG3 # ==> WWAN_CONFIG3 */ + PAD_CFG_GPI(GPP_H15, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + /* H20 : IMGCLKOUT1 ==> EN_MIPI_RCAM_PWR */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), + /* H21 : IMGCLKOUT2 ==> CAM_MCLK1 */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* H22 : IMGCLKOUT3 ==> CAM_MCLK0 */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* H23 : IMGCLKOUT4 ==> WWAN_ESIM_SEL_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R4 : HDA_RST# ==> HDA_RST_L */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : HDA_SDI1 ==> I2S1_PCH_RX_SPKR_TX */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* R6 : I2S1_TXD ==> I2S1_PCH_RX_SPKR_RX */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* R7 : I2S1_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S4 : SNDW2_CLK ==> DMIC_CLK1 */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* S5 : SNDW2_DATA ==> DMIC_DATA1 */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD0: BATLOW# ==> BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1: ACPRESENT ==> PCH_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */ + PAD_CFG_GPI(GPD2, NONE, DEEP), + /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4: SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5: SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6: SLP_A# ==> SLP_A_L */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7: GPD7_STRAP */ + PAD_CFG_GPI(GPD7, DN_20K, DEEP), + /* GPD8: SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10: SLP_S5# ==> SLP_S5_L */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + /* GPD11: LANPHYC ==> NC */ +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + + /* B17 : GSPI0_MISO ==> PCH_GSPIO_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_E12, 1, DEEP), + + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H11, 1, DEEP), +}; + +const struct pad_config *__weak variant_base_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *__weak variant_override_gpio_table(size_t *num) +{ + *num = 0; + return NULL; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM1_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM1_NAME), +}; + +const struct cros_gpio *__weak variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h new file mode 100644 index 0000000000..6920287ef5 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/ec.h @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __MAINBOARD_EC_H__ +#define __MAINBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid, power button or mode change event */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +#endif /* __MAINBOARD_EC_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h new file mode 100644 index 0000000000..51f4d376a4 --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_A9 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_B11 + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_C12 +#define GPIO_MEM_CONFIG_1 GPP_C15 +#define GPIO_MEM_CONFIG_2 GPP_C14 +#define GPIO_MEM_CONFIG_3 GPP_D15 + +/* EC wake is LAN_WAKE# */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_C6_IRQ + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* DRAM population strap (value 0=fully-populated, 1=half-populated) */ +#define GPIO_MEM_CH_SEL GPP_A17 + +#endif /* BASEBOARD_GPIO_H */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h new file mode 100644 index 0000000000..df4368bb0e --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include + +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *variant_base_gpio_table(size_t *num); +const struct pad_config *variant_early_gpio_table(size_t *num); +const struct pad_config *variant_override_gpio_table(size_t *num); + +const struct cros_gpio *variant_cros_gpios(size_t *num); + +int variant_memory_sku(void); + +#endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/volteer/Makefile.inc b/src/mainboard/google/volteer/variants/volteer/Makefile.inc new file mode 100644 index 0000000000..37893c21c6 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/Makefile.inc @@ -0,0 +1,10 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2020 The coreboot project Authors. +## +## SPDX-License-Identifier: GPL-2.0-or-later +## + +## Memory Options +SPD_SOURCES = samsung-K4U6E3S4AA-MGCL # 0b0000 diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl new file mode 100644 index 0000000000..74769e3390 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/acpi/dptf.asl @@ -0,0 +1,9 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h new file mode 100644 index 0000000000..cc897dcdcf --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/ec.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h new file mode 100644 index 0000000000..bf23f6e457 --- /dev/null +++ b/src/mainboard/google/volteer/variants/volteer/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ From b1fa25fab7af09fa90a7a83f283e51358069d333 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 28 Jan 2020 00:31:26 -0800 Subject: [PATCH 111/151] soc/intel/tigerlake: add memory configuration support Move some of the common memory code that was being performed in mainboard into the soc to reduce redundant code going forward. BUG=b:145642089 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, log into kernel and verify memory size shows 8GB. Change-Id: I8de502d4f05d52b9dae34e3b013c6d5b1886fa55 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/38606 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/tigerlake/Makefile.inc | 1 + .../intel/tigerlake/include/soc/meminit_tgl.h | 70 ++++++++ src/soc/intel/tigerlake/meminit_tgl.c | 164 ++++++++++++++++++ 3 files changed, 235 insertions(+) create mode 100644 src/soc/intel/tigerlake/include/soc/meminit_tgl.h create mode 100644 src/soc/intel/tigerlake/meminit_tgl.c diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 532861dbe1..56119f50db 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -25,6 +25,7 @@ bootblock-y += p2sb.c romstage-y += espi.c romstage-y += gpio.c +romstage-$(CONFIG_SOC_INTEL_TIGERLAKE) += meminit_tgl.c romstage-y += reset.c ramstage-y += acpi.c diff --git a/src/soc/intel/tigerlake/include/soc/meminit_tgl.h b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h new file mode 100644 index 0000000000..dd0541809e --- /dev/null +++ b/src/soc/intel/tigerlake/include/soc/meminit_tgl.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _SOC_MEMINIT_TGL_H_ +#define _SOC_MEMINIT_TGL_H_ + +#include +#include +#include + +#define BYTES_PER_CHANNEL 2 +#define BITS_PER_BYTE 8 +#define DQS_PER_CHANNEL 2 +#define NUM_CHANNELS 8 + +struct spd_by_pointer { + size_t spd_data_len; + uintptr_t spd_data_ptr; +}; + +enum mem_info_read_type { + NOT_EXISTING, /* No memory in this channel */ + READ_SPD_CBFS, /* Find spd file in CBFS. */ + READ_SPD_MEMPTR /* Find spd data from pointer. */ +}; + +struct spd_info { + enum mem_info_read_type read_type; + union spd_data_by { + /* To identify spd file when read_type is READ_SPD_CBFS. */ + int spd_index; + + /* To find spd data when read_type is READ_SPD_MEMPTR. */ + struct spd_by_pointer spd_data_ptr_info; + } spd_spec; +}; + +/* Board-specific memory configuration information */ +struct mb_lpddr4x_cfg { + /* DQ mapping */ + uint8_t dq_map[NUM_CHANNELS][BYTES_PER_CHANNEL * BITS_PER_BYTE]; + + /* + * DQS CPU<>DRAM map. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + uint8_t dqs_map[NUM_CHANNELS][DQS_PER_CHANNEL]; + + /* + * Early Command Training Enable/Disable Control + * 1 = enable, 0 = disable + */ + uint8_t ect; +}; + +/* Initialize default memory configurations for dimm0-only lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated); + +#endif /* _SOC_MEMINIT_TGL_H_ */ diff --git a/src/soc/intel/tigerlake/meminit_tgl.c b/src/soc/intel/tigerlake/meminit_tgl.c new file mode 100644 index 0000000000..922f66a543 --- /dev/null +++ b/src/soc/intel/tigerlake/meminit_tgl.c @@ -0,0 +1,164 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +enum dimm_enable_options { + ENABLE_BOTH_DIMMS = 0, + DISABLE_DIMM0 = 1, + DISABLE_DIMM1 = 2, + DISABLE_BOTH_DIMMS = 3 +}; + +#define MEM_INIT_CH_DQ_DQS_MAP(_mem_cfg, _b_cfg, _ch) \ + do { \ + memcpy(&_mem_cfg->DqMapCpu2DramCh ## _ch, \ + &_b_cfg->dq_map[_ch], \ + sizeof(_b_cfg->dq_map[_ch])); \ + memcpy(&_mem_cfg->DqsMapCpu2DramCh ## _ch, \ + &_b_cfg->dqs_map[_ch], \ + sizeof(_b_cfg->dqs_map[_ch])); \ + } while (0) + + +static void spd_read_from_cbfs(const struct spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + struct region_device spd_rdev; + size_t spd_index = spd->spd_spec.spd_index; + + printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found or incorrect index\n"); + + *spd_data_len = region_device_sz(&spd_rdev); + + /* Memory leak is ok since we have memory mapped boot media */ + assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); + + *spd_data_ptr = (uintptr_t)rdev_mmap_full(&spd_rdev); +} + +static void get_spd_data(const struct spd_info *spd, + uintptr_t *spd_data_ptr, size_t *spd_data_len) +{ + if (spd->read_type == READ_SPD_MEMPTR) { + *spd_data_ptr = spd->spd_spec.spd_data_ptr_info.spd_data_ptr; + *spd_data_len = spd->spd_spec.spd_data_ptr_info.spd_data_len; + return; + } + + if (spd->read_type == READ_SPD_CBFS) { + spd_read_from_cbfs(spd, spd_data_ptr, spd_data_len); + return; + } + + die("no valid way to read SPD info"); +} + +static void meminit_dq_dqs_map(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + bool half_populated) +{ + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 0); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 1); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 2); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 3); + + if (half_populated) + return; + + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 4); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 5); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 6); + MEM_INIT_CH_DQ_DQS_MAP(mem_cfg, board_cfg, 7); +} + +static void meminit_channels_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + uintptr_t spd_data_ptr, + bool half_populated) +{ + uint8_t dimm_cfg = DISABLE_DIMM1; /* Use only DIMM0 */ + + /* Channel 0 */ + mem_cfg->Reserved9[0] = dimm_cfg; + mem_cfg->MemorySpdPtr00 = spd_data_ptr; + mem_cfg->MemorySpdPtr01 = 0; + + /* Channel 1 */ + mem_cfg->Reserved9[1] = dimm_cfg; + mem_cfg->MemorySpdPtr02 = spd_data_ptr; + mem_cfg->MemorySpdPtr03 = 0; + + /* Channel 2 */ + mem_cfg->Reserved9[2] = dimm_cfg; + mem_cfg->MemorySpdPtr04 = spd_data_ptr; + mem_cfg->MemorySpdPtr05 = 0; + + /* Channel 3 */ + mem_cfg->Reserved9[3] = dimm_cfg; + mem_cfg->MemorySpdPtr06 = spd_data_ptr; + mem_cfg->MemorySpdPtr07 = 0; + + if (half_populated) { + printk(BIOS_INFO, "%s: DRAM half-populated\n", __func__); + dimm_cfg = DISABLE_BOTH_DIMMS; + spd_data_ptr = 0; + } + + /* Channel 4 */ + mem_cfg->Reserved9[4] = dimm_cfg; + mem_cfg->MemorySpdPtr08 = spd_data_ptr; + mem_cfg->MemorySpdPtr09 = 0; + + /* Channel 5 */ + mem_cfg->Reserved9[5] = dimm_cfg; + mem_cfg->MemorySpdPtr10 = spd_data_ptr; + mem_cfg->MemorySpdPtr11 = 0; + + /* Channel 6 */ + mem_cfg->Reserved9[6] = dimm_cfg; + mem_cfg->MemorySpdPtr12 = spd_data_ptr; + mem_cfg->MemorySpdPtr13 = 0; + + /* Channel 7 */ + mem_cfg->Reserved9[7] = dimm_cfg; + mem_cfg->MemorySpdPtr14 = spd_data_ptr; + mem_cfg->MemorySpdPtr15 = 0; + + meminit_dq_dqs_map(mem_cfg, board_cfg, half_populated); +} + +/* Initialize onboard memory configurations for lpddr4x */ +void meminit_lpddr4x_dimm0(FSP_M_CONFIG *mem_cfg, + const struct mb_lpddr4x_cfg *board_cfg, + const struct spd_info *spd, + bool half_populated) + +{ + size_t spd_data_len; + uintptr_t spd_data_ptr; + + get_spd_data(spd, &spd_data_ptr, &spd_data_len); + print_spd_info((unsigned char *)spd_data_ptr); + + mem_cfg->MemorySpdDataLen = spd_data_len; + meminit_channels_dimm0(mem_cfg, board_cfg, spd_data_ptr, + half_populated); + + /* LPDDR4 does not allow interleaved memory */ + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->ECT = board_cfg->ect; + mem_cfg->MrcSafeConfig = 0x1; +} From 540b8ecc1e965bbcceb16d46a5ecd51ee693fbea Mon Sep 17 00:00:00 2001 From: T Michael Turney Date: Fri, 24 Jan 2020 08:42:47 -0800 Subject: [PATCH 112/151] trogdor: update python scripts for python3 Change-Id: I46525243729c1dbcd30b346d4603452eea14ad9d Signed-off-by: T Michael Turney Reviewed-on: https://review.coreboot.org/c/coreboot/+/38558 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner --- util/qualcomm/createxbl.py | 92 +++++++++---------- util/qualcomm/ipqheader.py | 4 +- util/qualcomm/mbn_tools.py | 183 ++++++++++++++++++++----------------- util/qualcomm/mbncat.py | 42 ++++----- util/qualcomm/qgpt.py | 2 +- 5 files changed, 170 insertions(+), 153 deletions(-) diff --git a/util/qualcomm/createxbl.py b/util/qualcomm/createxbl.py index 861cec9110..65d8eb9460 100755 --- a/util/qualcomm/createxbl.py +++ b/util/qualcomm/createxbl.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 #============================================================================ # #/** @file createxbl.py @@ -238,9 +238,9 @@ def main(): target_nonsec = target_base + "_combined_hash.mbn" - #print "Input file 1:", elf_inp_file1 - #print "Input file 2:", elf_inp_file2 - #print "Output file:", binary_out + #print("Input file 1:", elf_inp_file1) + #print("Input file 2:", elf_inp_file2) + #print("Output file:", binary_out) merge_elfs([], elf_inp_file1, @@ -270,7 +270,7 @@ def main(): secure_type = image_header_secflag, header_version = header_version ) if rv: - raise RuntimeError, "Failed to run pboot_gen_elf" + raise RuntimeError("Failed to run pboot_gen_elf") # Create hash table header rv = mbn_tools.image_header([], @@ -281,7 +281,7 @@ def main(): elf_file_name = source_elf, header_version = header_version) if rv: - raise RuntimeError, "Failed to create image header for hash segment" + raise RuntimeError("Failed to create image header for hash segment") files_to_cat_in_order = [target_hash_hd, target_hash] mbn_tools.concat_files (target_nonsec, files_to_cat_in_order) @@ -369,7 +369,7 @@ def merge_elfs(env, # Create a new ELF header for the output file if is_out_elf_64_bit: - out_elf_header = mbn_tools.Elf64_Ehdr('\0' * ELF64_HDR_SIZE) + out_elf_header = mbn_tools.Elf64_Ehdr(b'\0' * ELF64_HDR_SIZE) out_elf_header.e_phoff = ELF64_HDR_SIZE out_elf_header.e_ehsize = ELF64_HDR_SIZE out_elf_header.e_phentsize = ELF64_PHDR_SIZE @@ -384,7 +384,7 @@ def merge_elfs(env, out_elf_header.e_entry = elf_header1.e_entry else: - out_elf_header = mbn_tools.Elf32_Ehdr('\0' * ELF32_HDR_SIZE) + out_elf_header = mbn_tools.Elf32_Ehdr(b'\0' * ELF32_HDR_SIZE) out_elf_header.e_phoff = ELF32_HDR_SIZE out_elf_header.e_ehsize = ELF32_HDR_SIZE out_elf_header.e_phentsize = ELF32_PHDR_SIZE @@ -401,7 +401,7 @@ def merge_elfs(env, # Address needs to be verified that it is not greater than 32 bits # as it is possible to go from a 64 bit elf to 32. if (elf_header1.e_entry > 0xFFFFFFFF): - print "ERROR: File 1's entry point is too large to convert." + print("ERROR: File 1's entry point is too large to convert.") exit() out_elf_header.e_entry = elf_header1.e_entry @@ -457,7 +457,7 @@ def merge_elfs(env, # Copy program header piece by piece to ensure possible conversion success if is_out_elf_64_bit == True: # Converting from 32 to 64 elf requires no data size validation - new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = mbn_tools.Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -470,7 +470,7 @@ def merge_elfs(env, # Converting from 64 to 32 elf requires data size validation # Note that there is an option to discard a segment if it is only ZI # and its address is greater than 32 bits - new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = mbn_tools.Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset @@ -478,7 +478,7 @@ def merge_elfs(env, if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 1 VAddr is too large for conversion." + print("ERROR: File 1 VAddr is too large for conversion.") exit() new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -486,33 +486,33 @@ def merge_elfs(env, if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 1 PAddr is too large for conversion." + print("ERROR: File 1 PAddr is too large for conversion.") exit() new_phdr.p_paddr = curr_phdr.p_paddr if curr_phdr.p_filesz > 0xFFFFFFFF: - print "ERROR: File 1 Filesz is too large for conversion." + print("ERROR: File 1 Filesz is too large for conversion.") exit() new_phdr.p_filesz = curr_phdr.p_filesz if curr_phdr.p_memsz > 0xFFFFFFFF: - print "ERROR: File 1 Memsz is too large for conversion." + print("ERROR: File 1 Memsz is too large for conversion.") exit() new_phdr.p_memsz = curr_phdr.p_memsz if curr_phdr.p_flags > 0xFFFFFFFF: - print "ERROR: File 1 Flags is too large for conversion." + print("ERROR: File 1 Flags is too large for conversion.") exit() new_phdr.p_flags = curr_phdr.p_flags if curr_phdr.p_align > 0xFFFFFFFF: - print "ERROR: File 1 Align is too large for conversion." + print("ERROR: File 1 Align is too large for conversion.") exit() new_phdr.p_align = curr_phdr.p_align - #print "i=",i - #print "phdr_offset=", phdr_offset + #print("i=",i) + #print("phdr_offset=", phdr_offset) # update output file location to next phdr location elf_out_fp.seek(phdr_offset) @@ -521,14 +521,14 @@ def merge_elfs(env, inp_data_offset = curr_phdr.p_offset # used to read data from input file -# print "inp_data_offset=" -# print inp_data_offset +# print("inp_data_offset=") +# print(inp_data_offset) # -# print "curr_phdr.p_offset=" -# print curr_phdr.p_offset +# print("curr_phdr.p_offset=") +# print(curr_phdr.p_offset) # -# print "curr_phdr.p_filesz=" -# print curr_phdr.p_filesz +# print("curr_phdr.p_filesz=") +# print(curr_phdr.p_filesz) # output current phdr if is_out_elf_64_bit == False: @@ -555,7 +555,7 @@ def merge_elfs(env, # Copy program header piece by piece to ensure possible conversion success if is_out_elf_64_bit == True: # Converting from 32 to 64 elf requires no data size validation - new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = mbn_tools.Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -568,7 +568,7 @@ def merge_elfs(env, # Converting from 64 to 32 elf requires data size validation # Note that there is an option to discard a segment if it is only ZI # and its address is greater than 32 bits - new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = mbn_tools.Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) new_phdr.p_type = curr_phdr.p_type new_phdr.p_offset = segment_offset @@ -576,7 +576,7 @@ def merge_elfs(env, if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 2 VAddr is too large for conversion." + print("ERROR: File 2 VAddr is too large for conversion.") exit() new_phdr.p_vaddr = curr_phdr.p_vaddr @@ -584,33 +584,33 @@ def merge_elfs(env, if (zi_oob_enabled == True) and (curr_phdr.p_filesz == 0): continue else: - print "ERROR: File 2 PAddr is too large for conversion." + print("ERROR: File 2 PAddr is too large for conversion.") exit() new_phdr.p_paddr = curr_phdr.p_paddr if curr_phdr.p_filesz > 0xFFFFFFFF: - print "ERROR: File 2 Filesz is too large for conversion." + print("ERROR: File 2 Filesz is too large for conversion.") exit() new_phdr.p_filesz = curr_phdr.p_filesz if curr_phdr.p_memsz > 0xFFFFFFFF: - print "ERROR: File 2 Memsz is too large for conversion." + print("ERROR: File 2 Memsz is too large for conversion.") exit() new_phdr.p_memsz = curr_phdr.p_memsz if curr_phdr.p_flags > 0xFFFFFFFF: - print "ERROR: File 2 Flags is too large for conversion." + print("ERROR: File 2 Flags is too large for conversion.") exit() new_phdr.p_flags = curr_phdr.p_flags if curr_phdr.p_align > 0xFFFFFFFF: - print "ERROR: File 2 Align is too large for conversion." + print("ERROR: File 2 Align is too large for conversion.") exit() new_phdr.p_align = curr_phdr.p_align -# print "i=",i -# print "phdr_offset=", phdr_offset +# print("i=",i) +# print("phdr_offset=", phdr_offset) # update output file location to next phdr location elf_out_fp.seek(phdr_offset) @@ -619,14 +619,14 @@ def merge_elfs(env, inp_data_offset = curr_phdr.p_offset # used to read data from input file -# print "inp_data_offset=" -# print inp_data_offset +# print("inp_data_offset=") +# print(inp_data_offset) # -# print "curr_phdr.p_offset=" -# print curr_phdr.p_offset +# print("curr_phdr.p_offset=") +# print(curr_phdr.p_offset) # -# print "curr_phdr.p_filesz=" -# print curr_phdr.p_filesz +# print("curr_phdr.p_filesz=") +# print(curr_phdr.p_filesz) # output current phdr if is_out_elf_64_bit == False: @@ -658,14 +658,14 @@ def merge_elfs(env, entry_seg_offset = phdr.p_offset break if entry_seg_offset == -1: - print "Error: Failed to find entry point in any segment!" + print("Error: Failed to find entry point in any segment!") exit() # magical equation for program header's phys and virt addr phys_virt_addr = entry_addr - entry_seg_offset if is_out_elf_64_bit: # Converting from 32 to 64 elf requires no data size validation - new_phdr = mbn_tools.Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = mbn_tools.Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) new_phdr.p_type = 0x1 new_phdr.p_offset = segment_offset new_phdr.p_vaddr = phys_virt_addr @@ -683,7 +683,7 @@ def merge_elfs(env, # Converting from 64 to 32 elf requires data size validation # Don't discard the segment containing xbl_sec, simply error out # if the address is greater than 32 bits - new_phdr = mbn_tools.Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = mbn_tools.Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) new_phdr.p_type = 0x1 # new_phdr.p_offset = segment_offset if header_version >= 5: @@ -696,13 +696,13 @@ def merge_elfs(env, if phys_virt_addr > 0xFFFFFFFF: if zi_oob_enabled == False or curr_phdr.p_filesz != 0: - print "ERROR: File xbl_sec VAddr or PAddr is too big for conversion." + print("ERROR: File xbl_sec VAddr or PAddr is too big for conversion.") exit() new_phdr.p_vaddr = phys_virt_addr new_phdr.p_paddr = phys_virt_addr if os.path.getsize(elf_in_file_xbl_sec) > 0xFFFFFFFF: - print "ERROR: File xbl_sec Filesz is too big for conversion." + print("ERROR: File xbl_sec Filesz is too big for conversion.") exit() new_phdr.p_filesz = os.path.getsize(elf_in_file_xbl_sec) new_phdr.p_memsz = new_phdr.p_filesz diff --git a/util/qualcomm/ipqheader.py b/util/qualcomm/ipqheader.py index 7615146499..fe14e1f241 100755 --- a/util/qualcomm/ipqheader.py +++ b/util/qualcomm/ipqheader.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # # Copyright (c) 2013 The Linux Foundation. All rights reserved. # @@ -97,7 +97,7 @@ def usage(msg=None): if msg != None: sys.stderr.write("%s: %s\n" % (PROG_NAME, msg)) - print "Usage: %s " % PROG_NAME + print("Usage: %s " % PROG_NAME) if msg != None: exit(1) diff --git a/util/qualcomm/mbn_tools.py b/util/qualcomm/mbn_tools.py index 6008da5d82..b89044ffb9 100755 --- a/util/qualcomm/mbn_tools.py +++ b/util/qualcomm/mbn_tools.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 #=============================================================================== # # MBN TOOLS @@ -100,24 +100,24 @@ ELFINFO_MAG0_INDEX = 0 ELFINFO_MAG1_INDEX = 1 ELFINFO_MAG2_INDEX = 2 ELFINFO_MAG3_INDEX = 3 -ELFINFO_MAG0 = '\x7f' -ELFINFO_MAG1 = 'E' -ELFINFO_MAG2 = 'L' -ELFINFO_MAG3 = 'F' +ELFINFO_MAG0 = 127 # 0x7F +ELFINFO_MAG1 = 69 # E +ELFINFO_MAG2 = 76 # L +ELFINFO_MAG3 = 70 # F ELFINFO_CLASS_INDEX = 4 -ELFINFO_CLASS_32 = '\x01' -ELFINFO_CLASS_64 = '\x02' +ELFINFO_CLASS_32 = 1 +ELFINFO_CLASS_64 = 2 ELFINFO_VERSION_INDEX = 6 -ELFINFO_VERSION_CURRENT = '\x01' +ELFINFO_VERSION_CURRENT = 1 ELF_BLOCK_ALIGN = 0x1000 ALIGNVALUE_1MB = 0x100000 ALIGNVALUE_4MB = 0x400000 -ELFINFO_DATA2LSB = '\x01' -ELFINFO_EXEC_ETYPE = '\x02\x00' -ELFINFO_ARM_MACHINETYPE = '\x28\x00' -ELFINFO_VERSION_EV_CURRENT = '\x01\x00\x00\x00' +ELFINFO_DATA2LSB = b'\x01' +ELFINFO_EXEC_ETYPE = b'\x02\x00' +ELFINFO_ARM_MACHINETYPE = b'\x28\x00' +ELFINFO_VERSION_EV_CURRENT = b'\x01\x00\x00\x00' ELFINFO_SHOFF = 0x00 -ELFINFO_PHNUM = '\x01\x00' +ELFINFO_PHNUM = b'\x01\x00' ELFINFO_RESERVED = 0x00 # ELF Program Header Types @@ -330,9 +330,9 @@ class Elf_Ehdr_common: self.e_version = unpacked_data[3] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) @@ -362,12 +362,16 @@ class Elf32_Ehdr: self.e_shstrndx = unpacked_data[13] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): - values = [self.e_ident, + if type(self.e_ident) == str: + packvalue = bytes(self.e_ident, 'utf-8') + else: + packvalue = self.e_ident + values = [packvalue, self.e_type, self.e_machine, self.e_version, @@ -406,9 +410,9 @@ class Elf32_Phdr: self.p_align = unpacked_data[7] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): values = [self.p_type, @@ -449,12 +453,16 @@ class Elf64_Ehdr: self.e_shstrndx = unpacked_data[13] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): - values = [self.e_ident, + if type(self.e_ident) == str: + packvalue = bytes(self.e_ident, 'utf-8') + else: + packvalue = self.e_ident + values = [packvalue, self.e_type, self.e_machine, self.e_version, @@ -493,9 +501,9 @@ class Elf64_Phdr: self.p_align = unpacked_data[7] def printValues(self): - print "ATTRIBUTE / VALUE" - for attr, value in self.__dict__.iteritems(): - print attr, value + print("ATTRIBUTE / VALUE") + for attr, value in self.__dict__.items(): + print(attr, value) def getPackedData(self): values = [self.p_type, @@ -518,7 +526,7 @@ class SegmentInfo: def __init__(self): self.flag = 0 def printValues(self): - print 'Flag: ' + str(self.flag) + print('Flag: ' + str(self.flag)) #---------------------------------------------------------------------------- # Regular Boot Header Class @@ -740,7 +748,7 @@ def generate_meta_data(env, meta_out_file_name, add_magic_num = False): xml_target_file.close() else: xml_target_file.close() - raise RuntimeError, "XML Size too large: " + str(xml_header_size) + raise RuntimeError("XML Size too large: " + str(xml_header_size)) #---------------------------------------------------------------------------- # encrypt_mbn @@ -831,7 +839,7 @@ def create_elf_header( output_file_name, is_elf_64_bit = False): if (output_file_name is None): - raise RuntimeError, "Requires a ELF header file" + raise RuntimeError("Requires a ELF header file") # Create a elf header and program header # Write the headers to the output file @@ -922,13 +930,13 @@ def image_header(env, gen_dict, # Preliminary checks if (requires_preamble is True) and (preamble_file_name is None): - raise RuntimeError, "Image Header requires a preamble file" + raise RuntimeError("Image Header requires a preamble file") if (gen_dict['IMAGE_KEY_MBN_TYPE'] == 'elf') and (elf_file_name is None): - raise RuntimeError, "ELF Image Headers require an elf file" + raise RuntimeError("ELF Image Headers require an elf file") if (in_code_size is None) and (os.path.exists(code_file_name) is False): - raise RuntimeError, "Code size unavailable, and input file does not exist" + raise RuntimeError("Code size unavailable, and input file does not exist") # Initialize if in_code_size is not None: @@ -1018,7 +1026,7 @@ def image_header(env, gen_dict, boot_header.writePackedData(target = output_file_name, write_full_hdr = write_full_hdr) else: - raise RuntimeError, "Header format not supported: " + str(header_format) + raise RuntimeError("Header format not supported: " + str(header_format)) return 0 @@ -1066,15 +1074,15 @@ def pboot_gen_elf(env, elf_in_file_name, hashtable_shift = 0 if elf_header.e_ident[ELFINFO_CLASS_INDEX] == ELFINFO_CLASS_64: - new_phdr = Elf64_Phdr('\0' * ELF64_PHDR_SIZE) + new_phdr = Elf64_Phdr(b'\0' * ELF64_PHDR_SIZE) elf_header_size = ELF64_HDR_SIZE is_elf64 = True else: - new_phdr = Elf32_Phdr('\0' * ELF32_PHDR_SIZE) + new_phdr = Elf32_Phdr(b'\0' * ELF32_PHDR_SIZE) elf_header_size = ELF32_HDR_SIZE is_elf64 = False - hash = '\0' * mi_prog_boot_digest_size + hash = b'\0' * mi_prog_boot_digest_size phdr_start = 0 bytes_to_pad = 0 hash_seg_end = 0 @@ -1083,7 +1091,7 @@ def pboot_gen_elf(env, elf_in_file_name, if elf_out_file_name is not None: # Assert limit on number of program headers in input ELF if num_phdrs > MAX_PHDR_COUNT: - raise RuntimeError, "Input ELF has exceeded maximum number of program headers" + raise RuntimeError("Input ELF has exceeded maximum number of program headers") # Create new program header for the ELF Header + Program Headers new_phdr.p_type = NULL_TYPE @@ -1093,11 +1101,11 @@ def pboot_gen_elf(env, elf_in_file_name, elf_header.e_phnum += 2 # Create an empty hash entry for PHDR_TYPE - hash_out_fp.write('\0' * mi_prog_boot_digest_size) + hash_out_fp.write(b'\0' * mi_prog_boot_digest_size) hashtable_size += mi_prog_boot_digest_size # Create an empty hash entry for the hash segment itself - hash_out_fp.write('\0' * mi_prog_boot_digest_size) + hash_out_fp.write(b'\0' * mi_prog_boot_digest_size) hashtable_size += mi_prog_boot_digest_size # Begin hash table generation @@ -1117,7 +1125,7 @@ def pboot_gen_elf(env, elf_in_file_name, # Seg_size should be page aligned if (seg_size & (ELF_BLOCK_ALIGN - 1)) > 0: - raise RuntimeError, "seg_size: " + hex(seg_size) + " is not ELF page aligned!" + raise RuntimeError("seg_size: " + hex(seg_size) + " is not ELF page aligned!") off = seg_offset + seg_size @@ -1134,7 +1142,7 @@ def pboot_gen_elf(env, elf_in_file_name, if MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True: hash = generate_hash(fbuf, sha_algo) else: - hash = '\0' * mi_prog_boot_digest_size + hash = b'\0' * mi_prog_boot_digest_size # Write hash to file hash_out_fp.write(hash) @@ -1153,7 +1161,7 @@ def pboot_gen_elf(env, elf_in_file_name, if (MI_PBT_CHECK_FLAG_TYPE(curr_phdr.p_flags) is True) and (data_len > 0): hash = generate_hash(file_buff, sha_algo) else: - hash = '\0' * mi_prog_boot_digest_size + hash = b'\0' * mi_prog_boot_digest_size # Write hash to file hash_out_fp.write(hash) @@ -1179,9 +1187,9 @@ def pboot_gen_elf(env, elf_in_file_name, if (hash_seg_max_size is not None): # Error checking for hash segment size validity if hashtable_size > hash_seg_max_size: - raise RuntimeError, "Hash table exceeds maximum hash segment size: " + hex(hash_seg_max_size) + raise RuntimeError("Hash table exceeds maximum hash segment size: " + hex(hash_seg_max_size)) if (hash_seg_max_size & (ELF_BLOCK_ALIGN-1)) is not 0: - raise RuntimeError, "Hash segment size passed is not ELF Block Aligned: " + hex(hash_seg_max_size) + raise RuntimeError("Hash segment size passed is not ELF Block Aligned: " + hex(hash_seg_max_size)) # Check if hash physical address parameter was passed if last_phys_addr is not None: @@ -1324,7 +1332,7 @@ def pboot_add_hash(env, elf_in_file_name, file_copy_offset(hash_tbl_fp, 0, elf_out_fp, hash_hdr_offset, hash_size) else: - raise RuntimeError, "Hash segment program header not found in file " + elf_in_file_name + raise RuntimeError("Hash segment program header not found in file " + elf_in_file_name) # Close files elf_in_fp.close() @@ -1339,7 +1347,7 @@ def pboot_add_hash(env, elf_in_file_name, def image_auth(env, *args): if len(args) < 7 or len(args) > 8: - raise RuntimeError, "Usage Invalid" + raise RuntimeError("Usage Invalid") # Initialize File Names binary_in = args[0] @@ -1369,7 +1377,7 @@ def image_auth(env, *args): num_certs = num_certs + 1 if (num_certs == 0): - raise RuntimeError, "Missing file(s) required for signing.\n" + raise RuntimeError("Missing file(s) required for signing.\n") # Create the Certificate Chain concat_files (cert_chain_out, cert_list) @@ -1383,7 +1391,7 @@ def image_auth(env, *args): pad_file(cert_fp, bytes_to_pad, PAD_BYTE_1) cert_fp.close() else: - raise RuntimeError, "Certificate Size too large: " + str(cert_size) + raise RuntimeError("Certificate Size too large: " + str(cert_size)) # Create the Final Signed Image File concat_files (signed_image_out, [binary_in, signature, cert_chain_out]) @@ -1488,7 +1496,7 @@ def modify_elf_flags(env, elf_in_file_name, # Check for corresponding number of segments if len(segment_list) is not elf_header.e_phnum: - raise RuntimeError, 'SCL file and ELF file have different number of segments!' + raise RuntimeError('SCL file and ELF file have different number of segments!') # Go to the start of the p_flag entry in the first program header file_offset = elf_header.e_phoff + phdr_flag_off @@ -1595,11 +1603,11 @@ def generate_code_hash(env, elf_in_file_name): (curr_phdr.p_flags & PH_PERM_MASK) == PH_PERM_RX and curr_pages == code_seg_pages): if (code_seg_idx != -1): - raise RuntimeError, 'Multiple code segments match for: ' + code_seg_pages + ' pages' + raise RuntimeError('Multiple code segments match for: ' + code_seg_pages + ' pages') code_seg_idx = i if (code_seg_idx == -1): - raise RuntimeError, 'No matching code segment found' + raise RuntimeError('No matching code segment found') code_phdr = phdr_table[code_seg_idx] @@ -1673,7 +1681,7 @@ def readSCL(filename, global_dict): # Token 1: Segment Name # Token 2: Start Address -- not used in MBN tools if len(tokens) < 2: - raise RuntimeError, 'SCL Segment Syntax malformed: ' + previous_line + raise RuntimeError('SCL Segment Syntax malformed: ' + previous_line) # Get the segment flags corresponding to the segment name description new_scl_entry.flag = getSegmentFlag(tokens[0].strip(strip_chars)) @@ -1720,7 +1728,7 @@ def getSegmentFlag(seg_info): UNSECURE = "UNSECURE" if seg_info is None or len(seg_info) is 0: - raise RuntimeError, 'Invalid segment information passed: ' + seg_info + raise RuntimeError('Invalid segment information passed: ' + seg_info) # Conditional checks and assignments of the corresponding segment flag values if NOTPAGEABLE in seg_info: @@ -1782,7 +1790,7 @@ def getSegmentFlag(seg_info): ret_val = MI_PBT_ELF_UNSECURE_SEGMENT else: - raise RuntimeError, 'The segment name is wrongly defined in the SCL file: ' + seg_info + raise RuntimeError('The segment name is wrongly defined in the SCL file: ' + seg_info) return ret_val @@ -1793,7 +1801,7 @@ def getSegmentFlag(seg_info): def pad_file(fp, num_bytes, value): if num_bytes < 0: - raise RuntimeError, "Number of bytes to pad must be greater than zero" + raise RuntimeError("Number of bytes to pad must be greater than zero") while num_bytes > 0: fp.write('%c' % value) @@ -1862,7 +1870,7 @@ def generate_global_dict(env): def populate_dictionary(*args): if len(args) < 1: - raise RuntimeError, "At least 1 file must be specified as an input" + raise RuntimeError("At least 1 file must be specified as an input") global_dict = {} Fields = ["Define", "Key", "Value"] @@ -1915,11 +1923,11 @@ def filter_dictionary(env, global_dict, **kwargs): # Check for Image Type # If IMAGE_TYPE parameter is not provided, raise error if not kwargs.has_key('IMAGE_TYPE'): - raise RuntimeError, "IMAGE_TYPE must be defined to use FilterDictionary." + raise RuntimeError("IMAGE_TYPE must be defined to use FilterDictionary.") else: image_type = kwargs.get('IMAGE_TYPE') if type(image_type) is not str: - raise RuntimeError, "IMAGE_TYPE must be of string type." + raise RuntimeError("IMAGE_TYPE must be of string type.") # Check for Flash Type # If FLASH_TYPE parameter is not provided, default to 'nand' @@ -1928,7 +1936,7 @@ def filter_dictionary(env, global_dict, **kwargs): else: flash_type = kwargs.get('FLASH_TYPE') if type(flash_type) is not str: - raise RuntimeError, "FLASH_TYPE must be of string type. " + raise RuntimeError("FLASH_TYPE must be of string type. ") # Check for MBN Type # If MBN_TYPE parameter is not provided, default to 'elf' @@ -1937,7 +1945,7 @@ def filter_dictionary(env, global_dict, **kwargs): else: mbn_type = kwargs.get('MBN_TYPE') if mbn_type != 'elf' and mbn_type != 'bin': - raise RuntimeError, "MBN_TYPE currently not supported: " + mbn_type + raise RuntimeError("MBN_TYPE currently not supported: " + mbn_type) # Check for Image ID # If IMAGE_ID parameter is not provided, default to ID 0 @@ -1946,7 +1954,7 @@ def filter_dictionary(env, global_dict, **kwargs): else: image_id = kwargs.get('IMAGE_ID') if type(image_id) is not int: - raise RuntimeError, "IMAGE_ID must be of integer type." + raise RuntimeError("IMAGE_ID must be of integer type.") # Initialize gen_dict = {} @@ -1971,9 +1979,9 @@ def filter_dictionary(env, global_dict, **kwargs): if template_key_match in global_dict: image_dest = global_dict[template_key_match] else: - raise RuntimeError, "Builds file does not have IMAGE_KEY pair for: " + image_type + raise RuntimeError("Builds file does not have IMAGE_KEY pair for: " + image_type) else: - raise RuntimeError, "MBN_TYPE currently not supported: " + mbn_type + raise RuntimeError("MBN_TYPE currently not supported: " + mbn_type) # Assign generic dictionary key/value pairs gen_dict['IMAGE_KEY_IMAGE_ID'] = id @@ -2004,7 +2012,7 @@ def filter_dictionary(env, global_dict, **kwargs): gen_dict['IMAGE_KEY_OEM_NUM_ROOT_CERTS'] = oem_num_root_certs else: - raise RuntimeError, "Invalid OEM root certificate configuration values" + raise RuntimeError("Invalid OEM root certificate configuration values") # Assign additional dictionary key/values pair as needed by tools. @@ -2034,7 +2042,7 @@ def preprocess_elf_file(elf_file_name): elf_header = Elf_Ehdr_common(elf_fp.read(ELF_HDR_COMMON_SIZE)) if verify_elf_header(elf_header) is False: - raise RuntimeError, "ELF file failed verification: " + elf_file_name + raise RuntimeError("ELF file failed verification: " + elf_file_name) elf_fp.seek(0) @@ -2047,7 +2055,7 @@ def preprocess_elf_file(elf_file_name): # Verify ELF header information if verify_elf_header(elf_header) is False: - raise RuntimeError, "ELF file failed verification: " + elf_file_name + raise RuntimeError("ELF file failed verification: " + elf_file_name) # Get program header size phdr_size = elf_header.e_phentsize @@ -2097,17 +2105,26 @@ def get_hash_address(elf_file_name): # Verify ELF header contents from an input ELF file #---------------------------------------------------------------------------- def verify_elf_header(elf_header): - if (elf_header.e_ident[ELFINFO_MAG0_INDEX] != ELFINFO_MAG0) or \ - (elf_header.e_ident[ELFINFO_MAG1_INDEX] != ELFINFO_MAG1) or \ - (elf_header.e_ident[ELFINFO_MAG2_INDEX] != ELFINFO_MAG2) or \ - (elf_header.e_ident[ELFINFO_MAG3_INDEX] != ELFINFO_MAG3) or \ - ((elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_64) and \ - (elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_32)) or \ - (elf_header.e_ident[ELFINFO_VERSION_INDEX] != ELFINFO_VERSION_CURRENT): - + if (elf_header.e_ident[ELFINFO_MAG0_INDEX] != ELFINFO_MAG0): + print("MAG0[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG0_INDEX]))) return False - else: - return True + if (elf_header.e_ident[ELFINFO_MAG1_INDEX] != ELFINFO_MAG1): + print("MAG1[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG1_INDEX]))) + return False + if (elf_header.e_ident[ELFINFO_MAG2_INDEX] != ELFINFO_MAG2): + print("MAG2[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG2_INDEX]))) + return False + if (elf_header.e_ident[ELFINFO_MAG3_INDEX] != ELFINFO_MAG3): + print("MAG3[{:d}]\n".format((elf_header.e_ident[ELFINFO_MAG3_INDEX]))) + return False + if ((elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_64) and \ + (elf_header.e_ident[ELFINFO_CLASS_INDEX] != ELFINFO_CLASS_32)): + print("ELFINFO_CLASS_INDEX[{:d}]\n".format((elf_header.e_ident[ELFINFO_CLASS_INDEX]))) + return False + if (elf_header.e_ident[ELFINFO_VERSION_INDEX] != ELFINFO_VERSION_CURRENT): + print("ELFINFO_VERSION_INDEX[{:d}]\n".format((elf_header.e_ident[ELFINFO_VERSION_INDEX]))) + return False + return True #---------------------------------------------------------------------------- # Perform file copy given offsets and the number of bytes to copy @@ -2159,9 +2176,9 @@ def initialize_hash_phdr(elf_in_file_name, hash_tbl_size, hdr_size, hdr_offset, # Update the hash table program header if is_elf64 is True: - hash_Phdr = Elf64_Phdr('\0'*ELF64_PHDR_SIZE) + hash_Phdr = Elf64_Phdr(b'\0'*ELF64_PHDR_SIZE) else: - hash_Phdr = Elf32_Phdr('\0'*ELF32_PHDR_SIZE) + hash_Phdr = Elf32_Phdr(b'\0'*ELF32_PHDR_SIZE) hash_Phdr.p_flags = MI_PBT_ELF_HASH_SEGMENT hash_Phdr.p_align = ELF_BLOCK_ALIGN hash_Phdr.p_offset = hash_hdr_offset @@ -2243,7 +2260,7 @@ def OPEN(file_name, mode): try: fp = open(file_name, mode) except IOError: - raise RuntimeError, "The file could not be opened: " + file_name + raise RuntimeError("The file could not be opened: " + file_name) # File open has succeeded with the given mode, return the file object return fp diff --git a/util/qualcomm/mbncat.py b/util/qualcomm/mbncat.py index c4da265f80..622ed2dcbd 100755 --- a/util/qualcomm/mbncat.py +++ b/util/qualcomm/mbncat.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 # Copyright (c) 2014, The Linux Foundation. All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -75,27 +75,27 @@ class NorSbl: self.verbose = verbose self.mbn_file_names = [] if self.verbose: - print 'Reading ' + sbl1 + print('Reading ' + sbl1) try: self.sbl1 = open(sbl1, 'rb').read() except IOError as e: - print 'I/O error({0}): {1}'.format(e.errno, e.strerror) + print('I/O error({0}): {1}'.format(e.errno, e.strerror)) raise (codeword, magic, _) = struct.unpack_from( self.NOR_SBL1_HEADER, self.sbl1) if codeword != self.NOR_CODE_WORD: - print '\n\nError: Unexpected Codeword!' - print 'Codeword : ' + ('0x%x' % self.NOR_CODE_WORD) + \ - ' != ' + ('0x%x' % codeword) + print('\n\nError: Unexpected Codeword!') + print('Codeword : ' + ('0x%x' % self.NOR_CODE_WORD) + \ + ' != ' + ('0x%x' % codeword)) sys.exit(-1) if magic != self.MAGIC_NUM: - print '\n\nError: Unexpected Magic!' - print 'Magic : ' + ('0x%x' % self.MAGIC_NUM) + \ - ' != ' + ('0x%x' % magic) + print('\n\nError: Unexpected Magic!') + print('Magic : ' + ('0x%x' % self.MAGIC_NUM) + \ + ' != ' + ('0x%x' % magic)) sys.exit(-1) def Append(self, src): @@ -119,10 +119,10 @@ class NorSbl: overflow = size % self.ALIGNMENT if overflow: pad_size = self.ALIGNMENT - overflow - pad = '\377' * pad_size + pad = b'\377' * pad_size outfile.write(pad) if self.verbose: - print 'Added %d byte padding' % pad_size + print('Added %d byte padding' % pad_size) return pad_size return 0 @@ -142,11 +142,11 @@ class NorSbl: for mbn_file_name in self.mbn_file_names: total_size += self.PadOutput(outfile, total_size) - mbn_file_data = open(mbn_file_name, 'r').read() + mbn_file_data = open(mbn_file_name, 'rb').read() outfile.write(mbn_file_data) if self.verbose: - print 'Added %s (%d bytes)' % (mbn_file_name, - len(mbn_file_data)) + print('Added %s (%d bytes)' % (mbn_file_name, + len(mbn_file_data))) total_size += len(mbn_file_data) outfile.seek(28) @@ -155,13 +155,13 @@ class NorSbl: def Usage(v): - print '%s: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock]' % ( - os.path.basename(sys.argv[0])) - print - print 'Concatenates up to three mbn files: two SBLs and a coreboot bootblock' - print ' -h This message' - print ' -v verbose' - print ' -o Output file name, (default: %s)\n' % DEFAULT_OUTPUT_FILE_NAME + print('%s: [-v] [-h] [-o Output MBN] sbl1 sbl2 [bootblock]' % ( + os.path.basename(sys.argv[0]))) + print() + print('Concatenates up to three mbn files: two SBLs and a coreboot bootblock') + print(' -h This message') + print(' -v verbose') + print(' -o Output file name, (default: %s)\n' % DEFAULT_OUTPUT_FILE_NAME) sys.exit(v) def main(): diff --git a/util/qualcomm/qgpt.py b/util/qualcomm/qgpt.py index 0b096b9cf5..fbf6d103df 100755 --- a/util/qualcomm/qgpt.py +++ b/util/qualcomm/qgpt.py @@ -1,4 +1,4 @@ -#!/usr/bin/env python2 +#!/usr/bin/env python3 #============================================================================ # #/** @file qgpt.py From 118e9755ecbd5dc8f793db620df228c47d850707 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 6 Feb 2020 13:53:10 -0700 Subject: [PATCH 113/151] mb/google/dedede: Add Compute & PCH Global device IDs Add compute and PCH Global device IDs with the concerned devices turned off. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I6f226abd52d4a27535de6711e93355b5f84a1941 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38738 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- .../dedede/variants/baseboard/devicetree.cb | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index eb9dc1cffb..cdd325cdd6 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -2,4 +2,50 @@ chip soc/intel/tigerlake device cpu_cluster 0 on device lapic 0 on end end + + device domain 0 on + device pci 00.0 off end # Host Bridge + device pci 02.0 off end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # IPU + device pci 09.0 off end # Intel Trace Hub + device pci 12.6 off end # GSPI 2 + device pci 14.0 off end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 off end # PMC SRAM + device pci 14.3 off end # CNVi wifi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 16.0 off end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 off end # SATA + device pci 19.0 off end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 off end # UART 2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 - WLAN + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 off end # eSPI Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA/cAVS + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + end end From cc633f2e3a946e3538f71e9e9918183f8f40015e Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 7 Feb 2020 13:11:02 -0700 Subject: [PATCH 114/151] mb/google/dedede: Add GPE configuration Configure the GPIO groups to be routed to the GPE0 block. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: Ife4d0179bd9fe1785e971686478f7c76de805e87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38771 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh --- .../dedede/variants/baseboard/devicetree.cb | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index cdd325cdd6..aedd32f7cc 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -3,6 +3,22 @@ chip soc/intel/tigerlake device lapic 0 on end end + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. + # DW0 is used by: + # - GPP_B3 - TRACKPAD_INT_ODL + # - GPP_B4 - H1_AP_INT_ODL + # DW1 is used by: + # - GPP_D3 - WLAN_PCIE_WAKE_ODL + # DW2 is used by: + # - GPP_H16 - WWAN_HOST_WAKE + # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_H" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device From 441867d2f068a3ff9951fcbbb97d3a07c1867626 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 6 Feb 2020 15:42:43 -0700 Subject: [PATCH 115/151] mb/google/dedede: Turn on ESPI device in devicetree BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I12a63e5776619e5a7684cf1edad78b0fd6fac12c Reviewed-on: https://review.coreboot.org/c/coreboot/+/38739 Reviewed-by: Justin TerAvest Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/dedede/variants/baseboard/devicetree.cb | 6 +++++- src/mainboard/google/dedede/variants/baseboard/gpio.c | 9 ++++++++- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index aedd32f7cc..44d9ca2e3b 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -56,7 +56,11 @@ chip soc/intel/tigerlake device pci 1e.1 off end # UART 1 device pci 1e.2 off end # GSPI 0 device pci 1e.3 off end # GSPI 1 - device pci 1f.0 off end # eSPI Interface + device pci 1f.0 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # eSPI Interface device pci 1f.1 off end # P2SB device pci 1f.2 off end # Power Management Controller device pci 1f.3 off end # Intel HDA/cAVS diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index 6c95a1d0f0..090841260f 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -13,7 +13,14 @@ /* Pad configuration in ramstage*/ static const struct pad_config gpio_table[] = { - /* ToDo: Fill gpio configuration */ + /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 */ + /* A1 : ESPI_IO1 */ + /* A2 : ESPI_IO2 */ + /* A3 : ESPI_IO3 */ + /* A4 : ESPI_CS# */ + /* A5 : ESPI_CLK */ + /* A6 : ESPI_RESET_L */ }; /* Early pad configuration in bootblock */ From c015bcc304d140c787a33f04fbd13e90c34cf7a0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Fri, 7 Feb 2020 16:45:26 -0700 Subject: [PATCH 116/151] mb/google/dedede: Add initial configuration for serial IO ports Add initial configuration for GSPI, I2C and UART ports and leave them in disabled state. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian Change-Id: I1cd7659337e6330a8ece34df247e399a085d21d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38775 Tested-by: build bot (Jenkins) Reviewed-by: Justin TerAvest --- .../dedede/variants/baseboard/devicetree.cb | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 44d9ca2e3b..2a0b760728 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -19,6 +19,39 @@ chip soc/intel/tigerlake register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_H" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device pci 00.0 off end # Host Bridge device pci 02.0 off end # Integrated Graphics Device From e967cfa4098ce9756ebdc2a85b63def327accd92 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Fri, 24 Jan 2020 09:51:46 -0700 Subject: [PATCH 117/151] util/mainboard/google: add support for Zork Update the create_coreboot_variant.sh and kconfig.py to support the zork baseboard. Full template files will be added in a later CL. BUG=b:148161697, b:148281637 BRANCH=None TEST=`./create_coreboot_variant.sh zork dalboz` and verify that the changes staged are correct. Signed-off-by: Paul Fagerburg Change-Id: Ie0a29bb9f4bb8f3bb7eaeae8799cef861c395e7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/38559 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../google/create_coreboot_variant.sh | 28 ++++++++++++------- util/mainboard/google/kconfig.py | 27 ++++++++++-------- .../google/zork/template/Makefile.inc | 13 +++++++++ 3 files changed, 47 insertions(+), 21 deletions(-) create mode 100644 util/mainboard/google/zork/template/Makefile.inc diff --git a/util/mainboard/google/create_coreboot_variant.sh b/util/mainboard/google/create_coreboot_variant.sh index 14b2115d18..dcbacb99cd 100755 --- a/util/mainboard/google/create_coreboot_variant.sh +++ b/util/mainboard/google/create_coreboot_variant.sh @@ -13,29 +13,32 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. -VERSION="1.0.2" +VERSION="2.0.0" SCRIPT=$(basename -- "${0}") export LC_ALL=C -if [[ "$#" -lt 2 ]]; then - echo "Usage: ${SCRIPT} base_name variant_name [bug_number]" - echo "e.g. ${SCRIPT} hatch kohaku b:140261109" +if [[ "$#" -lt 3 ]]; then + echo "Usage: ${SCRIPT} base_name reference_name variant_name [bug_number]" + echo "e.g. ${SCRIPT} hatch hatch kohaku b:140261109" + echo "e.g. ${SCRIPT} zork trembyle dalboz" echo "* Adds a new variant of the baseboard to Kconfig and Kconfig.name" echo "* Copies the template files for the baseboard to the new variant" exit 1 fi -# This is the name of the base board that we're using to make the variant. +# This is the name of the base board # ${var,,} converts to all lowercase. BASE="${1,,}" +# This is the name of the reference board that we're using to make the variant. +REFERENCE="${2,,}" # This is the name of the variant that is being cloned. # ${var,,} converts to all lowercase; ${var^^} is all uppercase. -VARIANT="${2,,}" +VARIANT="${3,,}" VARIANT_UPPER="${VARIANT^^}" # Assign BUG= text, or "None" if that parameter wasn't specified. -BUG=${3:-None} +BUG=${4:-None} # This script lives in util/mainboard/google # The template files are in util/mainboard/google/${BASE}/templates @@ -61,6 +64,10 @@ git checkout -b "coreboot_${VARIANT}_${DATE}" || exit 1 # Copy the template tree to the target. mkdir -p "variants/${VARIANT}/" cp -pr "${SRC}/${BASE}/template/." "variants/${VARIANT}/" +if [[ -e "variants/${VARIANT}/Kconfig" ]]; then + sed -i -e "s/BOARD_GOOGLE_TEMPLATE/BOARD_GOOGLE_${VARIANT_UPPER}/" \ + "variants/${VARIANT}/Kconfig" +fi git add "variants/${VARIANT}/" # Now add the new variant to Kconfig and Kconfig.name @@ -75,12 +82,13 @@ git add Kconfig Kconfig.name # Now commit the files. git commit -sm "${BASE}: Create ${VARIANT} variant -Create the ${VARIANT} variant of the ${BASE} baseboard by -copying the baseboard template files to a new directory -named for the variant. +Create the ${VARIANT} variant of the ${REFERENCE} reference +board by copying the template files to a new directory named +for the variant. (Auto-Generated by ${SCRIPT} version ${VERSION}). BUG=${BUG} +BRANCH=None TEST=util/abuild/abuild -p none -t google/${BASE} -x -a make sure the build includes GOOGLE_${VARIANT_UPPER}" diff --git a/util/mainboard/google/kconfig.py b/util/mainboard/google/kconfig.py index 6f9fccf1e0..1293f4aafe 100755 --- a/util/mainboard/google/kconfig.py +++ b/util/mainboard/google/kconfig.py @@ -1,10 +1,10 @@ #!/usr/bin/env python3 # -*- coding: utf-8 -*- -"""Add a new variant to the Kconfig and Kconfig.name for the baseboard +"""Add a new variant to the Kconfig and Kconfig.name -To start a new variant of an existing baseboard, we need to add -the variant into the Kconfig and Kconfig.name files for the -baseboard. In Kconfig, we have two sections that need additional +To start a new variant of an existing reference board, we need to +add the variant into the Kconfig and Kconfig.name files for the +reference board. In Kconfig, we have two sections that need additional entries, MAINBOARD_PART_NUMBER and VARIANT_DIR. The MAINBOARD_PART_NUMBER and VARIANT_DIR just use various @@ -36,13 +36,13 @@ def main(): parser = argparse.ArgumentParser( description='Add strings to coreboot Kconfig for a new board variant') parser.add_argument('--board', type=str, required=True, - help='Name of the baseboard') + help='Name of the reference board') parser.add_argument('--variant', type=str, required=True, help='Name of the board variant') args = parser.parse_args() - if args.board not in ['hatch', 'volteer']: - print('Unsupported baseboard "' + args.board + '"') + if args.board not in ['hatch', 'volteer', 'trembyle']: + print('Unsupported reference board "' + args.board + '"') sys.exit(1) add_to_Kconfig(args.variant) @@ -95,13 +95,13 @@ def add_to_Kconfig(variant_name): print(line, file=outfile) -def add_to_Kconfig_name(baseboard_name, variant_name): +def add_to_Kconfig_name(refboard_name, variant_name): """Add a config section for the variant to the Kconfig.name Kconfig.name is easier to modify than Kconfig; it only has a block at the end with the new variant's details. - baseboard_name The name of the baseboard, e.g. 'hatch' + refboard_name The name of the reference board, e.g. 'hatch' We expect the caller to have checked that it is one we support variant_name The name of the board variant, e.g. 'kohaku' """ @@ -119,17 +119,22 @@ def add_to_Kconfig_name(baseboard_name, variant_name): print(line, file=outfile) # Now add the new section - if baseboard_name == 'hatch': + if refboard_name == 'hatch': print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) print('\tbool "-> ' + capitalized + '"', file=outfile) print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) - if baseboard_name == 'volteer': + if refboard_name == 'volteer': print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) print('\tbool "-> ' + capitalized + '"', file=outfile) print('\tselect BOARD_GOOGLE_BASEBOARD_VOLTEER', file=outfile) + if refboard_name == 'trembyle': + print('\nconfig ' + 'BOARD_GOOGLE_' + uppercase, file=outfile) + print('\tbool "-> ' + capitalized + '"', file=outfile) + print('\tselect BOARD_GOOGLE_BASEBOARD_TREMBYLE', file=outfile) + if __name__ == '__main__': main() diff --git a/util/mainboard/google/zork/template/Makefile.inc b/util/mainboard/google/zork/template/Makefile.inc new file mode 100644 index 0000000000..38cf728d8f --- /dev/null +++ b/util/mainboard/google/zork/template/Makefile.inc @@ -0,0 +1,13 @@ +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = From e653ad07caaf9c0d156f0bcc55060777c127ac6b Mon Sep 17 00:00:00 2001 From: "Hash.Hung" Date: Wed, 22 Jan 2020 14:36:38 +0800 Subject: [PATCH 118/151] mb/google/octopus/variants/lick: Increase TCC offset to 15 Change tcc offset from 0 to 15 degree celsius for lick. BUG=b:147198431 BRANCH=octopus TEST=Build, and verify test result by thermal team. Signed-off-by: Hash.Hung Change-Id: Ife6b02321145837e05c82f979998466b83317f86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38506 Reviewed-by: Marco Chen Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/lick/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/octopus/variants/lick/overridetree.cb b/src/mainboard/google/octopus/variants/lick/overridetree.cb index 41d078e882..3aa369e9b2 100644 --- a/src/mainboard/google/octopus/variants/lick/overridetree.cb +++ b/src/mainboard/google/octopus/variants/lick/overridetree.cb @@ -52,6 +52,8 @@ chip soc/intel/apollolake #| I2C5 | Audio | #| I2C6 | Trackpad | #+-------------------+---------------------------+ + register "tcc_offset" = "15" + register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, From cb0306507439d8354bb1634bebac2ac48b19de37 Mon Sep 17 00:00:00 2001 From: Piotr Kleinschmidt Date: Tue, 8 Oct 2019 16:16:44 +0200 Subject: [PATCH 119/151] sb/amd/{agesa,pi}/hudson/Kconfig: Change default SATA mode to AHCI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The attempt to install pfSense on hard disk on PC Engines apu2 board ended up in a SATA driver error. The problem is related only to BSD and didn't occur with Linux kernel. Changing SATA mode from IDE to AHCI solved the problem. Additionally AHCI is faster than IDE so it speeds up the installation. Since AHCI works perfectly with SeaBIOS, Linux and BSD, make it a default choice for all Hudson southbridges. Change-Id: I1b0322392712d797dd5a8931150c8d0ff1b60940 Signed-off-by: Piotr Kleinschmidt Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/35891 Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/southbridge/amd/agesa/hudson/Kconfig | 2 +- src/southbridge/amd/pi/hudson/Kconfig | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index e56a493a63..96857b06f1 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -90,7 +90,7 @@ config HUDSON_GEC_FWM_FILE config HUDSON_SATA_MODE int "SATA Mode" - default 0 + default 2 range 0 6 help Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index ea37e3ee12..4884b73177 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -102,7 +102,7 @@ config AMD_PUBKEY_FILE config HUDSON_SATA_MODE int "SATA Mode" - default 0 + default 2 range 0 6 help Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. From e7ad0f2a2a29f3807a66eccaa9c7962fea358bf3 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Thu, 23 Jan 2020 09:03:11 +0100 Subject: [PATCH 120/151] Documentation: Remove qemu aarch64 from project ideas This has been implemented last year. Change-Id: I24e40a7a9a9d7238b8c9d34656d5b62a26b8252b Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38533 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- Documentation/contributing/project_ideas.md | 22 --------------------- 1 file changed, 22 deletions(-) diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 5bc4cacea5..90164a2bfa 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -64,28 +64,6 @@ across architectures. ### Mentors * Timothy Pearson -## Support QEMU AArch64 -Having QEMU support for the architectures coreboot can boot helps with -some (limited) compatibility testing: While QEMU generally doesn't need -much hardware init, any CPU state changes in the boot flow will likely -be quite close to reality. - -That could be used as a baseline to ensure that changes to architecture -code doesn't entirely break these architectures - -### Requirements -* coreboot knowledge: Should know the general boot flow in coreboot. -* other knowledge: This will require knowing how the architecture - typically boots, to adapt the coreboot payload interface to be - appropriate and, for example, provide a device tree in the platform's - typical format. -* hardware requirements: since QEMU runs practically everywhere and - needs no recovery mechanism, these are suitable projects when no special - hardware is available. - -### Mentors -* Patrick Georgi - ## Add Kernel Address Sanitizer functionality to coreboot The Kernel Address Sanitizer (KASAN) is a runtime dynamic memory error detector. The idea is to check every memory access (variables) for its validity From 1c40cdf36089f95934b87907ced627a6bcab3700 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 25 Jan 2020 17:51:46 +0100 Subject: [PATCH 121/151] mb/lenovo/t400: Move `gma-mainboard.ads` to variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some board revisions have the straps for display port detection wrongly configured. So with a single list covering all variants' possible outputs, we make libgfxinit probe unimplemented ports which may stall the GMBUS controller and delay the boot for some hundred milliseconds. This just copies the list to the various variants with different display ports, so we can test the actual changes individually. Change-Id: I48cdea1d71d9553b6bdbce432eae986996329239 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38571 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/mainboard/lenovo/t400/Makefile.inc | 8 ++++- .../{ => variants/r500}/gma-mainboard.ads | 0 .../t400/coronado-5/gma-mainboard.ads | 31 +++++++++++++++++++ .../variants/t400/malibu-3/gma-mainboard.ads | 31 +++++++++++++++++++ 4 files changed, 69 insertions(+), 1 deletion(-) rename src/mainboard/lenovo/t400/{ => variants/r500}/gma-mainboard.ads (100%) create mode 100644 src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads create mode 100644 src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads diff --git a/src/mainboard/lenovo/t400/Makefile.inc b/src/mainboard/lenovo/t400/Makefile.inc index e4e6a1f012..5d5669e2a3 100644 --- a/src/mainboard/lenovo/t400/Makefile.inc +++ b/src/mainboard/lenovo/t400/Makefile.inc @@ -22,4 +22,10 @@ ramstage-y += dock.c ramstage-y += cstates.c ramstage-y += blc.c -ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +ifeq ($(CONFIG_MAINBOARD_USE_LIBGFXINIT),y) +ramstage-$(CONFIG_BOARD_LENOVO_T400) += variants/t400/malibu-3/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_R400) += variants/t400/malibu-3/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_T500) += variants/t400/coronado-5/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_W500) += variants/t400/coronado-5/gma-mainboard.ads +ramstage-$(CONFIG_BOARD_LENOVO_R500) += variants/r500/gma-mainboard.ads +endif diff --git a/src/mainboard/lenovo/t400/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads similarity index 100% rename from src/mainboard/lenovo/t400/gma-mainboard.ads rename to src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads diff --git a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads new file mode 100644 index 0000000000..680dd1b0aa --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads new file mode 100644 index 0000000000..680dd1b0aa --- /dev/null +++ b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads @@ -0,0 +1,31 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + HDMI2, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; From 15ffb63db9485bf4da5d7669e55cc645bd0e3927 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 25 Jan 2020 17:55:17 +0100 Subject: [PATCH 122/151] mb/lenovo/t400: Correct display port list for [RT]400 variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The first digital display connector is unused, but strapped as if it were on later revisions. The DP AUX channel of the second connector is implemented, though, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I7d3e8b3a2123ddc407bb5a0cce86a3634b575f4a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38572 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- .../lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads index 680dd1b0aa..92702b2978 100644 --- a/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/malibu-3/gma-mainboard.ads @@ -21,8 +21,7 @@ use HW.GFX.GMA.Display_Probing; private package GMA.Mainboard is ports : constant Port_List := - (DP1, - HDMI1, + (DP2, HDMI2, Analog, Internal, From 20b03bb706f25964fe44a977b58fc4d249f00f3d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 25 Jan 2020 17:55:17 +0100 Subject: [PATCH 123/151] mb/lenovo/t400: Correct display port list for [TW]500 variants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit T500 and W500 (Coronado-5) use both digital display connectors. Both with the DP AUX channel implemented, so add DP2 to the list. Versions with a discrete GPU don't use external, digital connectors but seem to have the straps correctly configured. So we hopefully won't have to handle these specifically. Based on schematics only, not tested. Change-Id: I31e1415eff2d5d00c4a231906e3d861d2a59b629 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38573 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- .../lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads index 680dd1b0aa..71d160087a 100644 --- a/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/t400/coronado-5/gma-mainboard.ads @@ -23,6 +23,7 @@ private package GMA.Mainboard is ports : constant Port_List := (DP1, HDMI1, + DP2, HDMI2, Analog, Internal, From d666ee86a480fbbff5b13249750a7b5d9f5b687e Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 25 Jan 2020 17:55:17 +0100 Subject: [PATCH 124/151] mb/lenovo/t400: Correct display port list for R500 variant MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The second digital display connector is unused, but strapped as if it were used. Versions with a discrete GPU seem to use PM45 (i.e. no IGD), so we can ignore these. Based on schematics only, not tested. Change-Id: Ibb47fdeef2adb9c574b7f3ec8e2b1d61d28f21da Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38574 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads index 680dd1b0aa..8a72a31c6b 100644 --- a/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads +++ b/src/mainboard/lenovo/t400/variants/r500/gma-mainboard.ads @@ -23,7 +23,6 @@ private package GMA.Mainboard is ports : constant Port_List := (DP1, HDMI1, - HDMI2, Analog, Internal, others => Disabled); From 089790c7a32f92a433cb8aa6c3342d4f235e2f33 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 25 Jan 2020 20:24:20 +0100 Subject: [PATCH 125/151] mb/lenovo/t400: Configure panel-power sequencing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If the panel-power sequencer is not configured, libgfxinit falls back to very conservative defaults (210ms before EDID is probed). This results in a boot penalty of >100ms (depending on how long it takes to probe other ports). Values are taken from the VBTs already checked in. Untested. Change-Id: I189776ce8684b4c3c01acd6d2fc433ca33a050d5 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38576 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki --- src/mainboard/lenovo/t400/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 9561dfa93f..0eea193a13 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -3,6 +3,11 @@ chip northbridge/intel/gm45 register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" + register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms + register "gpu_panel_power_down_delay" = "250" # T3: 25ms + register "gpu_panel_power_backlight_on_delay" = "2500" # T5: 250ms + register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms + register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" device cpu_cluster 0 on From eabb0c06f5b0053a25d9f04bc4e165bd1324cc15 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 1 Jan 2020 22:43:31 +0100 Subject: [PATCH 126/151] cpu/intel: Drop unused file Change-Id: I1b41ddc5e99838f0585089974e995f3de7be1791 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37161 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../thermal_monitoring/thermal_monitoring.h | 16 ---------------- 1 file changed, 16 deletions(-) delete mode 100644 src/cpu/intel/thermal_monitoring/thermal_monitoring.h diff --git a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h b/src/cpu/intel/thermal_monitoring/thermal_monitoring.h deleted file mode 100644 index 5bb9cc239f..0000000000 --- a/src/cpu/intel/thermal_monitoring/thermal_monitoring.h +++ /dev/null @@ -1,16 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define THERMAL_MONITORING_OFF 0 -#define THERMAL_MONITORING_SET 0x00000008 -#define MISC_ENABLE 0x01a0 From 9f78faedabba30d491e7a5b923bd57b27e986c1d Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 7 Feb 2020 18:37:26 +0100 Subject: [PATCH 127/151] intel/stm: Add platform opt-in Kconfig Selecting STM on an arbitrary platform would likely result in a brick, so let's hide the prompt by default. Change-Id: I50f2106ac05c3efb7f92fccb1e6edfbf961b68b8 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38764 Tested-by: build bot (Jenkins) Reviewed-by: Reviewed-by: Angel Pons --- src/security/intel/stm/Kconfig | 5 ++++- src/soc/intel/skylake/Kconfig | 1 + 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/security/intel/stm/Kconfig b/src/security/intel/stm/Kconfig index a74eba8522..144deeda9e 100644 --- a/src/security/intel/stm/Kconfig +++ b/src/security/intel/stm/Kconfig @@ -1,9 +1,12 @@ +config PLATFORM_SUPPORTS_STM + bool + depends on SMM_TSEG config STM bool "Enable STM" default n - depends on SMM_TSEG + depends on PLATFORM_SUPPORTS_STM select USE_BLOBS help diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 6277cea0b8..ae60a63056 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -44,6 +44,7 @@ config CPU_SPECIFIC_OPTIONS select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PLATFORM_SUPPORTS_STM select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SA_ENABLE_DPR From 8a3bc3be922766b6b9a34499dc2124f038b3f467 Mon Sep 17 00:00:00 2001 From: Joel Kitching Date: Sat, 8 Feb 2020 10:58:48 +0800 Subject: [PATCH 128/151] vboot: correct workbuf size when VBOOT_STARTS_IN_ROMSTAGE Part of the design of vboot persistent context is that the workbuf gets placed in CBMEM and stays there for depthcharge to use in kernel verification. As such, the space allocated in CBMEM needs to be at least VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. In the VBOOT_STARTS_IN_ROMSTAGE case, prior to this CL, vboot_get_context() would get invoked for the first time after CBMEM comes up, and it would only allocate VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE. Initialize the workbuf directly in vboot_setup_cbmem() instead with the correct VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE. BUG=b:124141368, chromium:994060 TEST=make clean && make test-abuild TEST=boot on GOOGLE_EVE with VBOOT_STARTS_IN_ROMSTAGE set BRANCH=none Change-Id: Ie09c39f960b3f14f3a64c648eee6ca3f23214d9a Signed-off-by: Joel Kitching Reviewed-on: https://review.coreboot.org/c/coreboot/+/38778 Reviewed-by: Aaron Durbin Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/security/vboot/common.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index aeb4498839..ffd9353260 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -86,6 +86,7 @@ int vboot_locate_firmware(struct vb2_context *ctx, struct region_device *fw) static void vboot_setup_cbmem(int unused) { + vb2_error_t rv; const size_t cbmem_size = VB2_KERNEL_WORKBUF_RECOMMENDED_SIZE; void *wb_cbmem = cbmem_add(CBMEM_ID_VBOOT_WORKBUF, cbmem_size); assert(wb_cbmem != NULL); @@ -94,9 +95,17 @@ static void vboot_setup_cbmem(int unused) * occurs before CBMEM is brought online, using pre-RAM. In order to * make vboot data structures available downstream, copy vboot workbuf * from SRAM/CAR into CBMEM. + * + * For platforms where VBOOT_STARTS_IN_ROMSTAGE, verification occurs + * after CBMEM is brought online. Directly initialize vboot data + * structures in CBMEM, which will also be available downstream. */ if (CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) - assert(vb2api_relocate(wb_cbmem, _vboot2_work, cbmem_size, - &vboot_ctx) == VB2_SUCCESS); + rv = vb2api_relocate(wb_cbmem, _vboot2_work, cbmem_size, + &vboot_ctx); + else + rv = vb2api_init(wb_cbmem, cbmem_size, &vboot_ctx); + + assert(rv == VB2_SUCCESS); } ROMSTAGE_CBMEM_INIT_HOOK(vboot_setup_cbmem) From 37bead6d26fc45f66e8032c50b3af619b246f1dc Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 9 Feb 2020 19:13:52 +0530 Subject: [PATCH 129/151] Kconfig: Guard CONFIGURABLE_RAMSTAGE This patch guards CONFIGURABLE_RAMSTAGE symbol (which is default enable for all x86 systems) with another Kconfig that can be selected by platform that actually planning to use it. TEST=CONFIG_CONFIGURABLE_RAMSTAGE is not enabled by default. Change-Id: I2113445d507294df59fbc7fb1373793b47c6c31c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38795 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 3742c04675..4253ec7d52 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -354,9 +354,13 @@ config RAMPAYLOAD Skip PCI enumeration logic and only allocate BAR for fixed devices (bootable devices, TPM over GSPI). +config HAVE_CONFIGURABLE_RAMSTAGE + bool + config CONFIGURABLE_RAMSTAGE bool "Enable a configurable ramstage." default y if ARCH_X86 + depends on HAVE_CONFIGURABLE_RAMSTAGE help A configurable ramstage allows you to select which parts of the ramstage to run. Currently, we can only select a minimal PCI scanning step. From 1cb26a6300aeac438322a0288cecfb44e977d6ae Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 9 Feb 2020 19:35:16 +0530 Subject: [PATCH 130/151] Kconfig: Add CONFIG_PCI dependency for CONFIG_MINIMAL_PCI_SCANNING Make sure MINIMAL_PCI_SCANNING has right dependency over PCI kconfig symbol. Change-Id: I30b18345976e5d21ccedf8906985ff71e7d2815c Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38801 Reviewed-by: Jeremy Soller Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 4253ec7d52..f75f94279e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -369,9 +369,9 @@ config CONFIGURABLE_RAMSTAGE config MINIMAL_PCI_SCANNING bool "Enable minimal PCI scanning" - depends on CONFIGURABLE_RAMSTAGE + depends on CONFIGURABLE_RAMSTAGE && PCI help - If this option is enabled, coreboot will scan only devices + If this option is enabled, coreboot will scan only PCI devices marked as mandatory in devicetree.cb endmenu From 32c63e050cc06e79691a7ea27f969f75fa22ed14 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Sun, 29 Dec 2019 14:44:02 +0300 Subject: [PATCH 131/151] mb/lenovo/x201/acpi_tables: Default to lid open It's really hard to power up this laptop with the lid closed so let's make it open by default, as done on many other laptops. Change-Id: I5bb2f716865c2bb569a4735f135842526043713c Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/c/coreboot/+/37985 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/lenovo/x201/acpi_tables.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 6a29ba0f64..5065648e60 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -20,6 +20,9 @@ void acpi_create_gnvs(global_nvs_t *gnvs) { + /* the lid is open by default. */ + gnvs->lids = 1; + gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; } From 804b560704f8f0a4e14c40d8fff2b41c97d42dbe Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 11 Jan 2020 03:47:59 +0100 Subject: [PATCH 132/151] sb/intel/lynxpoint: Don't use_ADR and _HID To be compliant with ACPI specification, device object requires either a _HID or _ADR, but not both. Change-Id: I45cf2b8d455aa4d288de1ac53cf9ae801f758a9a Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38351 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/southbridge/intel/lynxpoint/acpi/serialio.asl | 8 -------- 1 file changed, 8 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/acpi/serialio.asl b/src/southbridge/intel/lynxpoint/acpi/serialio.asl index 9323b91cac..88138a1d61 100644 --- a/src/southbridge/intel/lynxpoint/acpi/serialio.asl +++ b/src/southbridge/intel/lynxpoint/acpi/serialio.asl @@ -125,7 +125,6 @@ Device (SDMA) // Serial IO DMA Controller Name (_HID, "INTL9C60") Name (_UID, 1) - Name (_ADR, 0x00150000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -163,7 +162,6 @@ Device (I2C0) Name (_HID, "INT33C2") Name (_CID, "INT33C2") Name (_UID, 1) - Name (_ADR, 0x00150001) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -245,7 +243,6 @@ Device (I2C1) Name (_HID, "INT33C3") Name (_CID, "INT33C3") Name (_UID, 1) - Name (_ADR, 0x00150002) Name (SSCN, Package () { 432, 507, 30 }) Name (FMCN, Package () { 72, 160, 30 }) @@ -327,7 +324,6 @@ Device (SPI0) Name (_HID, "INT33C0") Name (_CID, "INT33C0") Name (_UID, 1) - Name (_ADR, 0x00150003) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -365,7 +361,6 @@ Device (SPI1) Name (_HID, "INT33C1") Name (_CID, "INT33C1") Name (_UID, 1) - Name (_ADR, 0x00150004) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -416,7 +411,6 @@ Device (UAR0) Name (_HID, "INT33C4") Name (_CID, "INT33C4") Name (_UID, 1) - Name (_ADR, 0x00150005) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -467,7 +461,6 @@ Device (UAR1) Name (_HID, "INT33C5") Name (_CID, "INT33C5") Name (_UID, 1) - Name (_ADR, 0x00150006) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () @@ -505,7 +498,6 @@ Device (SDIO) Name (_HID, "INT33C6") Name (_CID, "PNP0D40") Name (_UID, 1) - Name (_ADR, 0x00170000) // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () From 12e9c5ee86f9aa87b1e84bfc59e6cdbab5a4b254 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 9 Feb 2020 14:30:26 -0700 Subject: [PATCH 133/151] Makefile.inc: Ignore _HID & _ADR conflicts in Broadwell & Lynxpoint We haven't been able to update IASL in 8 months because of this conflict. Ignoring it doesn't make things any worse than they are now. Signed-off-by: Martin Roth Change-Id: Iced2e55e9f2aa7a262a5c1ffeff32af78acfa35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38810 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Paul Menzel --- Makefile.inc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 4ca173b866..2690e8f462 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -261,7 +261,16 @@ EMPTY_RESOURCE_TEMPLATE_WARNING = 3150 # Redundant offset remarks are not useful in any way and are masking useful # ones that might indicate an issue so it is better to hide them. REDUNDANT_OFFSET_REMARK = 2158 +# Ignore _HID & _ADR coexisting in Intel Lynxpoint and Broadwell ASL code. +# See cb:38803 & cb:38802 +# "Multiple types (Device object requires either a _HID or _ADR, but not both)" +MULTIPLE_TYPES_WARNING = 3073 + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT)$(CONFIG_SOC_INTEL_BROADWELL),y) +IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) -vw $(MULTIPLE_TYPES_WARNING) +else IGNORED_IASL_WARNINGS = -vw $(EMPTY_RESOURCE_TEMPLATE_WARNING) -vw $(REDUNDANT_OFFSET_REMARK) +endif define asl_template $(CONFIG_CBFS_PREFIX)/$(1).aml-file = $(obj)/$(1).aml From e6db9105ec9b0e85df93d290deb233a43e53a569 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 3 Feb 2020 14:57:40 +0100 Subject: [PATCH 134/151] soc/intel/common/block/lpc: Add lpc_get_fixed_io_decode Add function to return the fixed io decode ranges contained in register 0x80 of the LPC interface. BUG=N/A TEST=build Change-Id: Ie46d7c9d7a399a8489c030d906f75ba61db19cc4 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38745 Reviewed-by: Frans Hendriks Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/include/intelblocks/lpc_lib.h | 2 ++ src/soc/intel/common/block/lpc/lpc_lib.c | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h index f77b8d5d71..cf6d8e9bdc 100644 --- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h +++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h @@ -70,6 +70,8 @@ struct lpc_mmio_range { * Output:I/O Enable Bits */ uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables); +/* Return the current decode settings */ +uint16_t lpc_get_fixed_io_decode(void); /* Open a generic IO window to the LPC bus. Four windows are available. */ void lpc_open_pmio_window(uint16_t base, uint16_t size); /* Close all generic IO windows to the LPC bus. */ diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index bc89e4ccae..3ad2176c11 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -37,6 +37,11 @@ uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) return io_enables; } +uint16_t lpc_get_fixed_io_decode(void) +{ + return pci_read_config16(PCH_DEV_LPC, LPC_IO_DECODE); +} + /* * Find the first unused IO window. * Returns -1 if not found, 0 for reg 0x84, 1 for reg 0x88 ... From 737b77c4bb437370c0134ae6ff263ac4ca3c2f81 Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Wed, 5 Feb 2020 12:15:39 +0100 Subject: [PATCH 135/151] mb/facebook/monolith: Enable the 2nd EC UART at 0x2f8 BUG=N/A TEST=tested on facebook monolith Change-Id: I36e652e66c66eeb770a5a5d987bb57c7eaa11382 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38749 Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/mainboard/facebook/monolith/Kconfig | 1 + .../facebook/monolith/acpi/superio.asl | 25 +++++++++++++++++++ src/mainboard/facebook/monolith/com_init.c | 11 +++++--- 3 files changed, 33 insertions(+), 4 deletions(-) diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 0ae704d3c3..203f8a5d25 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_IFD_GBE_REGION select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_LPC_COMB_ENABLE config CBFS_SIZE hex "CBFS_SIZE" diff --git a/src/mainboard/facebook/monolith/acpi/superio.asl b/src/mainboard/facebook/monolith/acpi/superio.asl index 0f5790da8d..537d9f8419 100644 --- a/src/mainboard/facebook/monolith/acpi/superio.asl +++ b/src/mainboard/facebook/monolith/acpi/superio.asl @@ -43,3 +43,28 @@ Device (COM1) { EndDependentFn () }) } + +Device (COM2) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 2) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + FixedIO (0x02F8, 0x08) + IRQNoFlags () {3} + }) + + Name (_PRS, ResourceTemplate () + { + StartDependentFn (0, 0) { + FixedIO (0x02F8, 0x08) + IRQNoFlags () {3} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/facebook/monolith/com_init.c b/src/mainboard/facebook/monolith/com_init.c index f19aba311c..d2519fa26d 100644 --- a/src/mainboard/facebook/monolith/com_init.c +++ b/src/mainboard/facebook/monolith/com_init.c @@ -19,11 +19,14 @@ #include #include "onboard.h" -#define SERIAL_DEV PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ +#define SERIAL_DEV1 PNP_DEV(ITE8528_CMD_PORT, 1) /* ITE8528 UART1 */ +#define SERIAL_DEV2 PNP_DEV(ITE8528_CMD_PORT, 2) /* ITE8528 UART2 */ void bootblock_mainboard_early_init(void) { - /* Enable the serial port inside the EC */ - pnp_set_logical_device(SERIAL_DEV); - pnp_set_enable(SERIAL_DEV, 1); + /* Enable the serial ports inside the EC */ + pnp_set_logical_device(SERIAL_DEV1); + pnp_set_enable(SERIAL_DEV1, 1); + pnp_set_logical_device(SERIAL_DEV2); + pnp_set_enable(SERIAL_DEV2, 1); } From 6cd5243295acf780d2b82312ba8955669e606cee Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Mon, 3 Feb 2020 14:41:46 +0100 Subject: [PATCH 136/151] arch/x86/acpi: Change message in acpi_write_dbg2_pci_uart to BIOS_DEBUG When acpi_write_dbg2_pci_uart is called and no pci uart is available the function prints "Device not found" as an error. This is not correct. Change the error level to BIOS_DEBUG so coreboot reports the device is not available but doesn't flag this as an error. BUG=N/A TEST=build Change-Id: I14567bcfcf5a6ff427e418d15bc2675ae7a28f53 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/38744 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Paul Menzel --- src/arch/x86/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 2f793b4cb2..6dab3733cc 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -946,7 +946,7 @@ unsigned long acpi_write_dbg2_pci_uart(acpi_rsdp_t *rsdp, unsigned long current, acpi_addr_t address; if (!dev) { - printk(BIOS_ERR, "%s: Device not found\n", __func__); + printk(BIOS_DEBUG, "%s: Device not found\n", __func__); return current; } if (!dev->enabled) { From 5a1ba1bc291e1db409ee302762222095fc24deff Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Thu, 19 Dec 2019 10:57:33 -0700 Subject: [PATCH 137/151] Documentation/soc/amd: Add PSP integration information Change-Id: I05187365158eb5c055be0d4a32f41324d2653f71 Signed-off-by: Marshall Dawson Reviewed-on: https://review.coreboot.org/c/coreboot/+/37847 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- Documentation/soc/amd/family15h.md | 1 + Documentation/soc/amd/family17h.md | 18 +- Documentation/soc/amd/index.md | 1 + Documentation/soc/amd/psp_integration.md | 376 +++++++++++++++++++++++ 4 files changed, 387 insertions(+), 9 deletions(-) create mode 100755 Documentation/soc/amd/psp_integration.md diff --git a/Documentation/soc/amd/family15h.md b/Documentation/soc/amd/family15h.md index fc41e91de2..5a8f95d601 100644 --- a/Documentation/soc/amd/family15h.md +++ b/Documentation/soc/amd/family15h.md @@ -47,3 +47,4 @@ structure. 3. [Models 30h-3Fh BKDG](https://www.amd.com/system/files/TechDocs/49125_15h_Models_30h-3Fh_BKDG.pdf) 4. [Models 60h-6Fh BKDG](https://www.amd.com/system/files/TechDocs/50742_15h_Models_60h-6Fh_BKDG.pdf) 5. [Models 70h-7Fh BKDG](https://www.amd.com/system/files/TechDocs/55072_AMD_Family_15h_Models_70h-7Fh_BKDG.pdf) +6. [PSP Integration](psp_integration.md) diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index dc3de13ffe..9608b57325 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -18,8 +18,8 @@ To the extent necessary, the role of the Platform Security Processor (a.k.a. PSP) in system initialization is addressed here. AMD has historically required an NDA for access to the PSP specification1. coreboot relies on util/amdfwtool to build -the structures and add various other firmware to the final image. The -Family 17h PSP design guide adds a new BIOS Directory Table, similar to +the structures and add various other firmware to the final image2. +The Family 17h PSP design guide adds a new BIOS Directory Table, similar to the PSP Directory Table. Support in coreboot for modern AMD products is based on AMD’s @@ -29,12 +29,12 @@ configuring proprietary core logic, assistance with generating ACPI tables, and other features. AGESA for products earlier than Family 17h is known as v5 or -Arch20082. Also note that coreboot currently contains both +Arch20083. Also note that coreboot currently contains both open source AGESA and closed source implementations (binaryPI) compiled from AGESA. The first AMD Family 17h device ported to coreboot is codenamed -“Picasso”3, and will be added to soc/amd/picasso. +“Picasso”4, and will be added to soc/amd/picasso. ## Additional Definitions @@ -207,7 +207,7 @@ the existing v5 interface impractical. Given the UEFI nature of modern AGESA, and the existing open source work from Intel, Picasso shall support AGESA via an FSP-like prebuilt -image. The Intel Firmware Support Package4 combines +image. The Intel Firmware Support Package5 combines reference code with EDK II source to create a modular image with discoverable entry points. coreboot source already contains knowledge of FSP, how to parse it, integrate it, and how to communicate with it. @@ -218,7 +218,7 @@ of FSP, how to parse it, integrate it, and how to communicate with it. for AMD Family 17h Processors” (PID #55758) and “AMD Platform Security Processor BIOS Architecture Design Guide” (PID #54267) for earlier products -2. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf) -3. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso) -4. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html) - +2. [PSP Integration](psp_integration.md) +3. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf) +4. [https://en.wikichip.org/wiki/amd/cores/picasso](https://en.wikichip.org/wiki/amd/cores/picasso) +5. [https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html](https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html) diff --git a/Documentation/soc/amd/index.md b/Documentation/soc/amd/index.md index 80413b0937..e4fa6c9337 100644 --- a/Documentation/soc/amd/index.md +++ b/Documentation/soc/amd/index.md @@ -6,6 +6,7 @@ This section contains documentation about coreboot on specific AMD SOCs. - [Family 15h](family15h.md) - [Family 17h](family17h.md) +- [Platform Security Processor Integration](psp_integration.md) ## amd_blobs Repository License diff --git a/Documentation/soc/amd/psp_integration.md b/Documentation/soc/amd/psp_integration.md new file mode 100755 index 0000000000..5f53a39f05 --- /dev/null +++ b/Documentation/soc/amd/psp_integration.md @@ -0,0 +1,376 @@ +# AMD Platform Security Processor (PSP) Firmware Integration Guide + +The following content defines the structures of PSP tables and describes the +firmware images integrated into a functioning system. Further details of +each Platform Security Processor (PSP) firmware blob or PSP feature are +beyond the scope of this document, and may be found in AMD NDA publications. + +The current name for the security technology is "AMD Secure Processor". +To be consistent with the latest documentation, and because of familiarity +with the older name, this document continues with "Platform Security Processor" +and "PSP". + +## Platform Security Processor (PSP) Overview + +The Platform Security Processor (PSP) is an on-die, isolated security processor +that runs independently from the main x86 cores of the platform. +Security-sensitive components run on the PSP without being affected by the +commodity or untrusted software running on the x86 cores. The PSP executes +its own firmware and shares the SPI flash storage that is used by the +system BIOS. + +## Embedded Firmware Structure + +The PSP identifies its important tables by first locating the Embedded Firmware +Structure. It reads specific addresses in the SPI flash, from top to bottom, +attempting to identify the signature. The locations (for clarity, the x86 +physical addresses) checked are: +* 0xfffa0000 +* 0xfff20000 +* 0xffe20000 +* 0xffc20000 +* 0xff820000 +* 0xff020000 + +Most coreboot implementations provide flexibility to position the structure in +any of the eligible locations. Below are typical definitions within the +structure (for all families combined). Individual features supported vary by +family and model. + + +--------------+---------------+------------------+----------------------------+ + | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | + +--------------+---------------+------------------+----------------------------+ + | Signature | 0x00 | 4 | 0x55aa55aa | + |--------------|---------------|------------------|----------------------------| + | IMC FW | 0x04 | 4 | Integrated Micro | + | | | | Controller: unsupported | + | | | | but functional in some | + | | | | systems | + |--------------|---------------|------------------|----------------------------| + | GbE FW | 0x08 | 4 | Gigabit Ethernet | + |--------------|---------------|------------------|----------------------------| + | xHCI FW | 0x0c | 4 | xHCI firmware | + |--------------|---------------|------------------|----------------------------| + | PSP Dir Tbl | 0x10 | 4 | Pointer to PSP Directory | + | | | | Table (early devices) | + |--------------|---------------|------------------|----------------------------| + | PSP Dir Tbl | 0x14 | 4 | Pointer to PSP Directory | + | | | | Table (later devices and | + | | | | is combo capable) | + |--------------|---------------|------------------|----------------------------| + | BIOS Dir Tbl | 0x18 | 4 | Pointer to BIOS Directory | + | | | | Table for models n* | + |--------------|---------------|------------------|----------------------------| + | BIOS Dir Tbl | 0x1c | 4 | Pointer to BIOS Directory | + | | | | Table for models nn | + |--------------|---------------|------------------|----------------------------| + | BIOS Dir Tbl | 0x20 | 4 | Pointer to BIOS Directory | + | | | | Table for models nnn | + |--------------|---------------|------------------|----------------------------| + | … | | | ... | + +--------------+---------------+------------------+----------------------------+ + +* The Embedded Firmware Structure may support pointers to multiple generations + of devices, e.g. Family 17h Models 00h-0Fh, Family 17h Models 10h-1Fh, etc. + Details are specific to the implementation. + +## PSP Directory Table + +The PSP Directory Table allows the PSP to find and load various images. A +second level table may be generated to allow updates without the risk of +corrupting the primary table. Certain models support a combo type table, +allowing secondary tables to be referenced by device ID. No coreboot +implementations currently use combo tables. + +### PSP Directory Table Header + + +--------------+---------------+------------------+----------------------------+ + | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | + +--------------+---------------+------------------+----------------------------+ + | PSP Cookie | 0x00 | 4 | PSP cookie "$PSP" to | + | | | | recognize the header. | + | | | | Cookie “$PL2” for level 2 | + |--------------|---------------|------------------|----------------------------| + | Checksum | 0x04 | 4 | 32-bit CRC value of header | + | | | | below this field and | + | | | | including all entries | + |--------------|---------------|------------------|----------------------------| + | Total Entries| 0x08 | 4 | Number of PSP Directory | + | | | | entries in the table | + |--------------|---------------|------------------|----------------------------| + | Reserved | 0x0C | 4 | Reserved - Set to zero | + +--------------+---------------+------------------+----------------------------+ + +### PSP Directory Table Entries + + +--------------+---------------+------------------+----------------------------+ + | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | + +--------------+---------------+------------------+----------------------------+ + | Type | 0x00 | 8 | Entry type (see below) | + |--------------|---------------|------------------|----------------------------| + | Sub Program | 0x01 | 8 | Specifies sub program | + |--------------|---------------|------------------|----------------------------| + | Reserved | 0x02 | 16 | Reserved - set to 0 | + |--------------|---------------|------------------|----------------------------| + | Size | 0x04 | 32 | Size of PSP entry in bytes | + |--------------|---------------|------------------|----------------------------| + | Location / | 0x08 | 64 | Location: Physical Address | + | Value | | | of SPIROM location where | + | | | | corresponding PSP entry | + | | | | located. | + | | | | | + | | | | Value: 64-bit value for the| + | | | | PSP Entry | + +--------------+---------------+------------------+----------------------------+ + +### PSP Directory Table Types + +**0x00**: AMD public key +* Public key used by on-chip bootcode to verify the signature of PSP boot + loader firmware. + +**0x01**: PSP boot loader firmware +* Second stage boot loader firmware to be loaded by on-chip bootcode. + +**0x02**: PSP SecureOS firmware +* Off-chip PSP boot loader will be overwritten in SRAM by the Secure/Trusted + OS during initial boot up. +* PSP SecureOS performs: + * Initialization of OS internal structures and instantiates the fTPM as a + trusted application + * Sets up CPU/BIOS-PSP interface registers + * Enters steady state idling and waiting for commands + * In steady state, on notification, prepares for S3 state + * Verify and loading GFX Firmware + +**0x03**: PSP recovery boot loader firmware +* Recovery PSP boot loader image, loaded by on-chip bootcode in case of + failure in loading PSP boot loader. + +**0x08**: SMU off-chip firmware + +**0x12**: SMU off-chip firmware section 2 +* Power Management firmware, responsible for system power/clock management. + +**0x09**: Secure Debug unlock public key +* Public key token used during Secure Debug unlock process to verify message + payload from AMD server. + +**0x0b**: Soft fuse chain +* Refer to documentation for definitions. (See External References below.) + +**0x0c**: PSP trustlet binaries +* Optional file to enable fTPM. + +**0x13**: PSP Secure Debug unlock debug image +* Secure Debug unlock firmware image, used to unlock the device. + +**0x21**: Wrapped iKEK +* Intermediate Key Encryption Key, used to decrypt encrypted firmware images. + This is mandatory in order to support encrypted firmware. + +**0x24**: Security policy binary +* A security policy is applied to restrict the untrusted access to security + sensitive regions. + +**0x25**: MP2 firmware +* The MP2 of the SMU, also known as the Sensor Fusion Integration is used to + aggregate the data from various sensors such as accelerometer, gyrometer, + ambient light sensor, orientation sensor, etc. This is off-chip firmware + for Sensor Fusion Processor (SFP) subsystem of the SMU. + +**0x28**: System driver +* Driver executing on top of SecureOS. + +**0x30 - 0x37**: PSP AGESA binaries +* AGESA Boot Loaders (ABLs) are a set of binary images executed by the PSP. + They are responsible for initializing APU silicon components (including but + not limited to APU memory interface) on S5, S4 and S3, prior to releasing + the main cores from reset. + +**0x3a**: Whitelist +* Optional image containing a signed whitelist of one or more serial numbers. + +**0x40**: Pointer to secondary table +* Pointer to PSP Directory Table level 2. + +**0x52**: PSP boot loader usermode OEM application +* Supported only in certain SKUs. + +**0x22**: PSP Token Unlock data +* Used to support time-bound Secure Debug unlock during boot. This entry may + be omitted if the Token Unlock debug feature is not required. + +### Firmware Version of Binaries + +Every firmware binary contains 256 bytes of a PSP Header, which includes +the firmware version. The version is made up of the four bytes located at +offset 0x60 in the binary image. + +For example, in the PSP BootLoader: + + 0000000: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 0000010: 2450 5331 c0e1 0000 0100 0000 0000 0000 $PS1............ + 0000020: 5c0a ddb8 b279 4846 e154 aa4c ed7d 414d \....yHF.T.L.}AM + 0000030: 0100 0000 0000 0000 60bb a67e 1a43 4c6b ........`..~.CLk + 0000040: 9807 bc8d fdb4 1f40 0000 0000 0000 0000 .......@........ + 0000050: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 0000060: 7401 0800 ffff ffff 0001 0000 c0e3 0000 t............... + 0000070: 0000 0000 0000 0000 0000 0000 0100 0000 ................ + 0000080: 4766 9186 9d5f e909 492d 491d d9ee 8e6c Gf..._..I-I....l + 0000090: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 00000a0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 00000b0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 00000c0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 00000d0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 00000e0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + 00000f0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ + +The PSP BootLoader version is 00.08.01.74. + +Note that only Firmware binary images have versions. Key tokens are not +versioned, as there will not be multiple keys. Keys are unique to processor +family. + +### BIOS Directory Table Entry Types + +All x86 accessible components (both executable and data blobs) are found via +the BIOS Directory Table. A second level table may be generated to allow for +updates without the risk of corrupting the primary table. + +The BIOS Directory table structure is slightly different from the PSP Directory: +* Multiple instances of firmware components are allowed for one specific type +* The type field is further structured to reflect attributes of BIOS + components such as "Region Type", "Reset Image", "Copy Image", "Read Only", + allowing design flexibility +* The "Destination Address" field is added for specific entries that are + expected to be copied from boot media to specific memory location + +### BIOS Directory Table Header + + +--------------+---------------+------------------+----------------------------+ + | Field Name | Offset (Hex) | Size (In Bytes) | Description/Purpose | + +--------------+---------------+------------------+----------------------------+ + | BIOS Cookie | 0x00 | 4 | BIOS cookie "$BHD" to | + | | | | recognize the header. | + | | | | Cookie “$BL2” for level 2 | + |--------------|---------------|------------------|----------------------------| + | Checksum | 0x04 | 4 | 32 bit CRC value of header | + | | | | below this field and | + | | | | including all entries | + |--------------|---------------|------------------|----------------------------| + | Total Entries| 0x08 | 4 | Number of BIOS Directory | + | | | | entries in the table | + |--------------|---------------|------------------|----------------------------| + | Reserved | 0x0C | 4 | Reserved - Set to zero | + +--------------+---------------+------------------+----------------------------+ + +### BIOS Directory Table Entries + + +--------------+---------------+------------------+----------------------------+ + | Field Name | Offset (Hex) | Size (In Bits) | Description/Purpose | + +--------------+---------------+------------------+----------------------------+ + | Type | 0x00 | 8 | Entry type (see below) | + |--------------|---------------|------------------|----------------------------| + | Region Type | 0x01 | 8 | Setup the memory region's | + | | | | security attribute for the | + | | | | BIOS entry | + |--------------|---------------|------------------|----------------------------| + | Reset Image | 0x02[0] | 1 | Boolean value to define the| + | | | | BIOS entry is a reset | + | | | | binary image | + |--------------|---------------|------------------|----------------------------| + | Copy Image | 0x02[1] | 1 | Define the binary image of | + | | | | the BIOS entry is for | + | | | | copying over to the memory | + | | | | region | + |--------------|---------------|------------------|----------------------------| + | Read Only | 0x02[2] | 1 | Setup the memory region for| + | | | | the BIOS entry to read only| + |--------------|---------------|------------------|----------------------------| + | Compressed | 0x02[3] | 1 | Compressed using zlib | + | | | | | + |--------------|---------------|------------------|----------------------------| + | Instance | 0x02[7:4] | 4 | Specify the Instance of an | + | | | | entry | + |--------------|---------------|------------------|----------------------------| + | SubProgram | 0x03[2:0] | 3 | Specify the SubProgram | + |--------------|---------------|------------------|----------------------------| + | Reserved | 0x03[7:3] | 5 | Reserved - Set to zero | + |--------------|---------------|------------------|----------------------------| + | Size | 0x04 | 32 | Memory Region Size | + |--------------|---------------|------------------|----------------------------| + | Source | 0x08 | 64 | Physical Address of SPIROM | + | Address | | | location where the data for| + | | | | the corresponding entry is | + | | | | located | + |--------------|---------------|------------------|----------------------------| + | Destination | 0x10 | 64 | Destination Address of | + | Address | | | memory location where the | + | | | | data for the corresponding | + | | | | BIOS Entry is copied | + +--------------+---------------+------------------+----------------------------+ + +### BIOS Directory Table Entry Types + +**0x60**: APCB data +* Source field points to the AGESA PSP Customization Block (APCB) data. + +**0x68**: Backup copy of APCB data +* Source field points to the backup copy of the AGESA PSP Customization Block + (APCB) data. + +**0x61**: APOB data +* Location field points to the AGESA PSP Output Block (APOB) data. + +**0x62**: BIOS reset image +* Source field points to BIOS binary image in flash. Destination points to + DRAM. + +**0x63**: APOB data NV +* Source field points to the AGESA PSP Output Block (APOB) data NV copy. + This data is written by coreboot and replayed by PSP ABLs during S3 resume + and in certain S5 boots. + +**0x64**: PMU firmware (instruction) +* Source field points to the instruction portion of Phy Microcontroller Unit + firmware. + +**0x65**: PMU firmware (data) +* Source field points to the data portion of Phy Microcontroller Unit + firmware. + +**0x66**: x86 microcode patch +* Source field points to the microcode patch. + +**0x6a**: MP2 FW config file +* Source field points to the MP2 FW configuration file. + +**0x70**: Pointer to secondary table +* Pointer to BIOS Directory Table level 2. + +## Tools + +### amdcompress + +`cbfstool/amdcompress` is a helper for creating the BIOS Reset Image (BIOS +Directory Table type 0x62). This is the code the PSP uncompresses into DRAM +at the location where the x86 begins execution when released from reset. +Typical usage is for amdcompress to convert an ELF file’s program section +into a zlib compressed image. + +### amdfwtool + +All images requiring PSP functionality rely on the amdfwtool utility. +amdfwtool takes image names as command-line arguments, as well as the size of +the flash device, and intended location of the Embedded Firmware Structure. +Its output is a monolithic image with correctly positioned headers, pointers, +structures, and the firmware images added. The file, typically named +`amdfw.rom`, may then be added directly into the coreboot image. + +## External Reference + +* NDA document #55758: *AMD Platform Security Processor BIOS Architecture + Design Guide for AMD Family 17h Processors* +* NDA document #54267 *AMD Platform Security Processor BIOS Architecture + Design Guide*: For all devices earlier than Family 17h From 5b43484db3b41ec2b9664ef73b7e613eed813374 Mon Sep 17 00:00:00 2001 From: Marshall Dawson Date: Tue, 4 Feb 2020 17:16:27 -0700 Subject: [PATCH 138/151] Documentation/soc/amd/family17: Update to match current design The Picasso no longer intends to implement a hybrid romstage, opting instead for a more traditional bootblock/romstage/ramstage. Update the documentation to reflect this. Clarify additional details that have come to light since the last revision. Signed-off-by: Marshall Dawson Change-Id: I6c98c007ddb8a4a05810f19e4215bde719de7bb8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38713 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- Documentation/soc/amd/family17h.md | 117 +++++++++++++++++------------ 1 file changed, 71 insertions(+), 46 deletions(-) diff --git a/Documentation/soc/amd/family17h.md b/Documentation/soc/amd/family17h.md index 9608b57325..b917c94526 100755 --- a/Documentation/soc/amd/family17h.md +++ b/Documentation/soc/amd/family17h.md @@ -14,13 +14,12 @@ Family 17h products are x86-based designs. This documentation assumes familiarity with x86, its reset state and its early initialization requirements. -To the extent necessary, the role of the Platform Security Processor -(a.k.a. PSP) in system initialization is addressed here. AMD has -historically required an NDA for access to the PSP -specification1. coreboot relies on util/amdfwtool to build -the structures and add various other firmware to the final image2. -The Family 17h PSP design guide adds a new BIOS Directory Table, similar to -the PSP Directory Table. +To the extent necessary, the role of the AMD Secure Processor (a.k.a. +Platform Security Processor or PSP) in system initialization is addressed +here. The PSP specification1 is available only with an NDA. +coreboot relies on util/amdfwtool to build the structures and add various +other firmware to the final image2. The Family 17h PSP design +guide adds a new BIOS Directory Table, similar to the PSP Directory Table. Support in coreboot for modern AMD products is based on AMD’s reference code: AMD Generic Encapsulated Software Architecture @@ -51,8 +50,13 @@ related firmware images * Embedded Firmware Structure - Signature and pointers used by the PSP to locate the PSP Directory Table and BIOS Directory Table; these items are generated during coreboot build and are located in the SPI ROM -* Verstage - The code to verify the firmware contained in the -writable section of the SPI ROM +* vboot - The generic technology name for verifying/choosing a RW A/B +or fallback RO path. +* verstage - The code (vboot) to verify the firmware contained in the +writable section of the SPI ROM, traditionally run on the x86 processor, +and in some cases a separate stage added to coreboot +* vboot app - A portion of vboot technology designed and compiled +to run on the PSP * APCB - AMD PSP Customization Block - A binary containing PSP and system configuration preferences (analogous to v5 BUILDOPT_ options), and generated by APCBTool to be added to coreboot/utils later @@ -90,7 +94,8 @@ dependency expressions, much functionality is rewritten as libraries, etc. It would, in no way, fit into the v5 model used in coreboot. * For the foreseeable future, AGESA source will distributed only -under NDA. +under NDA. Furthermore, because AGESA's integrated debug services divulge +NDA information, no debug builds will be released to the general public. ## Basic Pre-x86 Boot Flow @@ -102,15 +107,15 @@ The following steps occur prior to x86 processor operation. the SPI ROM * PSP verifies and executes the PSP off-chip bootloader * ChromeOS systems: - * Off-chip bootloader attempts to locate verstage via the RO BIOS + * Off-chip bootloader attempts to locate vboot app via the RO BIOS Directory Table - * If verstage is not found, booting continues with ABLs below - * Verstage initializes, setting up GPIOs, UART if needed, + * If vboot app is not found, booting continues with ABLs below + * vboot app initializes, setting up GPIOs, UART if needed, communication path to the EC, and the SPI controller for direct access to the flash device. - * Verstage verifies the RW sections (as is typically performed by + * vboot app verifies the RW sections (as is typically performed by the main processor) - * Verstage locates the Embedded Firmware Directory within the + * vboot app locates the Embedded Firmware Directory within the verified FMAP section and passes a pointer to the PSP bootloader. If the verification fails, it passes a pointer to the RO header to the bootloader. @@ -166,44 +171,61 @@ jump to protected mode must jump to the physical address in DRAM. Any code that is position-dependent must be linked to run at the final destination. -## Initial coreboot Implementation +## Implementation for coreboot -Supporting Picasso doesn’t fit well with many of the coreboot -assumptions. Initial porting shall attempt to fit within existing -coreboot paradigms and make minimal changes to common code. +Supporting Picasso doesn’t fit perfectly with many of the coreboot +assumptions about x86 processors. Changes are introduced primarily +into arch/x86 to accommodate a processor starting in DRAM and at a +nontraditional reset vector. -### CAR and bootblock +### CAR and early stages -The coreboot bootblock contains features Picasso doesn’t require or -can’t use, and is assumed to execute in an unusable location. -Picasso’s requirement for bootblock in coreboot will be eliminated. +The traditional coreboot bootblock and romstage rely on cache-as-RAM +and a linker script that positions temporary storage accordingly. A +substitute for the DCACHE variables, called EARLYRAM, is introduced. +Like DCACHE, this allows for a consistent mapping of early regions +required across multiple stages prior to cbmem coming online. +Examples are the _preram_cbmem_console and _timestamp. -### Hybrid romstage +Due to Picasso's unique nature of starting with DRAM already available, +no early stages run as execute-in-place (XIP). All post-bootblock +stages are copied from the BIOS flash into DRAM for faster +performance, and these regions are marked reserved later in POST. -Picasso’s x86 reset state doesn’t meet the coreboot expectations -for jumping directly to ramstage. The primary feature of romstage is -also not needed, however there are other important features that are -typically in romstage that Picasso does need. +Unlike CAR-based systems, and because Picasso does not run early +stages as XIP, its early stages are not constrained in their use +of .bss or .data sections. All stages' .bss is zeroed, and all +.data sections are fully R/W at load time. -The romstage architecture is designed around the presence of CAR. -Several features implement ROMSTAGE_CBMEM_INIT_HOOK, expecting to move -data from CAR to cbmem. The hybrid romstage consumes DRAM for the -purpose of implementing the expected CAR storage. This region as well -as the DRAM where romstage is decompressed must be reserved and -unavailable to the OS. +### bootblock -The initial Picasso port implements a hybrid romstage that contains the -first instruction fetched at the reset vector. It minimally configures -flat protected mode, initializes cbmem, then loads the next stage. -Future work will consider breaking the dependencies mentioned above -and/or potentially loading ramstage directly from the PSP. +Picasso uses a bootblock that mirrors a traditional bootblock as much +as possible. Because the image is loaded by the PSP, the bootblock is +not restricted to the top of the BIOS flash device. The compressed +image is added into the PSP's `amdfw.rom` build. + +### vboot app and verstage + +Development is currently underway for the vboot app, and potentially +an x86-based verstage companion. This document shall be updated once +the design is finalized and functioning. Support for the PSP honoring +the presence of the vboot app is available only in certain SKUs. + +### romstage and postcar + +A traditional romstage is maintained for Picasso. The primary reason for +this choice is to remain compatible with coreboot conventions and +to support the FSP 2.0 driver. Picasso's romstage uses an +fsp_memory_init() call to glean the memory map from AGESA. (See below.) +fsp_memory_init() brings cbmem online before returning to the caller. + +No postcar stage is required or supported. ## AGESA v9 on Picasso -Due to the current inability to publish AGESA source, a pre-built -binary solution remains a requirement. The rewrite from v5 to v9 for -direct inclusion into UEFI source makes modifying it for conforming to -the existing v5 interface impractical. +Due to the current restriction on publishing AGESA source, a pre-built +binary solution remains a requirement. Modifying v9 to conform to the +existing v5 binaryPI interface was considered impractical. Given the UEFI nature of modern AGESA, and the existing open source work from Intel, Picasso shall support AGESA via an FSP-like prebuilt @@ -211,12 +233,15 @@ image. The Intel Firmware Support Package5 combines reference code with EDK II source to create a modular image with discoverable entry points. coreboot source already contains knowledge of FSP, how to parse it, integrate it, and how to communicate with it. +Picasso's FSP is compatible with rev. 2.0 of the External Architecture +Specification. Deviations, e.g., no FSP-T support, shall be published +in an Integration Guide. ## Footnotes -1. “AMD Platform Security Processor BIOS Architecture Design Guide -for AMD Family 17h Processors” (PID #55758) and “AMD Platform -Security Processor BIOS Architecture Design Guide” (PID #54267) for +1. *AMD Platform Security Processor BIOS Architecture Design Guide +for AMD Family 17h Processors* (PID #55758) and *AMD Platform +Security Processor BIOS Architecture Design Guide* (PID #54267) for earlier products 2. [PSP Integration](psp_integration.md) 3. [https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf](https://www.amd.com/system/files/TechDocs/44065_Arch2008.pdf) From 75f0124c44a26aa2d71bb3cba7cdc42e224980ce Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 4 Feb 2020 20:40:47 -0800 Subject: [PATCH 139/151] mb/google/volteer: use new Tiger Lake memory config Some of the common memory code that was being performed in mainboard has moved into the soc to reduce redundant code. This change adapts volteer to use Tiger Lake's new common code. BUG=b:145642089, b:145238504, b:145564831 BRANCH=none TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot volteer, boot to kernel, "cat /proc/meminfo" and verify it reports "MemTotal: 8038196 kB". Change-Id: I32c9b8a040728d44565806eece6cf60b6b6073b6 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/38715 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/volteer/Makefile.inc | 1 + src/mainboard/google/volteer/romstage.c | 29 +++++++++ .../volteer/variants/baseboard/Makefile.inc | 2 + .../baseboard/include/baseboard/variants.h | 2 + .../volteer/variants/baseboard/memory.c | 59 +++++++++++++++++++ 5 files changed, 93 insertions(+) create mode 100644 src/mainboard/google/volteer/romstage.c create mode 100644 src/mainboard/google/volteer/variants/baseboard/memory.c diff --git a/src/mainboard/google/volteer/Makefile.inc b/src/mainboard/google/volteer/Makefile.inc index 6b5c065e1e..1b6b880806 100644 --- a/src/mainboard/google/volteer/Makefile.inc +++ b/src/mainboard/google/volteer/Makefile.inc @@ -9,6 +9,7 @@ bootblock-y += bootblock.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-y += romstage.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c new file mode 100644 index 0000000000..7e87a2ad78 --- /dev/null +++ b/src/mainboard/google/volteer/romstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + const struct mb_lpddr4x_cfg *board_cfg = variant_memory_params(); + const struct spd_info spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = variant_memory_sku(), + }; + bool half_populated = gpio_get(GPIO_MEM_CH_SEL); + + meminit_lpddr4x_dimm0(mem_cfg, board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc index 30f2b4605a..87a8667bc6 100644 --- a/src/mainboard/google/volteer/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/volteer/variants/baseboard/Makefile.inc @@ -8,6 +8,8 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c smm-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h index df4368bb0e..3f8597f9f4 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/variants.h @@ -10,6 +10,7 @@ #define __BASEBOARD_VARIANTS_H__ #include +#include #include #include @@ -23,6 +24,7 @@ const struct pad_config *variant_override_gpio_table(size_t *num); const struct cros_gpio *variant_cros_gpios(size_t *num); +const struct mb_lpddr4x_cfg *variant_memory_params(void); int variant_memory_sku(void); #endif /* __BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/volteer/variants/baseboard/memory.c b/src/mainboard/google/volteer/variants/baseboard/memory.c new file mode 100644 index 0000000000..111719871d --- /dev/null +++ b/src/mainboard/google/volteer/variants/baseboard/memory.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2020 The coreboot project Authors. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include + +static const struct mb_lpddr4x_cfg baseboard_memcfg = { + /* DQ byte map */ + .dq_map = { + { 0, 1, 2, 3, 4, 5, 6, 7, /* Byte 0 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ + { 7, 2, 6, 3, 5, 1, 4, 0, /* Byte 2 */ + 10, 8, 9, 11, 15, 12, 14, 13 }, /* Byte 3 */ + { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 4 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 5 */ + { 7, 0, 1, 6, 5, 4, 2, 3, /* Byte 6 */ + 15, 14, 8, 9, 10, 12, 11, 13 }, /* Byte 7 */ + { 3, 2, 1, 0, 4, 5, 6, 7, /* Byte 0 */ + 12, 13, 14, 15, 11, 10, 9, 8 }, /* Byte 1 */ + { 3, 4, 2, 5, 0, 6, 1, 7, /* Byte 2 */ + 13, 12, 11, 10, 14, 15, 9, 8 }, /* Byte 3 */ + { 3, 2, 1, 0, 7, 4, 5, 6, /* Byte 4 */ + 15, 14, 13, 12, 8, 9, 10, 11 }, /* Byte 5 */ + { 3, 4, 2, 5, 1, 0, 7, 6, /* Byte 6 */ + 15, 14, 9, 8, 12, 10, 11, 13 } /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + }, + + .ect = 0, /* Disable Early Command Training */ +}; + +const struct mb_lpddr4x_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPIO_MEM_CONFIG_0, + GPIO_MEM_CONFIG_1, + GPIO_MEM_CONFIG_2, + GPIO_MEM_CONFIG_3, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} From f538d74e9cf27d3353b3c1d56cb5be42c207ad84 Mon Sep 17 00:00:00 2001 From: Johanna Schander Date: Sun, 8 Dec 2019 11:04:09 +0100 Subject: [PATCH 140/151] vendorcode/intel: Remove Ice Lake FSP Bindings By updating the FSP submodule we now got all FSP headers from within that repo. This commit changes the default paths to use these and fixes some include paths to allow the usage of vendorcode/intel/edk2/UDK2017 together with the official Intel distribution. We are also adding back the CHANNEL_PRESENT enum, that is missing in the official headers. This was tested on the Razer Blade Stealth (late 2019). Change-Id: I7d5520dcd30f4a68af325125052e16e867e91ec9 Signed-off-by: Johanna Schander Reviewed-on: https://review.coreboot.org/c/coreboot/+/37579 Reviewed-by: Nico Huber Reviewed-by: Angel Pons Reviewed-by: Christoph Pomaska Tested-by: build bot (Jenkins) --- .../intel/fsp2_0/include/fsp/soc_binding.h | 18 +- src/soc/intel/icelake/Kconfig | 2 +- src/soc/intel/icelake/romstage/romstage.c | 7 + .../fsp2_0/icelake/FirmwareVersionInfoHob.h | 67 - .../intel/fsp/fsp2_0/icelake/FspUpd.h | 48 - .../intel/fsp/fsp2_0/icelake/FspmUpd.h | 3054 -------------- .../intel/fsp/fsp2_0/icelake/FspsUpd.h | 3610 ----------------- .../intel/fsp/fsp2_0/icelake/FsptUpd.h | 74 - .../intel/fsp/fsp2_0/icelake/MemInfoHob.h | 280 -- 9 files changed, 22 insertions(+), 7138 deletions(-) delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h delete mode 100644 src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h diff --git a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h index 931e427188..607738d7a4 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h +++ b/src/drivers/intel/fsp2_0/include/fsp/soc_binding.h @@ -17,6 +17,20 @@ #include #pragma pack(push) + +/** + * These includes are required to include headers that are missing in + * the FSP headers. Import order matter for the correct PiHob definition + * to be found. + */ +#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION +#include +#include +#include +#include +#include +#endif + /* * This file is a implementation specific header. i.e. different * FSP implementations for different chipsets. @@ -28,10 +42,6 @@ #include #endif -#if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION -#include -#include -#endif #pragma pack(pop) diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 15e895fa1d..42e86c73b2 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -180,7 +180,7 @@ config CBFS_SIZE config FSP_HEADER_PATH string "Location of FSP headers" - default "src/vendorcode/intel/fsp/fsp2_0/icelake/" + default "3rdparty/fsp/IceLakeFspBinPkg/Include" config FSP_FD_PATH string diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 7f1be731e8..37fc678cd9 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -35,6 +35,13 @@ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ } +/* Memory Channel Present Status */ +enum { + CHANNEL_NOT_PRESENT, + CHANNEL_DISABLED, + CHANNEL_PRESENT +}; + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h deleted file mode 100644 index 0dbafffa86..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FirmwareVersionInfoHob.h +++ /dev/null @@ -1,67 +0,0 @@ -/** @file - Header file for Firmware Version Information - - Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
- - This program and the accompanying materials are licensed and made available under - the terms and conditions of the BSD License which accompanies this distribution. - The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -**/ - -#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ -#define _FIRMWARE_VERSION_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack(1) -/// -/// Firmware Version Structure -/// -typedef struct { - UINT8 MajorVersion; - UINT8 MinorVersion; - UINT8 Revision; - UINT16 BuildNumber; -} FIRMWARE_VERSION; - -/// -/// Firmware Version Information Structure -/// -typedef struct { - UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name - UINT8 VersionStringIndex; ///< Offset 1 Index of Version String - FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version -} FIRMWARE_VERSION_INFO; - -#ifndef __SMBIOS_STANDARD_H__ -/// -/// The Smbios structure header. -/// -typedef struct { - UINT8 Type; - UINT8 Length; - UINT16 Handle; -} SMBIOS_STRUCTURE; -#endif - -/// -/// Firmware Version Information HOB Structure -/// -typedef struct { - EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB - SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB - UINT8 Count; ///< Offset 28 Number of FVI elements included. -/// -/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer -/// -} FIRMWARE_VERSION_INFO_HOB; -#pragma pack() - -#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h deleted file mode 100644 index 1ef1e76b0f..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspUpd.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPUPD_H__ -#define __FSPUPD_H__ - -#include - -#pragma pack(1) - -#define FSPT_UPD_SIGNATURE 0x545F4450554C4349 /* 'ICLUPD_T' */ - -#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4349 /* 'ICLUPD_M' */ - -#define FSPS_UPD_SIGNATURE 0x535F4450554C4349 /* 'ICLUPD_S' */ - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h deleted file mode 100644 index e42727bbfc..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspmUpd.h +++ /dev/null @@ -1,3054 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPMUPD_H__ -#define __FSPMUPD_H__ - -#include - -#pragma pack(1) - - -#include - -/// -/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. -/// -typedef struct { - UINT8 Revision; ///< Chipset Init Info Revision - UINT8 Rsvd[3]; ///< Reserved - UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table - UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table -} CHIPSET_INIT_INFO; - - -/** Fsp M Configuration -**/ -typedef struct { - -/** Offset 0x0040 - Memory SPD Pointer Channel 0 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr00; - -/** Offset 0x0044 - Memory SPD Pointer Channel 0 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr01; - -/** Offset 0x0048 - Memory SPD Pointer Channel 1 Dimm 0 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr10; - -/** Offset 0x004C - Memory SPD Pointer Channel 1 Dimm 1 - Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 -**/ - UINT32 MemorySpdPtr11; - -/** Offset 0x0050 - Spd Address Tabl - Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used - if SPD Address is 00 -**/ - UINT8 SpdAddressTable[4]; - -/** Offset 0x0054 - SPD Data Length - Length of SPD Data - 0x100:256 Bytes, 0x200:512 Bytes -**/ - UINT16 MemorySpdDataLen; - -/** Offset 0x0056 - Dq Byte Map CH0 - Dq byte mapping between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqByteMapCh0[12]; - -/** Offset 0x0062 - Dq Byte Map CH1 - Dq byte mapping between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqByteMapCh1[12]; - -/** Offset 0x006E - Dqs Map CPU to DRAM CH 0 - Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent -**/ - UINT8 DqsMapCpu2DramCh0[8]; - -/** Offset 0x0076 - Dqs Map CPU to DRAM CH 1 - Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent -**/ - UINT8 DqsMapCpu2DramCh1[8]; - -/** Offset 0x007E - RcompResister settings - Indicates RcompReister settings: Board-dependent -**/ - UINT16 RcompResistor[3]; - -/** Offset 0x0084 - RcompTarget settings - RcompTarget settings: board-dependent -**/ - UINT16 RcompTarget[5]; - -/** Offset 0x008E -**/ - UINT8 UnusedUpdSpace0[2]; - -/** Offset 0x0090 - Platform Reserved Memory Size - The minimum platform memory size required to pass control into DXE -**/ - UINT64 PlatformMemorySize; - -/** Offset 0x0098 - PcdSerialDebugLevel - Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, - Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, - Info & Verbose. - 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load - Error Warnings and Info, 5:Load Error Warnings Info and Verbose -**/ - UINT8 PcdSerialDebugLevel; - -/** Offset 0x0099 - Ask MRC to clear memory content - Ask MRC to clear memory content 0: Do not Clear Memory; 1: Clear Memory. - $EN_DIS -**/ - UINT8 CleanMemory; - -/** Offset 0x009A - Smram Mask - The SMM Regions AB-SEG and/or H-SEG reserved - 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both -**/ - UINT8 SmramMask; - -/** Offset 0x009B - Dqs Pins Interleaved Setting - Indicates DqPinsInterleaved setting: board-dependent - $EN_DIS -**/ - UINT8 DqPinsInterleaved; - -/** Offset 0x009C - SA GV - System Agent dynamic frequency support and when enabled memory will be training - at three different frequencies. - 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled -**/ - UINT8 SaGv; - -/** Offset 0x009D -**/ - UINT8 UnusedUpdSpace1; - -/** Offset 0x009E - DDR Frequency Limit - Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, - 2133, 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 DdrFreqLimit; - -/** Offset 0x00A0 - Channel A DIMM Control - Channel A DIMM Control Support - Enable or Disable Dimms on Channel A. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel0; - -/** Offset 0x00A1 - Channel B DIMM Control - Channel B DIMM Control Support - Enable or Disable Dimms on Channel B. - 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs -**/ - UINT8 DisableDimmChannel1; - -/** Offset 0x00A2 - MRC Safe Config - Enables/Disable MRC Safe Config - $EN_DIS -**/ - UINT8 MrcSafeConfig; - -/** Offset 0x00A3 - LPDDR4 Write DQ/DQS Retraining - Enables/Disable LPDDR4 Write DQ/DQS Retraining - $EN_DIS -**/ - UINT8 Lp4DqsOscEn; - -/** Offset 0x00A4 - Training Trace - This option enables the trained state tracing feature in MRC. This feature will - print out the key training parameters state across major training steps. - $EN_DIS -**/ - UINT8 TrainTrace; - -/** Offset 0x00A5 - Rank Margin Tool per Task - This option enables the user to execute Rank Margin Tool per major training step - in the MRC. - $EN_DIS -**/ - UINT8 RmtPerTask; - -/** Offset 0x00A6 - LowSupplyEnData - Enable: Enable Low Supply for LPDDR4 Data, Disable(Default) - $EN_DIS -**/ - UINT8 LowSupplyEnData; - -/** Offset 0x00A7 - LowSupplyEnCcc - Enable: Enable Low Supply for LPDDR4 Clock/Command/Control, Disable(Default) - $EN_DIS -**/ - UINT8 LowSupplyEnCcc; - -/** Offset 0x00A8 - Memory Test on Warm Boot - Run Base Memory Test on Warm Boot - 0:Disable, 1:Enable -**/ - UINT8 MemTestOnWarmBoot; - -/** Offset 0x00A9 -**/ - UINT8 UnusedUpdSpace2; - -/** Offset 0x00AA - Low Frequency - SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvLow; - -/** Offset 0x00AC - Mid Frequency - SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133, - 2400, 2667, 2933 and 0 for Auto. - 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto -**/ - UINT16 FreqSaGvMid; - -/** Offset 0x00AE - DDR Speed Control - DDR Frequency and Gear control for all SAGV points. - 0:Auto, 1:Manual -**/ - UINT8 DdrSpeedControl; - -/** Offset 0x00AF - SA GV Low Gear - Gear Selection for SAGV Low point - 0:Gear1, 1:Gear2 -**/ - UINT8 SaGvLowGear2; - -/** Offset 0x00B0 - SA GV Mid Gear - Gear Selection for SAGV Mid point - 0:Gear1, 1:Gear2 -**/ - UINT8 SaGvMidGear2; - -/** Offset 0x00B1 - SA GV High Gear - Gear Selection for SAGV High point, or when SAGV is disabled - 0:Gear1, 1:Gear2 -**/ - UINT8 SaGvHighGear2; - -/** Offset 0x00B2 - Scrambler Support - This option enables data scrambling in memory. - $EN_DIS -**/ - UINT8 ScramblerSupport; - -/** Offset 0x00B3 - Safe Mode Support - This option configures the varous items in the IO and MC to be more conservative.(def=Disable) - $EN_DIS -**/ - UINT8 SafeMode; - -/** Offset 0x00B4 - Ddr4OneDpc - DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, - or on both (default) - 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled -**/ - UINT8 Ddr4OneDpc; - -/** Offset 0x00B5 - Probeless Trace - Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. - This also requires IED to be enabled. - $EN_DIS -**/ - UINT8 ProbelessTrace; - -/** Offset 0x00B6 - VREF_CA - CA Vref routing: board-dependent - 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B, - 2:VREF_CA to CH_A and VREF_DQ_B to CH_B -**/ - UINT8 CaVrefConfig; - -/** Offset 0x00B7 - SPD Profile Selected - Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP - Profile 1, 3=XMP Profile 2 - 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2 -**/ - UINT8 SpdProfileSelected; - -/** Offset 0x00B8 - Memory Voltage - Memory Voltage Override (Vddq). Default = no override - 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40 - Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts -**/ - UINT16 VddVoltage; - -/** Offset 0x00BA - Memory Reference Clock - 100MHz, 133MHz. - 0:133MHz, 1:100MHz -**/ - UINT8 RefClk; - -/** Offset 0x00BB - Memory Ratio - Automatic or the frequency will equal ratio times reference clock. Set to Auto to - recalculate memory timings listed below. - 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 -**/ - UINT8 Ratio; - -/** Offset 0x00BC - tCL - CAS Latency, 0: AUTO, max: 31 -**/ - UINT8 tCL; - -/** Offset 0x00BD - tCWL - Min CAS Write Latency Delay Time, 0: AUTO, max: 34 -**/ - UINT8 tCWL; - -/** Offset 0x00BE - tFAW - Min Four Activate Window Delay Time, 0: AUTO, max: 63 -**/ - UINT16 tFAW; - -/** Offset 0x00C0 - tRAS - RAS Active Time, 0: AUTO, max: 64 -**/ - UINT16 tRAS; - -/** Offset 0x00C2 - tRCD/tRP - RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63 -**/ - UINT8 tRCDtRP; - -/** Offset 0x00C3 -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x00C4 - tREFI - Refresh Interval, 0: AUTO, max: 65535 -**/ - UINT16 tREFI; - -/** Offset 0x00C6 - tRFC - Min Refresh Recovery Delay Time, 0: AUTO, max: 1023 -**/ - UINT16 tRFC; - -/** Offset 0x00C8 - tRRD - Min Row Active to Row Active Delay Time, 0: AUTO, max: 15 -**/ - UINT8 tRRD; - -/** Offset 0x00C9 - tRTP - Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal - values: 5, 6, 7, 8, 9, 10, 12 -**/ - UINT8 tRTP; - -/** Offset 0x00CA - tWR - Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, - 20, 24, 30, 34, 40 - 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, - 34:34, 40:40 -**/ - UINT8 tWR; - -/** Offset 0x00CB - tWTR - Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28 -**/ - UINT8 tWTR; - -/** Offset 0x00CC - NMode - System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N -**/ - UINT8 NModeSupport; - -/** Offset 0x00CD - DllBwEn[0] - DllBwEn[0], for 1067 (0..7) -**/ - UINT8 DllBwEn0; - -/** Offset 0x00CE - DllBwEn[1] - DllBwEn[1], for 1333 (0..7) -**/ - UINT8 DllBwEn1; - -/** Offset 0x00CF - DllBwEn[2] - DllBwEn[2], for 1600 (0..7) -**/ - UINT8 DllBwEn2; - -/** Offset 0x00D0 - DllBwEn[3] - DllBwEn[3], for 1867 and up (0..7) -**/ - UINT8 DllBwEn3; - -/** Offset 0x00D1 - ISVT IO Port Address - ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default -**/ - UINT8 IsvtIoPort; - -/** Offset 0x00D2 - HobBufferSize - Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB - total HOB size). - 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value -**/ - UINT8 HobBufferSize; - -/** Offset 0x00D3 - Early Command Training - Enables/Disable Early Command Training - $EN_DIS -**/ - UINT8 ECT; - -/** Offset 0x00D4 - SenseAmp Offset Training - Enables/Disable SenseAmp Offset Training - $EN_DIS -**/ - UINT8 SOT; - -/** Offset 0x00D5 - Early ReadMPR Timing Centering 2D - Enables/Disable Early ReadMPR Timing Centering 2D - $EN_DIS -**/ - UINT8 ERDMPRTC2D; - -/** Offset 0x00D6 - Read MPR Training - Enables/Disable Read MPR Training - $EN_DIS -**/ - UINT8 RDMPRT; - -/** Offset 0x00D7 - Receive Enable Training - Enables/Disable Receive Enable Training - $EN_DIS -**/ - UINT8 RCVET; - -/** Offset 0x00D8 - Jedec Write Leveling - Enables/Disable Jedec Write Leveling - $EN_DIS -**/ - UINT8 JWRL; - -/** Offset 0x00D9 - Early Write Time Centering 2D - Enables/Disable Early Write Time Centering 2D - $EN_DIS -**/ - UINT8 EWRTC2D; - -/** Offset 0x00DA - Early Read Time Centering 2D - Enables/Disable Early Read Time Centering 2D - $EN_DIS -**/ - UINT8 ERDTC2D; - -/** Offset 0x00DB - Write Timing Centering 1D - Enables/Disable Write Timing Centering 1D - $EN_DIS -**/ - UINT8 WRTC1D; - -/** Offset 0x00DC - Write Voltage Centering 1D - Enables/Disable Write Voltage Centering 1D - $EN_DIS -**/ - UINT8 WRVC1D; - -/** Offset 0x00DD - Read Timing Centering 1D - Enables/Disable Read Timing Centering 1D - $EN_DIS -**/ - UINT8 RDTC1D; - -/** Offset 0x00DE - Dimm ODT Training - Enables/Disable Dimm ODT Training - $EN_DIS -**/ - UINT8 DIMMODTT; - -/** Offset 0x00DF - DIMM RON Training - Enables/Disable DIMM RON Training - $EN_DIS -**/ - UINT8 DIMMRONT; - -/** Offset 0x00E0 - Write Slew Rate Training - Enables/Disable Write Slew Rate Training - $EN_DIS -**/ - UINT8 WRSRT; - -/** Offset 0x00E1 - Read ODT Training - Enables/Disable Read ODT Training - $EN_DIS -**/ - UINT8 RDODTT; - -/** Offset 0x00E2 - Read Equalization Training - Enables/Disable Read Equalization Training - $EN_DIS -**/ - UINT8 RDEQT; - -/** Offset 0x00E3 - Read Amplifier Training - Enables/Disable Read Amplifier Training - $EN_DIS -**/ - UINT8 RDAPT; - -/** Offset 0x00E4 - Write Timing Centering 2D - Enables/Disable Write Timing Centering 2D - $EN_DIS -**/ - UINT8 WRTC2D; - -/** Offset 0x00E5 - Read Timing Centering 2D - Enables/Disable Read Timing Centering 2D - $EN_DIS -**/ - UINT8 RDTC2D; - -/** Offset 0x00E6 - Write Voltage Centering 2D - Enables/Disable Write Voltage Centering 2D - $EN_DIS -**/ - UINT8 WRVC2D; - -/** Offset 0x00E7 - Read Voltage Centering 2D - Enables/Disable Read Voltage Centering 2D - $EN_DIS -**/ - UINT8 RDVC2D; - -/** Offset 0x00E8 - Command Voltage Centering - Enables/Disable Command Voltage Centering - $EN_DIS -**/ - UINT8 CMDVC; - -/** Offset 0x00E9 - Late Command Training - Enables/Disable Late Command Training - $EN_DIS -**/ - UINT8 LCT; - -/** Offset 0x00EA - Round Trip Latency Training - Enables/Disable Round Trip Latency Training - $EN_DIS -**/ - UINT8 RTL; - -/** Offset 0x00EB - Turn Around Timing Training - Enables/Disable Turn Around Timing Training - $EN_DIS -**/ - UINT8 TAT; - -/** Offset 0x00EC - Receive Enable Centering 1D - Enables/Disable Receive Enable Centering 1D - $EN_DIS -**/ - UINT8 RCVENC1D; - -/** Offset 0x00ED - Rank Margin Tool - Enable/disable Rank Margin Tool. - $EN_DIS -**/ - UINT8 RMT; - -/** Offset 0x00EE - Margin Limit Check - Margin Limit Check. Choose level of margin check - 0:Disable, 1:L1, 2:L2, 3:Both -**/ - UINT8 MarginLimitCheck; - -/** Offset 0x00EF -**/ - UINT8 UnusedUpdSpace4; - -/** Offset 0x00F0 - Margin Limit L2 - % of L1 check for margin limit check -**/ - UINT16 MarginLimitL2; - -/** Offset 0x00F2 - Memory Test - Enables/Disable Memory Test - $EN_DIS -**/ - UINT8 MEMTST; - -/** Offset 0x00F3 - DIMM SPD Alias Test - Enables/Disable DIMM SPD Alias Test - $EN_DIS -**/ - UINT8 ALIASCHK; - -/** Offset 0x00F4 - Retrain Margin Check - Enables/Disable Retrain Margin Check - $EN_DIS -**/ - UINT8 RMC; - -/** Offset 0x00F5 - Write Drive Strength Up/Dn independently - Enables/Disable Write Drive Strength Up/Dn independently - $EN_DIS -**/ - UINT8 WRDSUDT; - -/** Offset 0x00F6 - Command Slew Rate Training - Enables/Disable Command Slew Rate Training - $EN_DIS -**/ - UINT8 CMDSR; - -/** Offset 0x00F7 - Command Drive Strength and Equalization 2D - Enables/Disable Command Drive Strength and Equalization 2D - $EN_DIS -**/ - UINT8 CMDDSEQ; - -/** Offset 0x00F8 - Command Normalization - Enables/Disable Command Normalization - $EN_DIS -**/ - UINT8 CMDNORM; - -/** Offset 0x00F9 - Early DQ Write Drive Strength and Equalization Training - Enables/Disable Early DQ Write Drive Strength and Equalization Training - $EN_DIS -**/ - UINT8 EWRDSEQ; - -/** Offset 0x00FA - Read Voltage Centering - Enables/Disable Read Voltage Centering - $EN_DIS -**/ - UINT8 RDVC1D; - -/** Offset 0x00FB - Write TCO Comp Training - Enables/Disable Write TCO Comp Training - $EN_DIS -**/ - UINT8 TXTCO; - -/** Offset 0x00FC - Clock TCO Comp Training - Enables/Disable Clock TCO Comp Training - $EN_DIS -**/ - UINT8 CLKTCO; - -/** Offset 0x00FD - Dimm ODT CA Training - Enables/Disable Dimm ODT CA Training - $EN_DIS -**/ - UINT8 DIMMODTCA; - -/** Offset 0x00FE - Write TCO Dqs Training - Enables/Disable Write TCO Dqs Training - $EN_DIS -**/ - UINT8 TXTCODQS; - -/** Offset 0x00FF - Duty Cycle Correction - Enables/Disable Duty Cycle Correction - $EN_DIS -**/ - UINT8 DCC; - -/** Offset 0x0100 - DQ DFE Training - Enable/Disable DQ DFE Training - $EN_DIS -**/ - UINT8 DQDFE; - -/** Offset 0x0101 - Sense Amplifier Correction Training - Enable/Disable Sense Amplifier Correction Training - $EN_DIS -**/ - UINT8 SOTC; - -/** Offset 0x0102 - ECC Support - Enables/Disable ECC Support - $EN_DIS -**/ - UINT8 EccSupport; - -/** Offset 0x0103 - Memory Remap - Enables/Disable Memory Remap - $EN_DIS -**/ - UINT8 RemapEnable; - -/** Offset 0x0104 - MRC Time Measure - Enable/Disable MRC Time Measure - $EN_DIS -**/ - UINT8 MrcTimeMeasure; - -/** Offset 0x0105 - MRC Fast Boot - Enable/Disable MRC Fast flow - $EN_DIS -**/ - UINT8 MrcFastBoot; - -/** Offset 0x0106 - MRC Force Training on Warm - Enables/Disable the MRC training on warm boot - $EN_DIS -**/ - UINT8 MrcTrainOnWarm; - -/** Offset 0x0107 - Rank Interleave support - Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at - the same time. - $EN_DIS -**/ - UINT8 RankInterleave; - -/** Offset 0x0108 - Enhanced Interleave support - Enables/Disable Enhanced Interleave support - $EN_DIS -**/ - UINT8 EnhancedInterleave; - -/** Offset 0x0109 - Memory Trace - Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of - equal size. This option may change TOLUD and REMAP values as needed. - $EN_DIS -**/ - UINT8 MemoryTrace; - -/** Offset 0x010A - Ch Hash Support - Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode - $EN_DIS -**/ - UINT8 ChHashEnable; - -/** Offset 0x010B - Extern Therm Status - Enables/Disable Extern Therm Status - $EN_DIS -**/ - UINT8 EnableExtts; - -/** Offset 0x010C - Closed Loop Therm Manage - Enables/Disable Closed Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableCltm; - -/** Offset 0x010D - Open Loop Therm Manage - Enables/Disable Open Loop Therm Manage - $EN_DIS -**/ - UINT8 EnableOltm; - -/** Offset 0x010E - DDR PowerDown and idle counter - Enables/Disable DDR PowerDown and idle counter - $EN_DIS -**/ - UINT8 EnablePwrDn; - -/** Offset 0x010F - DDR PowerDown and idle counter - LPDDR - Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) - $EN_DIS -**/ - UINT8 EnablePwrDnLpddr; - -/** Offset 0x0110 - Use user provided power weights, scale factor, and channel power floor values - Enables/Disable Use user provided power weights, scale factor, and channel power - floor values - $EN_DIS -**/ - UINT8 UserPowerWeightsEn; - -/** Offset 0x0111 - RAPL PL Lock - Enables/Disable RAPL PL Lock - $EN_DIS -**/ - UINT8 RaplLim2Lock; - -/** Offset 0x0112 - RAPL PL 2 enable - Enables/Disable RAPL PL 2 enable - $EN_DIS -**/ - UINT8 RaplLim2Ena; - -/** Offset 0x0113 - RAPL PL 1 enable - Enables/Disable RAPL PL 1 enable - $EN_DIS -**/ - UINT8 RaplLim1Ena; - -/** Offset 0x0114 - SelfRefresh Enable - Enables/Disable SelfRefresh Enable - $EN_DIS -**/ - UINT8 SrefCfgEna; - -/** Offset 0x0115 - Throttler CKEMin Defeature - LPDDR - Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeatLpddr; - -/** Offset 0x0116 - Throttler CKEMin Defeature - Enables/Disable Throttler CKEMin Defeature - $EN_DIS -**/ - UINT8 ThrtCkeMinDefeat; - -/** Offset 0x0117 - Enable RH Prevention - Enables/Disable RH Prevention - $EN_DIS -**/ - UINT8 RhPrevention; - -/** Offset 0x0118 - Exit On Failure (MRC) - Enables/Disable Exit On Failure (MRC) - $EN_DIS -**/ - UINT8 ExitOnFailure; - -/** Offset 0x0119 - LPDDR Thermal Sensor - Enables/Disable LPDDR Thermal Sensor - $EN_DIS -**/ - UINT8 DdrThermalSensor; - -/** Offset 0x011A - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedClock; - -/** Offset 0x011B - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP - $EN_DIS -**/ - UINT8 Ddr4DdpSharedZq; - -/** Offset 0x011C - Base reference clock value - Base reference clock value, in Hertz(Default is 125Hz) - 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz -**/ - UINT32 BClkFrequency; - -/** Offset 0x0120 - Ch Hash Interleaved Bit - Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave - the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 - 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 -**/ - UINT8 ChHashInterleaveBit; - -/** Offset 0x0121 -**/ - UINT8 UnusedUpdSpace5; - -/** Offset 0x0122 - Ch Hash Mask - Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to - BITS [19:6] Default is 0x30CC -**/ - UINT16 ChHashMask; - -/** Offset 0x0124 - Extended Bank Hashing - Eanble/Disable ExtendedBankHashing - $EN_DIS -**/ - UINT8 ExtendedBankHashing; - -/** Offset 0x0125 - Energy Scale Factor - Energy Scale Factor, Default is 4 -**/ - UINT8 EnergyScaleFact; - -/** Offset 0x0126 - EPG DIMM Idd3N - Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on - a per DIMM basis. Default is 26 -**/ - UINT16 Idd3n; - -/** Offset 0x0128 - EPG DIMM Idd3P - Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated - on a per DIMM basis. Default is 11 -**/ - UINT16 Idd3p; - -/** Offset 0x012A - RH Activation Probability - RH Activation Probability, Probability value is 1/2^(inputvalue) -**/ - UINT8 RhActProbability; - -/** Offset 0x012B - RAPL PL 2 WindowX - Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim2WindX; - -/** Offset 0x012C - RAPL PL 2 WindowY - Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim2WindY; - -/** Offset 0x012D - RAPL PL 1 WindowX - Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindX; - -/** Offset 0x012E - RAPL PL 1 WindowY - Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def) -**/ - UINT8 RaplLim1WindY; - -/** Offset 0x012F -**/ - UINT8 UnusedUpdSpace6; - -/** Offset 0x0130 - RAPL PL 2 Power - range[0;2^14-1]= [2047.875;0]in W, (224= Def) -**/ - UINT16 RaplLim2Pwr; - -/** Offset 0x0132 - RAPL PL 1 Power - range[0;2^14-1]= [2047.875;0]in W, (224= Def) -**/ - UINT16 RaplLim1Pwr; - -/** Offset 0x0134 - Warm Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh0Dimm0; - -/** Offset 0x0135 - Warm Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh0Dimm1; - -/** Offset 0x0136 - Warm Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh1Dimm0; - -/** Offset 0x0137 - Warm Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 WarmThresholdCh1Dimm1; - -/** Offset 0x0138 - Hot Threshold Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh0Dimm0; - -/** Offset 0x0139 - Hot Threshold Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh0Dimm1; - -/** Offset 0x013A - Hot Threshold Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh1Dimm0; - -/** Offset 0x013B - Hot Threshold Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Fefault is 255 -**/ - UINT8 HotThresholdCh1Dimm1; - -/** Offset 0x013C - Warm Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm0; - -/** Offset 0x013D - Warm Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh0Dimm1; - -/** Offset 0x013E - Warm Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm0; - -/** Offset 0x013F - Warm Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 WarmBudgetCh1Dimm1; - -/** Offset 0x0140 - Hot Budget Ch0 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm0; - -/** Offset 0x0141 - Hot Budget Ch0 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh0Dimm1; - -/** Offset 0x0142 - Hot Budget Ch1 Dimm0 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm0; - -/** Offset 0x0143 - Hot Budget Ch1 Dimm1 - range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM -**/ - UINT8 HotBudgetCh1Dimm1; - -/** Offset 0x0144 - Idle Energy Ch0Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm0; - -/** Offset 0x0145 - Idle Energy Ch0Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh0Dimm1; - -/** Offset 0x0146 - Idle Energy Ch1Dimm0 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm0; - -/** Offset 0x0147 - Idle Energy Ch1Dimm1 - Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) -**/ - UINT8 IdleEnergyCh1Dimm1; - -/** Offset 0x0148 - PowerDown Energy Ch0Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm0; - -/** Offset 0x0149 - PowerDown Energy Ch0Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh0Dimm1; - -/** Offset 0x014A - PowerDown Energy Ch1Dimm0 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm0; - -/** Offset 0x014B - PowerDown Energy Ch1Dimm1 - PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def) -**/ - UINT8 PdEnergyCh1Dimm1; - -/** Offset 0x014C - Activate Energy Ch0Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm0; - -/** Offset 0x014D - Activate Energy Ch0Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh0Dimm1; - -/** Offset 0x014E - Activate Energy Ch1Dimm0 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm0; - -/** Offset 0x014F - Activate Energy Ch1Dimm1 - Activate Energy Contribution, range[255;0],(172= Def) -**/ - UINT8 ActEnergyCh1Dimm1; - -/** Offset 0x0150 - Read Energy Ch0Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm0; - -/** Offset 0x0151 - Read Energy Ch0Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh0Dimm1; - -/** Offset 0x0152 - Read Energy Ch1Dimm0 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm0; - -/** Offset 0x0153 - Read Energy Ch1Dimm1 - Read Energy Contribution, range[255;0],(212= Def) -**/ - UINT8 RdEnergyCh1Dimm1; - -/** Offset 0x0154 - Write Energy Ch0Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm0; - -/** Offset 0x0155 - Write Energy Ch0Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh0Dimm1; - -/** Offset 0x0156 - Write Energy Ch1Dimm0 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm0; - -/** Offset 0x0157 - Write Energy Ch1Dimm1 - Write Energy Contribution, range[255;0],(221= Def) -**/ - UINT8 WrEnergyCh1Dimm1; - -/** Offset 0x0158 - Throttler CKEMin Timer - Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). - Dfault is 0x30 -**/ - UINT8 ThrtCkeMinTmr; - -/** Offset 0x0159 - Cke Rank Mapping - Bits [7:4] - Channel 1, bits [3:0] - Channel 0. 0xAA=Default Bit [i] specifies - which rank CKE[i] goes to. -**/ - UINT8 CkeRankMapping; - -/** Offset 0x015A - Rapl Power Floor Ch0 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh0; - -/** Offset 0x015B - Rapl Power Floor Ch1 - Power budget ,range[255;0],(0= 5.3W Def) -**/ - UINT8 RaplPwrFlCh1; - -/** Offset 0x015C - Command Rate Support - CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs - 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS -**/ - UINT8 EnCmdRate; - -/** Offset 0x015D - REFRESH_2X_MODE - 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot - 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only -**/ - UINT8 Refresh2X; - -/** Offset 0x015E - Energy Performance Gain - Enable/disable(default) Energy Performance Gain. - $EN_DIS -**/ - UINT8 EpgEnable; - -/** Offset 0x015F - Row Hammer Solution - Type of method used to prevent Row Hammer. Default is Hardware RHP - 0:Hardware RHP, 1:2x Refresh -**/ - UINT8 RhSolution; - -/** Offset 0x0160 - User Manual Threshold - Disabled: Predefined threshold will be used.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserThresholdEnable; - -/** Offset 0x0161 - User Manual Budget - Disabled: Configuration of memories will defined the Budget value.\n - Enabled: User Input will be used. - $EN_DIS -**/ - UINT8 UserBudgetEnable; - -/** Offset 0x0162 - TcritMax - Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax - has to be greater than THIGHMax .\n - Critical temperature will be TcritMax -**/ - UINT8 TsodTcritMax; - -/** Offset 0x0163 - Event mode - Disable:Comparator mode.\n - Enable:Interrupt mode - $EN_DIS -**/ - UINT8 TsodEventMode; - -/** Offset 0x0164 - EVENT polarity - Disable:Active LOW.\n - Enable:Active HIGH - $EN_DIS -**/ - UINT8 TsodEventPolarity; - -/** Offset 0x0165 - Critical event only - Disable:Trips on alarm or critical.\n - Enable:Trips only if criticaal temperature is reached - $EN_DIS -**/ - UINT8 TsodCriticalEventOnly; - -/** Offset 0x0166 - Event output control - Disable:Event output disable.\n - Enable:Event output enabled - $EN_DIS -**/ - UINT8 TsodEventOutputControl; - -/** Offset 0x0167 - Alarm window lock bit - Disable:Alarm trips are not locked and can be changed.\n - Enable:Alarm trips are locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodAlarmwindowLockBit; - -/** Offset 0x0168 - Critical trip lock bit - Disable:Critical trip is not locked and can be changed.\n - Enable:Critical trip is locked and cannot be changed - $EN_DIS -**/ - UINT8 TsodCriticaltripLockBit; - -/** Offset 0x0169 - Shutdown mode - Disable:Temperature sensor enable.\n - Enable:Temperature sensor disable - $EN_DIS -**/ - UINT8 TsodShutdownMode; - -/** Offset 0x016A - ThighMax - Thigh = ThighMax (Default is 93) -**/ - UINT8 TsodThigMax; - -/** Offset 0x016B - User Manual Thig and Tcrit - Disabled(Default): Temperature will be given by the configuration of memories and - 1x or 2xrefresh rate.\n - Enabled: User Input will define for Thigh and Tcrit. - $EN_DIS -**/ - UINT8 TsodManualEnable; - -/** Offset 0x016C - Force OLTM or 2X Refresh when needed - Disabled(Default): = Force OLTM.\n - Enabled: = Force 2x Refresh. - $EN_DIS -**/ - UINT8 ForceOltmOrRefresh2x; - -/** Offset 0x016D - Pwr Down Idle Timer - The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means - AUTO: 64 for ULX/ULT, 128 for DT/Halo -**/ - UINT8 PwdwnIdleCounter; - -/** Offset 0x016E - Bitmask of ranks that have CA bus terminated - Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. 0x01=Default, - Rank0 is terminating and Rank1 is non-terminating -**/ - UINT8 CmdRanksTerminated; - -/** Offset 0x016F - RMTLoopCount - Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO -**/ - UINT8 RMTLoopCount; - -/** Offset 0x0170 - Throttler CKEMin Timer for LPDDR - LPDDR Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH - (4). Dfault is 0x40 -**/ - UINT8 ThrtCkeMinTmrLpddr; - -/** Offset 0x0171 - Retrain on Fast Fail - Restart MRC in Cold mode if SW MemTest fails during Fast flow. Default = Enabled - $EN_DIS -**/ - UINT8 RetrainOnFastFail; - -/** Offset 0x0172 - Rank Margin Tool Per Bit - Enable/disable Rank Margin Tool Per Bit. - $EN_DIS -**/ - UINT8 RMTBIT; - -/** Offset 0x0173 -**/ - UINT8 MrcPreMemRsvd[14]; - -/** Offset 0x0181 - Over clocking support - Over clocking support; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 OcSupport; - -/** Offset 0x0182 - Over clocking Lock - Over clocking Lock Enable/Disable; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 OcLock; - -/** Offset 0x0183 - Maximum Core Turbo Ratio Override - Maximum core turbo ratio override allows to increase CPU core frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 -**/ - UINT8 CoreMaxOcRatio; - -/** Offset 0x0184 - Core voltage mode - Core voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 CoreVoltageMode; - -/** Offset 0x0185 - Maximum clr turbo ratio override - Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the - fused max turbo ratio limit. 0: Hardware defaults. Range: 0-85 -**/ - UINT8 RingMaxOcRatio; - -/** Offset 0x0186 - Ring Downbin - Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always - lower than the core ratio.0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 RingDownBin; - -/** Offset 0x0187 - Ring voltage mode - Ring voltage mode; 0: Adaptive; 1: Override. - $EN_DIS -**/ - UINT8 RingVoltageMode; - -/** Offset 0x0188 - Ring voltage override - The ring voltage override which is applied to the entire range of cpu ring frequencies. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageOverride; - -/** Offset 0x018A - Ring Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 RingVoltageAdaptive; - -/** Offset 0x018C - Ring Turbo voltage Offset - The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 -**/ - UINT16 RingVoltageOffset; - -/** Offset 0x018E - core voltage override - The core voltage override which is applied to the entire range of cpu core frequencies. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageOverride; - -/** Offset 0x0190 - Core Turbo voltage Adaptive - Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. - Valid Range 0 to 2000 -**/ - UINT16 CoreVoltageAdaptive; - -/** Offset 0x0192 - Core Turbo voltage Offset - The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 -**/ - UINT16 CoreVoltageOffset; - -/** Offset 0x0194 - Core PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 CorePllVoltageOffset; - -/** Offset 0x0195 - GT PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 GtPllVoltageOffset; - -/** Offset 0x0196 - Ring PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 RingPllVoltageOffset; - -/** Offset 0x0197 - System Agent PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 SaPllVoltageOffset; - -/** Offset 0x0198 - Memory Controller PLL voltage offset - Core PLL voltage offset. 0: No offset. Range 0-63 -**/ - UINT8 McPllVoltageOffset; - -/** Offset 0x0199 - BCLK Adaptive Voltage Enable - When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. 0: - Disable; 1: Enable - $EN_DIS -**/ - UINT8 BclkAdaptiveVoltage; - -/** Offset 0x019A - AVX2 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx2RatioOffset; - -/** Offset 0x019B - AVX3 Ratio Offset - 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio - vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. -**/ - UINT8 Avx3RatioOffset; - -/** Offset 0x019C - TjMax Offset - TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support - TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 -**/ - UINT8 TjMaxOffset; - -/** Offset 0x019D - Fivr Faults - Fivr Faults; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrFaults; - -/** Offset 0x019E - Fivr Efficiency - Fivr Efficiency Management; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 FivrEfficiency; - -/** Offset 0x019F -**/ - UINT8 UnusedUpdSpace7; - -/** Offset 0x01A0 - VccIn Voltage Override - This will override VccIn output voltage level to the voltage value specified. Valid - Range 0 to 3000 -**/ - UINT16 VccInVoltageOverride; - -/** Offset 0x01A2 - Avx2 Voltage Guardband Scaling Factor - AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in - 1/100 units, where a value of 125 would apply a 1.25 scale factor. -**/ - UINT8 Avx2VoltageScaleFactor; - -/** Offset 0x01A3 - Avx512 Voltage Guardband Scaling Factor - AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200 - in 1/100 units, where a value of 125 would apply a 1.25 scale factor. -**/ - UINT8 Avx512VoltageScaleFactor; - -/** Offset 0x01A4 - Non-Core High Voltage Mode - Enable High Voltage Mode in the non-core FIVR domains (Ring/GT). Used for LN2 cold - boot mitigation. 0 - Disable, 1 - Enable - $EN_DIS -**/ - UINT8 NonCoreHighVoltageMode; - -/** Offset 0x01A5 - Core High Voltage Mode - Enable High Voltage Mode in the core FIVR Domains. Used for LN2 cold boot mitigation. - 0 - Disable, 1 - Enable - $EN_DIS -**/ - UINT8 CoreHighVoltageMode; - -/** Offset 0x01A6 - Per Core Ratio Limit - Per Core Ratio Limit. Range 0 - 120. Default = 0, no BIOS programming of - per core ratio. -**/ - UINT8 PerCoreRatioLimit[8]; - -/** Offset 0x01AE - FIVR TDC - Enable or Disable FIVR TDC from PCODE. 0: Disable. 1: Enable. - $EN_DIS -**/ - UINT8 FivrTdc; - -/** Offset 0x01AF - Full Range Multiplier unlock enable - Enable or Disable communication between Punit and Core in 100MHz granularity. 0: - Disable. 1: Enable. - $EN_DIS -**/ - UINT8 FullRangeMultiplierUnlockEn; - -/** Offset 0x01B0 - SA PLL Freq override - Enable or Disable SA PLL Freq override to 1600MHz instead of 3200MHz on Desktop. - 0: Disable. 1: Enable. - $EN_DIS -**/ - UINT8 SaPllFreqOverride; - -/** Offset 0x01B1 - XHCI PLL override - Enable or Disable XHCI PLL override to use TMU PLL instead of SA PLL. 0: Disable. - 1: Enable. - $EN_DIS -**/ - UINT8 XhciPllOverride; - -/** Offset 0x01B2 - FIVR PS - Enable or Disable FIVR PS. 0: Disable. 1: Enable. - $EN_DIS -**/ - UINT8 FivrPs; - -/** Offset 0x01B3 - FIVR PROTECTION - Enable or Disable FIVR overvoltage and overcurrent protection. 0: Disable. - 1: Enable. - $EN_DIS -**/ - UINT8 FivrProtection; - -/** Offset 0x01B4 - TSC HW Fixup - Enable or Disable Core HW Fixup during TSC copy from PMA and APIC. 0: Disable. - 1: Enable. - $EN_DIS -**/ - UINT8 TscHwFixup; - -/** Offset 0x01B5 -**/ - UINT8 UnusedUpdSpace8; - -/** Offset 0x01B6 - VccIN VR MAX Voltage - The new VccIN VR MAX Voltage to allow requesting in U3.13V format. Valid Range is - in U3.13 from 0 to 7999V. -**/ - UINT16 VccinVrMaxVoltage; - -/** Offset 0x01B8 - Post Divider (PVD) Ratio Threshold - PVD Ratio Threshold. 0: No offset. Range 0-63 -**/ - UINT8 PvdRatioThreshold; - -/** Offset 0x01B9 - Hyper Threading Enable/Disable - Enable or Disable Hyper Threading; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 HyperThreading; - -/** Offset 0x01BA - Boot frequency - Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.- - 1: Maximum non-turbo performance.- 2: Turbo performance. @note If Turbo - is selected BIOS will start in max non-turbo mode and switch to Turbo mode. - 0:0, 1:1, 2:2 -**/ - UINT8 BootFrequency; - -/** Offset 0x01BB - Number of active cores - Number of active cores(Depends on Number of cores). 0: All;1: 1 ;2: - 2 ;3: 3 - 0:All, 1:1, 2:2, 3:3 -**/ - UINT8 ActiveCoreCount; - -/** Offset 0x01BC - Processor Early Power On Configuration FCLK setting - 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- - 2: 400 MHz. - 3: Reserved - 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved -**/ - UINT8 FClkFrequency; - -/** Offset 0x01BD - Set JTAG power in C10 and deeper power states - False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 - and deeper power states for debug purpose. 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 JtagC10PowerGateDisable; - -/** Offset 0x01BE - BIST on Reset - Enable or Disable BIST on Reset; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 BistOnReset; - -/** Offset 0x01BF - Enable or Disable VMX - Enable or Disable VMX; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 VmxEnable; - -/** Offset 0x01C0 - CPU ratio value - CPU ratio value. Valid Range 0 to 63 -**/ - UINT8 CpuRatio; - -/** Offset 0x01C1 - Enable or Disable TME - Enable or Disable TME; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TmeEnable; - -/** Offset 0x01C2 - Enable CPU CrashLog - Enable or Disable CPU CrashLog; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CpuCrashLogEnable; - -/** Offset 0x01C3 - CPU Run Control - Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; 2: - No Change - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DebugInterfaceEnable; - -/** Offset 0x01C4 - CPU Run Control Lock - Lock or Unlock CPU Run Control; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DebugInterfaceLockEnable; - -/** Offset 0x01C5 - Skip Multi-Processor Initialization - When this is skipped, boot loader must initialize processors before SilicionInit - API. 0: Initialize; 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInitPreMem; - -/** Offset 0x01C6 -**/ - UINT8 CpuPreMemRsvd[13]; - -/** Offset 0x01D3 - Skip Stop PBET Timer Enable/Disable - Skip Stop PBET Timer; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 SkipStopPbet; - -/** Offset 0x01D4 - C6DRAM power gating feature - This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM - power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating - feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. - $EN_DIS -**/ - UINT8 EnableC6Dram; - -/** Offset 0x01D5 - BiosGuard - Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable - $EN_DIS -**/ - UINT8 BiosGuard; - -/** Offset 0x01D6 -**/ - UINT8 BiosGuardToolsInterface; - -/** Offset 0x01D7 - EnableSgx - Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control - 0: Disable, 1: Enable, 2: Software Control -**/ - UINT8 EnableSgx; - -/** Offset 0x01D8 - Txt - Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable - $EN_DIS -**/ - UINT8 Txt; - -/** Offset 0x01D9 -**/ - UINT8 UnusedUpdSpace9[3]; - -/** Offset 0x01DC - PrmrrSize - Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable -**/ - UINT32 PrmrrSize; - -/** Offset 0x01E0 - TxtAcheckRequest - Enable/Disable. When Enabled, it will forcing calling TXT Acheck once. - $EN_DIS -**/ - UINT8 TxtAcheckRequest; - -/** Offset 0x01E1 -**/ - UINT8 UnusedUpdSpace10; - -/** Offset 0x01E2 - BiosSize - Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable -**/ - UINT16 BiosSize; - -/** Offset 0x01E4 - SinitMemorySize - Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable -**/ - UINT32 SinitMemorySize; - -/** Offset 0x01E8 - TxtHeapMemorySize - Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable -**/ - UINT32 TxtHeapMemorySize; - -/** Offset 0x01EC -**/ - UINT8 UnusedUpdSpace11[4]; - -/** Offset 0x01F0 - TxtDprMemoryBase - Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable -**/ - UINT64 TxtDprMemoryBase; - -/** Offset 0x01F8 - TxtDprMemorySize - Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable -**/ - UINT32 TxtDprMemorySize; - -/** Offset 0x01FC - BiosAcmBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 BiosAcmBase; - -/** Offset 0x0200 - BiosAcmSize - Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable -**/ - UINT32 BiosAcmSize; - -/** Offset 0x0204 - TgaSize - Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable -**/ - UINT32 TgaSize; - -/** Offset 0x0208 - TxtLcpPdBase - Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable -**/ - UINT64 TxtLcpPdBase; - -/** Offset 0x0210 - TxtLcpPdSize - Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable -**/ - UINT64 TxtLcpPdSize; - -/** Offset 0x0218 - ApStartupBase - Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable -**/ - UINT32 ApStartupBase; - -/** Offset 0x021C - IsTPMPresence - IsTPMPresence default values -**/ - UINT8 IsTPMPresence; - -/** Offset 0x021D -**/ - UINT8 SecurityPreMemRsvd[16]; - -/** Offset 0x022D -**/ - UINT8 UnusedUpdSpace12[3]; - -/** Offset 0x0230 - Intel Enhanced Debug - Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied - 0 : Disable, 0x400000 : Enable -**/ - UINT32 IedSize; - -/** Offset 0x0234 - Board Type - MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile - Halo, 7=UP Server - 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server -**/ - UINT8 UserBd; - -/** Offset 0x0235 - State of X2APIC_OPT_OUT bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 X2ApicOptOut; - -/** Offset 0x0236 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table - 0=Disable/Clear, 1=Enable/Set - $EN_DIS -**/ - UINT8 DmaControlGuarantee; - -/** Offset 0x0237 -**/ - UINT8 UnusedUpdSpace13[1]; - -/** Offset 0x0238 - Base addresses for VT-d function MMIO access - Base addresses for VT-d MMIO access per VT-d engine -**/ - UINT32 VtdBaseAddress[9]; - -/** Offset 0x025C - Disable VT-d - 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) - $EN_DIS -**/ - UINT8 VtdDisable; - -/** Offset 0x025D - Internal Graphics Pre-allocated Memory - Size of memory preallocated for internal graphics. - 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, - 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, - 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB -**/ - UINT8 IgdDvmt50PreAlloc; - -/** Offset 0x025E - Internal Graphics - Enable/disable internal graphics. - $EN_DIS -**/ - UINT8 InternalGfx; - -/** Offset 0x025F - Aperture Size - Select the Aperture Size. - 0:128 MB, 1:256 MB, 2:512 MB -**/ - UINT8 ApertureSize; - -/** Offset 0x0260 - Selection of the primary display device - 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics - 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics -**/ - UINT8 PrimaryDisplay; - -/** Offset 0x0261 -**/ - UINT8 UnusedUpdSpace14[3]; - -/** Offset 0x0264 - Temporary MMIO address for GTTMMADR - The reference code will use this as Temporary MMIO address space to access GTTMMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr - to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO - + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) -**/ - UINT32 GttMmAdr; - -/** Offset 0x0268 - Temporary MMIO address for GMADR - The reference code will use this as Temporary MMIO address space to access GMADR - Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to - (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress - - 0x1) (Where ApertureSize = 256MB) -**/ - UINT32 GmAdr; - -/** Offset 0x026C - Selection of iGFX GTT Memory size - 1=2MB, 2=4MB, 3=8MB, Default is 3 - 1:2MB, 2:4MB, 3:8MB -**/ - UINT16 GttSize; - -/** Offset 0x026E - Selection of PSMI Region size - 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 - 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB -**/ - UINT8 PsmiRegionSize; - -/** Offset 0x026F - Selection of PSMI Support On/Off - 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support - $EN_DIS -**/ - UINT8 GtPsmiSupport; - -/** Offset 0x0270 - Panel Power Enable - Control for enabling/disabling VDD force bit (Required only for early enabling of - eDP panel). 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 PanelPowerEnable; - -/** Offset 0x0271 - PCIe root port Function number for Hybrid Graphics dGPU - Root port Index number to indicate which PCIe root port has dGPU -**/ - UINT8 RootPortIndex; - -/** Offset 0x0272 -**/ - UINT8 UnusedUpdSpace15[2]; - -/** Offset 0x0274 - Hybrid Graphics GPIO information for PEG 0 - Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs -**/ - UINT32 SaRtd3Pcie0Gpio[24]; - -/** Offset 0x02D4 - Hybrid Graphics GPIO information for PEG 1 - Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs -**/ - UINT32 SaRtd3Pcie1Gpio[24]; - -/** Offset 0x0334 - Hybrid Graphics GPIO information for PEG 2 - Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs -**/ - UINT32 SaRtd3Pcie2Gpio[24]; - -/** Offset 0x0394 - Hybrid Graphics GPIO information for PEG 3 - Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs -**/ - UINT32 SaRtd3Pcie3Gpio[24]; - -/** Offset 0x03F4 - HG dGPU Power Delay - HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is - 300=300 microseconds -**/ - UINT16 HgDelayAfterPwrEn; - -/** Offset 0x03F6 - HG dGPU Reset Delay - HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 - microseconds -**/ - UINT16 HgDelayAfterHoldReset; - -/** Offset 0x03F8 - MMIO size adjustment for AUTO mode - Positive number means increasing MMIO size, Negative value means decreasing MMIO - size: 0 (Default)=no change to AUTO mode MMIO size -**/ - UINT16 MmioSizeAdjustment; - -/** Offset 0x03FA - MMIO Size - Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB -**/ - UINT16 MmioSize; - -/** Offset 0x03FC - Tseg Size - Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build - 0x0400000:4MB, 0x01000000:16MB -**/ - UINT32 TsegSize; - -/** Offset 0x0400 - Enable/Disable MRC TXT dependency - When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): - MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization - $EN_DIS -**/ - UINT8 TxtImplemented; - -/** Offset 0x0401 - Skip external display device scanning - Enable: Do not scan for external display device, Disable (Default): Scan external - display devices - $EN_DIS -**/ - UINT8 SkipExtGfxScan; - -/** Offset 0x0402 - Generate BIOS Data ACPI Table - Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it - $EN_DIS -**/ - UINT8 BdatEnable; - -/** Offset 0x0403 - BdatTestType - Indicates the type of Memory Training data to populate into the BDAT ACPI table. - 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D -**/ - UINT8 BdatTestType; - -/** Offset 0x0404 - Detect External Graphics device for LegacyOpROM - Detect and report if external graphics device only support LegacyOpROM or not (to - support CSM auto-enable). Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 ScanExtGfxForLegacyOpRom; - -/** Offset 0x0405 - Lock PCU Thermal Management registers - Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 - $EN_DIS -**/ - UINT8 LockPTMregs; - -/** Offset 0x0406 - Enable/Disable DMI GEN3 Static EQ Phase1 programming - Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 DmiGen3ProgramStaticEq; - -/** Offset 0x0407 - Enable/Disable PEG 0 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg0Enable; - -/** Offset 0x0408 - Enable/Disable PEG 1 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg1Enable; - -/** Offset 0x0409 - Enable/Disable PEG 2 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg2Enable; - -/** Offset 0x040A - Enable/Disable PEG 3 - Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits - it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise - 0:Disable, 1:Enable, 2:AUTO -**/ - UINT8 Peg3Enable; - -/** Offset 0x040B - PEG 0 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg0MaxLinkSpeed; - -/** Offset 0x040C - PEG 1 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg1MaxLinkSpeed; - -/** Offset 0x040D - PEG 2 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg2MaxLinkSpeed; - -/** Offset 0x040E - PEG 3 Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 Peg3MaxLinkSpeed; - -/** Offset 0x040F - PEG 0 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8 - 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8 -**/ - UINT8 Peg0MaxLinkWidth; - -/** Offset 0x0410 - PEG 1 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2, (0x3):Limit Link to x4 - 0:Auto, 1:x1, 2:x2, 3:x4 -**/ - UINT8 Peg1MaxLinkWidth; - -/** Offset 0x0411 - PEG 2 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg2MaxLinkWidth; - -/** Offset 0x0412 - PEG 3 Max Link Width - Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2): - Limit Link to x2 - 0:Auto, 1:x1, 2:x2 -**/ - UINT8 Peg3MaxLinkWidth; - -/** Offset 0x0413 - Power down unused lanes on PEG 0 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg0PowerDownUnusedLanes; - -/** Offset 0x0414 - Power down unused lanes on PEG 1 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg1PowerDownUnusedLanes; - -/** Offset 0x0415 - Power down unused lanes on PEG 2 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg2PowerDownUnusedLanes; - -/** Offset 0x0416 - Power down unused lanes on PEG 3 - (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based - on the max possible link width - 0:No power saving, 1:Auto -**/ - UINT8 Peg3PowerDownUnusedLanes; - -/** Offset 0x0417 - PCIe ASPM programming will happen in relation to the Oprom - Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): - Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after - Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume - 0:Before, 1:After -**/ - UINT8 InitPcieAspmAfterOprom; - -/** Offset 0x0418 - PCIe Disable Spread Spectrum Clocking - PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing - 0:Normal Operation, 1:Disable SSC -**/ - UINT8 PegDisableSpreadSpectrumClocking; - -/** Offset 0x0419 - DMI Gen3 Root port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 DmiGen3RootPortPreset[8]; - -/** Offset 0x0421 - DMI Gen3 End port preset values per lane - Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 DmiGen3EndPointPreset[8]; - -/** Offset 0x0429 - DMI Gen3 End port Hint values per lane - Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 DmiGen3EndPointHint[8]; - -/** Offset 0x0431 - DMI Gen3 RxCTLEp per-Bundle control - Range: 0-15, 0 is default for each bundle, must be specified based upon platform design -**/ - UINT8 DmiGen3RxCtlePeaking[4]; - -/** Offset 0x0435 - PEG Gen3 RxCTLEp per-Bundle control - Range: 0-15, 12 is default for each bundle, must be specified based upon platform design -**/ - UINT8 PegGen3RxCtlePeaking[10]; - -/** Offset 0x043F -**/ - UINT8 UnusedUpdSpace16; - -/** Offset 0x0440 - Memory data pointer for saved preset search results - The reference code will store the Gen3 Preset Search results in the SaDataHob's - PegData structure (SA_PEG_DATA) and platform code can save/restore this data to - skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0 -**/ - UINT32 PegDataPtr; - -/** Offset 0x0444 - PEG PERST# GPIO information - The reference code will use the information in this structure in order to reset - PCIe Gen3 devices during equalization, if necessary -**/ - UINT8 PegGpioData[28]; - -/** Offset 0x0460 - DeEmphasis control for DMI - DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB - 0: -6dB, 1: -3.5dB -**/ - UINT8 DmiDeEmphasis; - -/** Offset 0x0461 - PCIe Hot Plug Enable/Disable per port - 0(Default): Disable, 1: Enable -**/ - UINT8 PegRootPortHPE[4]; - -/** Offset 0x0465 - DMI Max Link Speed - Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 - Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed - 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 -**/ - UINT8 DmiMaxLinkSpeed; - -/** Offset 0x0466 - DMI Equalization Phase 2 - DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): - AUTO - Use the current default method - 0:Disable phase2, 1:Enable phase2, 2:Auto -**/ - UINT8 DmiGen3EqPh2Enable; - -/** Offset 0x0467 - DMI Gen3 Equalization Phase3 - DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 DmiGen3EqPh3Method; - -/** Offset 0x0468 - Phase2 EQ enable on the PEG 0:1:0. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg0Gen3EqPh2Enable; - -/** Offset 0x0469 - Phase2 EQ enable on the PEG 0:1:1. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg1Gen3EqPh2Enable; - -/** Offset 0x046A - Phase2 EQ enable on the PEG 0:1:2. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg2Gen3EqPh2Enable; - -/** Offset 0x046B - Phase2 EQ enable on the PEG 0:1:3. - Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1): - Enable phase 2, Auto(0x2)(Default): Use the current default method - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Peg3Gen3EqPh2Enable; - -/** Offset 0x046C - Phase3 EQ method on the PEG 0:1:0. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg0Gen3EqPh3Method; - -/** Offset 0x046D - Phase3 EQ method on the PEG 0:1:1. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg1Gen3EqPh3Method; - -/** Offset 0x046E - Phase3 EQ method on the PEG 0:1:2. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg2Gen3EqPh3Method; - -/** Offset 0x046F - Phase3 EQ method on the PEG 0:1:3. - PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, - HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software - Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static - EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just - Phase1), Disabled(0x4): Bypass Equalization Phase 3 - 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 -**/ - UINT8 Peg3Gen3EqPh3Method; - -/** Offset 0x0470 - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static - Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 PegGen3ProgramStaticEq; - -/** Offset 0x0471 - PEG Gen3 SwEq Always Attempt - Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default): - Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test - and generate new EQ values every boot, not recommended - 0:Disable, 1:Enable -**/ - UINT8 Gen3SwEqAlwaysAttempt; - -/** Offset 0x0472 - Select number of TxEq presets to test in the PCIe/DMI SwEq - Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test - Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the - current default method (Default)Auto will test Presets 7, 3, and 5. It is possible - for this default to change over time;using Auto will ensure Reference Code always - uses the latest default settings - 0:P7 P3 P5, 1:P0 to P9, 2:Auto -**/ - UINT8 Gen3SwEqNumberOfPresets; - -/** Offset 0x0473 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq - Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization - Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default): - Use the current default - 0:Disable, 1:Enable, 2:Auto -**/ - UINT8 Gen3SwEqEnableVocTest; - -/** Offset 0x0474 - PCIe Rx Compliance Testing Mode - Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1): - PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode; - it should only be set when doing PCIe compliance testing - $EN_DIS -**/ - UINT8 PegRxCemTestingMode; - -/** Offset 0x0475 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled - the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0 -**/ - UINT8 PegRxCemLoopbackLane; - -/** Offset 0x0476 - Generate PCIe BDAT Margin Table - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin - data generation, Enable(0x1): Generate PCIe BDAT margin data - $EN_DIS -**/ - UINT8 PegGenerateBdatMarginTable; - -/** Offset 0x0477 - PCIe Non-Protocol Awareness for Rx Compliance Testing - Set this policy to enable the generation and addition of PCIe margin data to the - BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness, - Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for - compliance testing - $EN_DIS -**/ - UINT8 PegRxCemNonProtocolAwareness; - -/** Offset 0x0478 - PCIe Override RxCTLE - Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1): - Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE - peak values unmodified - $EN_DIS -**/ - UINT8 PegGen3RxCtleOverride; - -/** Offset 0x0479 - PEG Gen3 Root port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane -**/ - UINT8 PegGen3RootPortPreset[20]; - -/** Offset 0x048D - PEG Gen3 End port preset values per lane - Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane -**/ - UINT8 PegGen3EndPointPreset[20]; - -/** Offset 0x04A1 - PEG Gen3 End port Hint values per lane - Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane -**/ - UINT8 PegGen3EndPointHint[20]; - -/** Offset 0x04B5 -**/ - UINT8 UnusedUpdSpace17; - -/** Offset 0x04B6 - Jitter Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterDwellTime; - -/** Offset 0x04B8 - Jitter Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 1. @warning Do not change from the default -**/ - UINT16 Gen3SwEqJitterErrorTarget; - -/** Offset 0x04BA - VOC Dwell Time for PCIe Gen3 Software Equalization - Range: 0-65535, default is 10000. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocDwellTime; - -/** Offset 0x04BC - VOC Error Target for PCIe Gen3 Software Equalization - Range: 0-65535, default is 2. @warning Do not change from the default -**/ - UINT16 Gen3SwEqVocErrorTarget; - -/** Offset 0x04BE - Enable/Disable SA IPU - Enable(Default): Enable SA IPU, Disable: Disable SA IPU - $EN_DIS -**/ - UINT8 SaIpuEnable; - -/** Offset 0x04BF - IPU IMR Configuration - 0:IPU Camera, 1:IPU Gen Default is 0 - 0:IPU Camera, 1:IPU Gen -**/ - UINT8 SaIpuImrConfiguration; - -/** Offset 0x04C0 - IMGU CLKOUT Configuration - The configuration of IMGU CLKOUT, 0: Disable;1: Enable. - $EN_DIS -**/ - UINT8 ImguClkOutEn[5]; - -/** Offset 0x04C5 - CPU Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode -**/ - UINT8 CpuTraceHubMode; - -/** Offset 0x04C6 - CPU Trace Hub Memory Region 0 - CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg0Size; - -/** Offset 0x04C7 - CPU Trace Hub Memory Region 1 - CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 CpuTraceHubMemReg1Size; - -/** Offset 0x04C8 - Enable/Disable SA OcSupport - Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport - $EN_DIS -**/ - UINT8 SaOcSupport; - -/** Offset 0x04C9 - GT slice Voltage Mode - 0(Default): Adaptive, 1: Override - 0: Adaptive, 1: Override -**/ - UINT8 GtVoltageMode; - -/** Offset 0x04CA - Maximum GTs turbo ratio override - 0(Default)=Minimal/Auto, 42=Maximum -**/ - UINT8 GtMaxOcRatio; - -/** Offset 0x04CB -**/ - UINT8 UnusedUpdSpace18; - -/** Offset 0x04CC - The voltage offset applied to GT slice - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 GtVoltageOffset; - -/** Offset 0x04CE - The GT slice voltage override which is applied to the entire range of GT frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtVoltageOverride; - -/** Offset 0x04D0 - adaptive voltage applied during turbo frequencies - 0(Default)=Minimal, 2000=Maximum -**/ - UINT16 GtExtraTurboVoltage; - -/** Offset 0x04D2 - voltage offset applied to the SA - 0(Default)=Minimal, 1000=Maximum -**/ - UINT16 SaVoltageOffset; - -/** Offset 0x04D4 - Realtime Memory Timing - 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform - realtime memory timing changes after MRC_DONE. - 0: Disabled, 1: Enabled -**/ - UINT8 RealtimeMemoryTiming; - -/** Offset 0x04D5 - TCSS Thunderbolt PCIE Root Port 0 Enable - Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie0En; - -/** Offset 0x04D6 - TCSS Thunderbolt PCIE Root Port 1 Enable - Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie1En; - -/** Offset 0x04D7 - TCSS Thunderbolt PCIE Root Port 2 Enable - Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie2En; - -/** Offset 0x04D8 - TCSS Thunderbolt PCIE Root Port 3 Enable - Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssItbtPcie3En; - -/** Offset 0x04D9 - TCSS USB HOST (xHCI) Enable - Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below - $EN_DIS -**/ - UINT8 TcssXhciEn; - -/** Offset 0x04DA - TCSS USB DEVICE (xDCI) Enable - Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled - $EN_DIS -**/ - UINT8 TcssXdciEn; - -/** Offset 0x04DB - TCSS DMA0 Enable - Set TCSS DMA0. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssDma0En; - -/** Offset 0x04DC - TCSS DMA1 Enable - Set TCSS DMA1. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssDma1En; - -/** Offset 0x04DD - This is policy to control iTBT PCIe Multiple Segment setting. - When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the - TBT PCIe RP are located at Segment1. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PcieMultipleSegmentEnabled; - -/** Offset 0x04DE - Enable/Disable SA CRID - Enable: SA CRID, Disable (Default): SA CRID - $EN_DIS -**/ - UINT8 CridEnable; - -/** Offset 0x04DF - TCSS USB Port Enable - Bitmap for per port enabling -**/ - UINT8 UsbTcPortEnPreMem; - -/** Offset 0x04E0 - PEG IMR support - This option configures the IMR support for PEG.(def=Disable) - $EN_DIS -**/ - UINT8 PegImrEnable; - -/** Offset 0x04E1 - PEG Root port number for IMR. - PEG Root port number for IMR. -**/ - UINT8 PegImrRpSelection; - -/** Offset 0x04E2 - PEG IMR size - The size of IMR to be allocated for PEG EndPoint device -**/ - UINT16 PegImrSize; - -/** Offset 0x04E4 - Enable above 4GB MMIO resource support - Enable/disable above 4GB MMIO resource support - $EN_DIS -**/ - UINT8 EnableAbove4GBMmio; - -/** Offset 0x04E5 -**/ - UINT8 SaPreMemRsvd[31]; - -/** Offset 0x0504 - HECI Timeouts - 0: Disable, 1: Enable (Default) timeout check for HECI - $EN_DIS -**/ - UINT8 HeciTimeouts; - -/** Offset 0x0505 - Force ME DID Init Status - Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set - ME DID init stat value - $EN_DIS -**/ - UINT8 DidInitStat; - -/** Offset 0x0506 - CPU Replaced Polling Disable - Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop - $EN_DIS -**/ - UINT8 DisableCpuReplacedPolling; - -/** Offset 0x0507 - ME DID Message - Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent - the DID message from being sent) - $EN_DIS -**/ - UINT8 SendDidMsg; - -/** Offset 0x0508 - Check HECI message before send - Test, 0: disable, 1: enable, Enable/Disable message check. - $EN_DIS -**/ - UINT8 DisableMessageCheck; - -/** Offset 0x0509 - Skip MBP HOB - Test, 0: disable, 1: enable, Enable/Disable MOB HOB. - $EN_DIS -**/ - UINT8 SkipMbpHob; - -/** Offset 0x050A - HECI2 Interface Communication - Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. - $EN_DIS -**/ - UINT8 HeciCommunication2; - -/** Offset 0x050B - Enable KT device - Test, 0: disable, 1: enable, Enable or Disable KT device. - $EN_DIS -**/ - UINT8 KtDeviceEnable; - -/** Offset 0x050C - HECI1 BAR address - BAR address of HECI1 -**/ - UINT32 Heci1BarAddress; - -/** Offset 0x0510 - HECI2 BAR address - BAR address of HECI2 -**/ - UINT32 Heci2BarAddress; - -/** Offset 0x0514 - HECI3 BAR address - BAR address of HECI3 -**/ - UINT32 Heci3BarAddress; - -/** Offset 0x0518 -**/ - UINT8 MePreMemRsvd[16]; - -/** Offset 0x0528 - PCH Trace Hub Mode - Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' - if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. - 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode -**/ - UINT8 PchTraceHubMode; - -/** Offset 0x0529 - PCH Trace Hub Memory Region 0 buffer Size - Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg0Size; - -/** Offset 0x052A - PCH Trace Hub Memory Region 1 buffer Size - Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, - 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB. - 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB -**/ - UINT8 PchTraceHubMemReg1Size; - -/** Offset 0x052B - Enable SMBus - Enable/disable SMBus controller. - $EN_DIS -**/ - UINT8 SmbusEnable; - -/** Offset 0x052C - Enable SMBus ARP support - Enable SMBus ARP support. - $EN_DIS -**/ - UINT8 SmbusArpEnable; - -/** Offset 0x052D - Smbus dynamic power gating - Disable or Enable Smbus dynamic power gating. - $EN_DIS -**/ - UINT8 SmbusDynamicPowerGating; - -/** Offset 0x052E - SMBUS SPD Write Disable - Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write - Disable bit. For security recommendations, SPD write disable bit must be set. - $EN_DIS -**/ - UINT8 SmbusSpdWriteDisable; - -/** Offset 0x052F - Enable SMBus Alert Pin - Enable SMBus Alert Pin. - $EN_DIS -**/ - UINT8 PchSmbAlertEnable; - -/** Offset 0x0530 - SMBUS Base Address - SMBUS Base Address (IO space). -**/ - UINT16 PchSmbusIoBase; - -/** Offset 0x0532 - Number of RsvdSmbusAddressTable. - The number of elements in the RsvdSmbusAddressTable. -**/ - UINT8 PchNumRsvdSmbusAddresses; - -/** Offset 0x0533 -**/ - UINT8 UnusedUpdSpace19; - -/** Offset 0x0534 - Point of RsvdSmbusAddressTable - Array of addresses reserved for non-ARP-capable SMBus devices. -**/ - UINT32 RsvdSmbusAddressTablePtr; - -/** Offset 0x0538 - DCI Enable - Determine if to enable DCI debug from host - $EN_DIS -**/ - UINT8 DciEn; - -/** Offset 0x0539 - Enable DCI ModPHY Pwoer Gate - Enable ModPHY Pwoer Gate when DCI is enabled - $EN_DIS -**/ - UINT8 DciModphyPg; - -/** Offset 0x053A - DCI DbC Mode - Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: - Set both USB2/3DBCEN; No Change: Comply with HW value,for PCH-LP ICL U/Y board - with D0 stepping need to Disable it by default - 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change -**/ - UINT8 DciDbcMode; - -/** Offset 0x053B - USB3 Type-C UFP2DFP Kernel/Platform Debug Support - This BIOS option enables kernel and platform debug for USB3 interface over a UFP - Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. - 0:Disabled, 1:Enabled, 2:No Change -**/ - UINT8 DciUsb3TypecUfpDbg; - -/** Offset 0x053C - Enable PCIE RP Mask - Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 - for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpEnableMask; - -/** Offset 0x0540 - Enable PCIe IMR - 0:Disable, 1:Enable - $EN_DIS -**/ - UINT8 PcieImrEnabled; - -/** Offset 0x0541 -**/ - UINT8 UnusedUpdSpace20; - -/** Offset 0x0542 - Size of PCIe IMR. - Size of PCIe IMR in megabytes -**/ - UINT16 PcieImrSize; - -/** Offset 0x0544 - Root port number for IMR. - Root port number for IMR. -**/ - UINT8 ImrRpSelection; - -/** Offset 0x0545 - Enable PCH HSIO PCIE Rx Set Ctle - Enable PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtleEnable[24]; - -/** Offset 0x055D - PCH HSIO PCIE Rx Set Ctle Value - PCH PCIe Gen 3 Set CTLE Value. -**/ - UINT8 PchPcieHsioRxSetCtle[24]; - -/** Offset 0x0575 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24]; - -/** Offset 0x058D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen1DownscaleAmp[24]; - -/** Offset 0x05A5 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24]; - -/** Offset 0x05BD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen2DownscaleAmp[24]; - -/** Offset 0x05D5 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24]; - -/** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value - PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchPcieHsioTxGen3DownscaleAmp[24]; - -/** Offset 0x0605 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen1DeEmphEnable[24]; - -/** Offset 0x061D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value - PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen1DeEmph[24]; - -/** Offset 0x0635 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24]; - -/** Offset 0x064D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph3p5[24]; - -/** Offset 0x0665 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24]; - -/** Offset 0x067D - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value - PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. -**/ - UINT8 PchPcieHsioTxGen2DeEmph6p0[24]; - -/** Offset 0x0695 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; - -/** Offset 0x069D - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen1EqBoostMag[8]; - -/** Offset 0x06A5 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; - -/** Offset 0x06AD - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen2EqBoostMag[8]; - -/** Offset 0x06B5 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; - -/** Offset 0x06BD - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. -**/ - UINT8 PchSataHsioRxGen3EqBoostMag[8]; - -/** Offset 0x06C5 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; - -/** Offset 0x06CD - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen1DownscaleAmp[8]; - -/** Offset 0x06D5 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; - -/** Offset 0x06DD - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen2DownscaleAmp[8]; - -/** Offset 0x06E5 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; - -/** Offset 0x06ED - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. -**/ - UINT8 PchSataHsioTxGen3DownscaleAmp[8]; - -/** Offset 0x06F5 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen1DeEmphEnable[8]; - -/** Offset 0x06FD - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen1DeEmph[8]; - -/** Offset 0x0705 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen2DeEmphEnable[8]; - -/** Offset 0x070D - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen2DeEmph[8]; - -/** Offset 0x0715 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override - 0: Disable; 1: Enable. -**/ - UINT8 PchSataHsioTxGen3DeEmphEnable[8]; - -/** Offset 0x071D - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. -**/ - UINT8 PchSataHsioTxGen3DeEmph[8]; - -/** Offset 0x0725 - ChipsetInit HECI message - DEPRECATED - $EN_DIS -**/ - UINT8 ChipsetInitMessage; - -/** Offset 0x0726 - Bypass ChipsetInit sync reset. - DEPRECATED - $EN_DIS -**/ - UINT8 BypassPhySyncReset; - -/** Offset 0x0727 - PCH LPC Enhance the port 8xh decoding - Original LPC only decodes one byte of port 80h. - $EN_DIS -**/ - UINT8 PchLpcEnhancePort8xhDecoding; - -/** Offset 0x0728 - PCH Port80 Route - Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. - $EN_DIS -**/ - UINT8 PchPort80Route; - -/** Offset 0x0729 - Disable and Lock Watch Dog Register - Set 1 to clear WDT status, then disable and lock WDT registers. - $EN_DIS -**/ - UINT8 WdtDisableAndLock; - -/** Offset 0x072A - Enable Intel HD Audio (Azalia) - 0: Disable, 1: Enable (Default) Azalia controller - $EN_DIS -**/ - UINT8 PchHdaEnable; - -/** Offset 0x072B - Enable PCH ISH Controller - 0: Disable, 1: Enable (Default) ISH Controller - $EN_DIS -**/ - UINT8 PchIshEnable; - -/** Offset 0x072C - Platform Debug Consent - To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type. - Enabling this BIOS option may alter the default value of other debug-related BIOS - options.\Manual: Do not use Platform Debug Consent to override other debug-relevant - policies, but the user must set each debug option manually, aimed at advanced users.\n - Note: DCI OOB (aka BSSB) uses CCA probe - 0:Disabled, 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled - (USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual -**/ - UINT8 PlatformDebugConsent; - -/** Offset 0x072D - Debug Interfaces - Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, - BIT2 - Not used. -**/ - UINT8 PcdDebugInterfaceFlags; - -/** Offset 0x072E - Serial Io Uart Debug Controller Number - Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT - Core interface, it cannot be used for debug purpose. - 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 -**/ - UINT8 SerialIoUartDebugControllerNumber; - -/** Offset 0x072F - Serial Io Uart Debug Auto Flow - Enables UART hardware flow control, CTS and RTS lines. - $EN_DIS -**/ - UINT8 SerialIoUartDebugAutoFlow; - -/** Offset 0x0730 - Serial Io Uart Debug BaudRate - Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, - 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 -**/ - UINT32 SerialIoUartDebugBaudRate; - -/** Offset 0x0734 - Serial Io Uart Debug Parity - Set default Parity. - 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartDebugParity; - -/** Offset 0x0735 - Serial Io Uart Debug Stop Bits - Set default stop bits. - 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits -**/ - UINT8 SerialIoUartDebugStopBits; - -/** Offset 0x0736 - Serial Io Uart Debug Data Bits - Set default word length. 0: Default, 5,6,7,8 - 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS -**/ - UINT8 SerialIoUartDebugDataBits; - -/** Offset 0x0737 - ISA Serial Base selection - Select ISA Serial Base address. Default is 0x3F8. - 0:0x3F8, 1:0x2F8 -**/ - UINT8 PcdIsaSerialUartBase; - -/** Offset 0x0738 - PcdSerialDebugBaudRate - Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. - 3:9600, 4:19200, 6:56700, 7:115200 -**/ - UINT8 PcdSerialDebugBaudRate; - -/** Offset 0x0739 -**/ - UINT8 UnusedUpdSpace21; - -/** Offset 0x073A - Post Code Output Port - This option configures Post Code Output Port -**/ - UINT16 PostCodeOutputPort; - -/** Offset 0x073C -**/ - UINT8 PchPreMemRsvd[32]; - -/** Offset 0x075C - Write Drive Strength/Equalization 2D - Enables/Disable Write Drive Strength/Equalization 2D - $EN_DIS -**/ - UINT8 WRDSEQT; - -/** Offset 0x075D -**/ - UINT8 UnusedUpdSpace22[4]; - -/** Offset 0x0761 -**/ - UINT8 ReservedFspmUpd[15]; -} FSP_M_CONFIG; - -/** Fsp M UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPM_ARCH_UPD FspmArchUpd; - -/** Offset 0x0040 -**/ - FSP_M_CONFIG FspmConfig; - -/** Offset 0x0770 -**/ - UINT8 UnusedUpdSpace23[6]; - -/** Offset 0x0776 -**/ - UINT16 UpdTerminator; -} FSPM_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h deleted file mode 100644 index 4aa5008356..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FspsUpd.h +++ /dev/null @@ -1,3610 +0,0 @@ -/** @file - -Copyright (c) 2019, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPSUPD_H__ -#define __FSPSUPD_H__ - -#include - -#pragma pack(1) - - -/// -/// Azalia Header structure -/// -typedef struct { - UINT16 VendorId; ///< Codec Vendor ID - UINT16 DeviceId; ///< Codec Device ID - UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. - UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. - UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer. - UINT32 Reserved; ///< Reserved for future use. Must be set to 0. -} AZALIA_HEADER; - -/// -/// Audio Azalia Verb Table structure -/// -typedef struct { - AZALIA_HEADER Header; ///< AZALIA PCH header - UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header -} AUDIO_AZALIA_VERB_TABLE; - -/// -/// Refer to the definition of PCH_INT_PIN -/// -typedef enum { - SiPchNoInt, ///< No Interrupt Pin - SiPchIntA, - SiPchIntB, - SiPchIntC, - SiPchIntD -} SI_PCH_INT_PIN; -/// -/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device. -/// -typedef struct { - UINT8 Device; ///< Device number - UINT8 Function; ///< Device function - UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN) - UINT8 Irq; ///< IRQ to be set for device. -} SI_PCH_DEVICE_INTERRUPT_CONFIG; - -#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices - - -/** Fsp S Configuration -**/ -typedef struct { - -/** Offset 0x0020 - Si Config CSM Flag. - Platform specific common policies that used by several silicon components. CSM status flag. - $EN_DIS -**/ - UINT8 SiCsmFlag; - -/** Offset 0x0021 -**/ - UINT8 UnusedUpdSpace0[3]; - -/** Offset 0x0024 - SVID SDID table Poniter. - The address of the table of SVID SDID to customize each SVID SDID entry. -**/ - UINT32 SiSsidTablePtr; - -/** Offset 0x0028 - Number of ssid table. - SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr. -**/ - UINT16 SiNumberOfSsidTableEntry; - -/** Offset 0x002A -**/ - UINT8 SiPostMemRsvd[16]; - -/** Offset 0x003A -**/ - UINT8 UnusedUpdSpace1[2]; - -/** Offset 0x003C - MicrocodeRegionBase - Memory Base of Microcode Updates -**/ - UINT32 MicrocodeRegionBase; - -/** Offset 0x0040 - MicrocodeRegionSize - Size of Microcode Updates -**/ - UINT32 MicrocodeRegionSize; - -/** Offset 0x0044 - Enable or Disable TXT - Enable or Disable TXT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TxtEnable; - -/** Offset 0x0045 - Advanced Encryption Standard (AES) feature - Enable or Disable Advanced Encryption Standard (AES) feature; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 AesEnable; - -/** Offset 0x0046 - Deprecated Skip Multi-Processor Initialization - {@deprecated SkipMpInit has been moved to FspmUpd as SkipMpInitPreMem. 0: Initialize; - 1: Skip - $EN_DIS -**/ - UINT8 SkipMpInit; - -/** Offset 0x0047 - PpinSupport to view Protected Processor Inventory Number - Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this - flag is set) for PPIN Support - 0: Disable, 1: Enable, 2: Auto -**/ - UINT8 PpinSupport; - -/** Offset 0x0048 - Turbo Mode - Enable/Disable Turbo mode. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 TurboMode; - -/** Offset 0x0049 - Power State 3 enable/disable - PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; 1: Enable. - For all VR Indexes -**/ - UINT8 Psi3Enable; - -/** Offset 0x004A - Power State 4 enable/disable - PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 Psi4Enable; - -/** Offset 0x004B -**/ - UINT8 UnusedUpdSpace2; - -/** Offset 0x004C - Imon slope correction - PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values. - Range is 0-200. 125 = 1.25. 0: Auto.For all VR Indexes -**/ - UINT16 ImonSlope; - -/** Offset 0x004E - Imon offset correction - PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer. - Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. 0: Auto -**/ - UINT16 ImonOffset; - -/** Offset 0x0050 - Enable/Disable BIOS configuration of VR - Enable/Disable BIOS configuration of VR; 0: Disable; 1: Enable.For all VR Indexes -**/ - UINT8 VrConfigEnable; - -/** Offset 0x0051 - Thermal Design Current enable/disable - PCODE MMIO Mailbox: Thermal Design Current enable/disable; 0: Disable; 1: - Enable.For all VR Indexes -**/ - UINT8 TdcEnable; - -/** Offset 0x0052 - HECI3 state - PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds. - Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms - , 8 - 8ms , 10 - 10ms.For all VR Indexe -**/ - UINT8 TdcTimeWindow; - -/** Offset 0x0053 - Thermal Design Current Lock - PCODE MMIO Mailbox: Thermal Design Current Lock; 0: Disable; 1: Enable.For - all VR Indexes -**/ - UINT8 TdcLock; - -/** Offset 0x0054 - Thermal Design Current current limit - PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units. - Range is 0-4095. 1000 = 125A. 0: Auto. For all VR Indexes -**/ - UINT16 TdcPowerLimit; - -/** Offset 0x0056 - AcLoadline - PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249. Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 AcLoadline; - -/** Offset 0x0058 - DcLoadline - PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is - 0-6249.Intel Recommended Defaults vary by domain and SKU. -**/ - UINT16 DcLoadline; - -/** Offset 0x005A - Power State 1 Threshold current - PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi1Threshold; - -/** Offset 0x005C - Power State 2 Threshold current - PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi2Threshold; - -/** Offset 0x005E - Power State 3 Threshold current - PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A. -**/ - UINT16 Psi3Threshold; - -/** Offset 0x0060 - Icc Max limit - PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A -**/ - UINT16 IccMax; - -/** Offset 0x0062 - VR Voltage Limit - PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV. -**/ - UINT16 VrVoltageLimit; - -/** Offset 0x0064 - Platform Psys slope correction - PCODE MMIO Mailbox: Platform Psys slope correction. 0 - Auto Specified in - 1/100 increment values. Range is 0-200. 125 = 1.25 -**/ - UINT8 PsysSlope; - -/** Offset 0x0065 - Platform Psys offset correction - PCODE MMIO Mailbox: Platform Psys offset correction. 0 - Auto Units 1/4, - Range 0-255. Value of 100 = 100/4 = 25 offset -**/ - UINT8 PsysOffset; - -/** Offset 0x0066 - Acoustic Noise Mitigation feature - Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program - slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.0: - Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 AcousticNoiseMitigation; - -/** Offset 0x0067 - Pre Wake Randomization time - PCODE MMIO Mailbox: Acoustic Mitigation Range.Defines the maximum pre-wake randomization - time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled. - Range 0-255 0. -**/ - UINT8 PreWake; - -/** Offset 0x0068 - Ramp Up Randomization time - PCODE MMIO Mailbox: Acoustic Mitigation Range.Defines the maximum Ramp Up randomization - time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled.Range - 0-255 0. -**/ - UINT8 RampUp; - -/** Offset 0x0069 - Ramp Down Randomization time - PCODE MMIO Mailbox: Acoustic Mitigation Range.Defines the maximum Ramp Down randomization - time in micro ticks.This can be programmed only if AcousticNoiseMitigation is enabled.Range - 0-255 0. -**/ - UINT8 RampDown; - -/** Offset 0x006A - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain - Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation - feature enabled. 0: False; 1: True - $EN_DIS -**/ - UINT8 FastPkgCRampDisableFivr; - -/** Offset 0x006B - Slew Rate configuration for Deep Package C States for VR FIVR domain - Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic - Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2: Fast/8; 3: Fast/16 - 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16 -**/ - UINT8 SlowSlewRateForFivr; - -/** Offset 0x006C - Enable VR specific mailbox command - VR specific mailbox commands. 00b - no VR specific command sent. 01b - A - VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific - command sent for PS4 exit issue. 11b - Reserved. - $EN_DIS -**/ - UINT8 SendVrMbxCmd; - -/** Offset 0x006D -**/ - UINT8 UnusedUpdSpace3; - -/** Offset 0x006E - FIVR RFI Frequency - PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. 0: - Auto. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock; - 0-1535 (Up to 153.5MHz) for 19MHz clock. -**/ - UINT16 FivrRfiFrequency; - -/** Offset 0x0070 - FIVR RFI Spread Spectrum - PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments, with range of - 0.2% to 10%. 2: 0.2%; Range: 0.2% to 10.0% (2-100). -**/ - UINT8 FivrSpreadSpectrum; - -/** Offset 0x0071 - Enable or Disable Minimum Voltage Override - Enable or disable Minimum Voltage overrides ; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 EnableMinVoltageOverride; - -/** Offset 0x0072 - Min Voltage for C8 - PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride = - 1. Range 0 to 1999mV. 0: 0mV -**/ - UINT16 MinVoltageC8; - -/** Offset 0x0074 - Min Voltage for Runtime - PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride - = 1. Range 0 to 1999mV. 0: 0mV -**/ - UINT16 MinVoltageRuntime; - -/** Offset 0x0076 - Enable or Disable MLC Streamer Prefetcher - Enable or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MlcStreamerPrefetcher; - -/** Offset 0x0077 - Enable or Disable MLC Spatial Prefetcher - Enable or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 MlcSpatialPrefetcher; - -/** Offset 0x0078 - Enable or Disable Monitor /MWAIT instructions - Enable or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MonitorMwaitEnable; - -/** Offset 0x0079 - Control on Processor Trace output scheme - Control on Processor Trace output scheme; 0: Single Range Output; 1: ToPA Output. - 0: Single Range Output, 1: ToPA Output -**/ - UINT8 ProcessorTraceOutputScheme; - -/** Offset 0x007A - Enable or Disable Processor Trace feature - Enable or Disable Processor Trace feature; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcessorTraceEnable; - -/** Offset 0x007B -**/ - UINT8 UnusedUpdSpace4[5]; - -/** Offset 0x0080 - Base of memory region allocated for Processor Trace - Base address of memory region allocated for Processor Trace. Processor Trace requires - 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT64 ProcessorTraceMemBase; - -/** Offset 0x0088 - Memory region allocation for Processor Trace - Length in bytes of memory region allocated for Processor Trace. Processor Trace - requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. 0: Disable -**/ - UINT32 ProcessorTraceMemLength; - -/** Offset 0x008C - Enable or Disable Voltage Optimization feature - Enable or Disable Voltage Optimization feature 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 VoltageOptimization; - -/** Offset 0x008D - Set Three Strike Counter Disable - False (default): Three Strike counter will be incremented and True: Prevents Three - Strike counter from incrementing; 0: False; 1: True. - 0: False, 1: True -**/ - UINT8 ThreeStrikeCounterDisable; - -/** Offset 0x008E - Enable or Disable initialization of machine check registers - Enable or Disable initialization of machine check registers; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MachineCheckEnable; - -/** Offset 0x008F - AP Idle Manner of waiting for SIPI - AP Idle Manner of waiting for SIPI; 1: HALT loop; 2: MWAIT loop; 3: RUN loop. - 1: HALT loop, 2: MWAIT loop, 3: RUN loop -**/ - UINT8 ApIdleManner; - -/** Offset 0x0090 - 1-Core Ratio Limit - 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal - to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83 -**/ - UINT8 OneCoreRatioLimit; - -/** Offset 0x0091 - 2-Core Ratio Limit - 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 -**/ - UINT8 TwoCoreRatioLimit; - -/** Offset 0x0092 - 3-Core Ratio Limit - 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 -**/ - UINT8 ThreeCoreRatioLimit; - -/** Offset 0x0093 - 4-Core Ratio Limit - 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 -**/ - UINT8 FourCoreRatioLimit; - -/** Offset 0x0094 - 5-Core Ratio Limit - 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 FiveCoreRatioLimit; - -/** Offset 0x0095 - 6-Core Ratio Limit - 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 SixCoreRatioLimit; - -/** Offset 0x0096 - 7-Core Ratio Limit - 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 SevenCoreRatioLimit; - -/** Offset 0x0097 - 8-Core Ratio Limit - 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused - 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal - to 1-Core Ratio Limit.Range is 0 to 83 - 0x0:0xFF -**/ - UINT8 EightCoreRatioLimit; - -/** Offset 0x0098 - Enable or Disable HWP - Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; - 2-3:Reserved - $EN_DIS -**/ - UINT8 Hwp; - -/** Offset 0x0099 - Hardware Duty Cycle Control - Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved - $EN_DIS -**/ - UINT8 HdcControl; - -/** Offset 0x009A - Package Long duration turbo mode time - Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds) - 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PowerLimit1Time; - -/** Offset 0x009B - Short Duration Turbo Mode - Enable or Disable short duration Turbo Mode. 0 : Disable; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit2; - -/** Offset 0x009C - Turbo settings Lock - Lock all Turbo settings Enable/Disable; 0: Disable , 1: Enable - $EN_DIS -**/ - UINT8 TurboPowerLimitLock; - -/** Offset 0x009D - Package PL3 time window - Package PL3 time window range for this policy from 0 to 64ms -**/ - UINT8 PowerLimit3Time; - -/** Offset 0x009E - Package PL3 Duty Cycle - Package PL3 Duty Cycle; Valid Range is 0 to 100 -**/ - UINT8 PowerLimit3DutyCycle; - -/** Offset 0x009F - Package PL3 Lock - Package PL3 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit3Lock; - -/** Offset 0x00A0 - Package PL4 Lock - Package PL4 Lock Enable/Disable; 0: Disable ; 1: Enable - $EN_DIS -**/ - UINT8 PowerLimit4Lock; - -/** Offset 0x00A1 - TCC Activation Offset - TCC Activation Offset. Offset from factory set TCC activation temperature at which - the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation - Temperature, in volts.For SKL Y SKU, the recommended default for this policy is - 10, For all other SKUs the recommended default are 0 -**/ - UINT8 TccActivationOffset; - -/** Offset 0x00A2 - Tcc Offset Clamp Enable/Disable - Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle - below P1.For SKL Y SKU, the recommended default for this policy is 1: Enabled, - For all other SKUs the recommended default are 0: Disabled. - $EN_DIS -**/ - UINT8 TccOffsetClamp; - -/** Offset 0x00A3 - Tcc Offset Lock - Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature - target; 0: Disabled; 1: Enabled. - $EN_DIS -**/ - UINT8 TccOffsetLock; - -/** Offset 0x00A4 - Package Long duration turbo mode power limit - Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. - Valid Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit1; - -/** Offset 0x00A8 - Package Short duration turbo mode power limit - Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit2Power; - -/** Offset 0x00AC - Package PL3 power limit - Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 PowerLimit3; - -/** Offset 0x00B0 - Package PL4 power limit - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 PowerLimit4; - -/** Offset 0x00B4 - Tcc Offset Time Window for RATL - Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 1023875 in Step size of 125 -**/ - UINT32 TccOffsetTimeWindowForRatl; - -/** Offset 0x00B8 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 HwpInterruptControl; - -/** Offset 0x00B9 - Intel Turbo Boost Max Technology 3.0 - Intel Turbo Boost Max Technology 3.0. 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbm; - -/** Offset 0x00BA - Intel Turbo Boost Max Technology 3.0 Driver - Intel Turbo Boost Max Technology 3.0 Driver 0: Disabled; 1: Enabled - $EN_DIS -**/ - UINT8 EnableItbmDriver; - -/** Offset 0x00BB - Enable or Disable Per Core P State OS control - Enable or Disable Per Core P State OS control. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 EnablePerCorePState; - -/** Offset 0x00BC - Enable or Disable HwP Autonomous Per Core P State OS control - Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; 1: - Enable - $EN_DIS -**/ - UINT8 EnableHwpAutoPerCorePstate; - -/** Offset 0x00BD - Enable or Disable HwP Autonomous EPP Grouping - Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 EnableHwpAutoEppGrouping; - -/** Offset 0x00BE - Enable or Disable EPB override over PECI - Enable or Disable EPB override over PECI. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 EnableEpbPeciOverride; - -/** Offset 0x00BF - Enable or Disable Fast MSR for IA32_HWP_REQUEST - Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;1: Enable - $EN_DIS -**/ - UINT8 EnableFastMsrHwpReq; - -/** Offset 0x00C0 - Minimum Ring ratio limit override - Minimum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MinRingRatioLimit; - -/** Offset 0x00C1 - Maximum Ring ratio limit override - Maximum Ring ratio limit override. 0: Hardware defaults. Range: 0 - Max turbo - ratio limit -**/ - UINT8 MaxRingRatioLimit; - -/** Offset 0x00C2 - Custom Ratio State Entries - The number of custom ratio state entries, ranges from 0 to 40 for a valid custom - ratio table.Sets the number of custom P-states. At least 2 states must be present -**/ - UINT8 NumberOfEntries; - -/** Offset 0x00C3 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128 -**/ - UINT8 Custom1PowerLimit1Time; - -/** Offset 0x00C4 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128 -**/ - UINT8 Custom2PowerLimit1Time; - -/** Offset 0x00C5 - Custom Short term Power Limit time window - Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128 -**/ - UINT8 Custom3PowerLimit1Time; - -/** Offset 0x00C6 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255 -**/ - UINT8 Custom1TurboActivationRatio; - -/** Offset 0x00C7 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255 -**/ - UINT8 Custom2TurboActivationRatio; - -/** Offset 0x00C8 - Custom Turbo Activation Ratio - Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255 -**/ - UINT8 Custom3TurboActivationRatio; - -/** Offset 0x00C9 - ConfigTdp mode settings Lock - Lock the ConfigTdp mode settings from runtime changes; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ConfigTdpLock; - -/** Offset 0x00CA - Load Configurable TDP SSDT - Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ConfigTdpBios; - -/** Offset 0x00CB - Max P-State Ratio - Max P-State Ratio, Valid Range 0 to 0x7F -**/ - UINT8 MaxRatio; - -/** Offset 0x00CC - P-state ratios for custom P-state table - P-state ratios for custom P-state table. NumberOfEntries has valid range between - 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries] - are configurable. Valid Range of each entry is 0 to 0x7F -**/ - UINT8 StateRatio[40]; - -/** Offset 0x00F4 - Short term Power Limit value for custom cTDP level 1 - Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit1; - -/** Offset 0x00F8 - Long term Power Limit value for custom cTDP level 1 - Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom1PowerLimit2; - -/** Offset 0x00FC - Short term Power Limit value for custom cTDP level 2 - Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit1; - -/** Offset 0x0100 - Long term Power Limit value for custom cTDP level 2 - Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom2PowerLimit2; - -/** Offset 0x0104 - Short term Power Limit value for custom cTDP level 3 - Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit1; - -/** Offset 0x0108 - Long term Power Limit value for custom cTDP level 3 - Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid - Range 0 to 4095875 in Step size of 125 -**/ - UINT32 Custom3PowerLimit2; - -/** Offset 0x010C - PL1 Enable value - PL1 Enable value to limit average platform power. 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit1; - -/** Offset 0x010D - PL1 timewindow - PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16 - , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128 -**/ - UINT8 PsysPowerLimit1Time; - -/** Offset 0x010E - PL2 Enable Value - PL2 Enable activates the PL2 value to limit average platform power.0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PsysPowerLimit2; - -/** Offset 0x010F -**/ - UINT8 UnusedUpdSpace5; - -/** Offset 0x0110 - Platform Power Pmax - PCODE MMIO Mailbox: Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. - Range 0-1024 Watts. Value of 800 = 100W -**/ - UINT16 PsysPmax; - -/** Offset 0x0112 -**/ - UINT8 UnusedUpdSpace6[2]; - -/** Offset 0x0114 - Platform PL1 power - Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit1Power; - -/** Offset 0x0118 - Platform PL2 power - Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range - 0 to 4095875 in Step size of 125 -**/ - UINT32 PsysPowerLimit2Power; - -/** Offset 0x011C - Enable or Disable Intel SpeedStep Technology - Enable or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Eist; - -/** Offset 0x011D - Enable or Disable Energy Efficient P-state - Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientPState; - -/** Offset 0x011E - Enable or Disable Energy Efficient Turbo - Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable; - 1: Enable - $EN_DIS -**/ - UINT8 EnergyEfficientTurbo; - -/** Offset 0x011F - Enable or Disable T states - Enable or Disable T states; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 TStates; - -/** Offset 0x0120 - Enable or Disable Bi-Directional PROCHOT# - Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 BiProcHot; - -/** Offset 0x0121 - Enable or Disable PROCHOT# signal being driven externally - Enable or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableProcHotOut; - -/** Offset 0x0122 - Enable or Disable PROCHOT# Response - Enable or Disable PROCHOT# Response; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ProcHotResponse; - -/** Offset 0x0123 - Enable or Disable VR Thermal Alert - Enable or Disable VR Thermal Alert; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 DisableVrThermalAlert; - -/** Offset 0x0124 - Enable or Disable Thermal Reporting - Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 AutoThermalReporting; - -/** Offset 0x0125 - Enable or Disable Thermal Monitor - Enable or Disable Thermal Monitor; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ThermalMonitor; - -/** Offset 0x0126 - Enable or Disable CPU power states (C-states) - Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 Cx; - -/** Offset 0x0127 - Configure C-State Configuration Lock - Configure C-State Configuration Lock; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmgCstCfgCtrlLock; - -/** Offset 0x0128 - Enable or Disable Enhanced C-states - Enable or Disable Enhanced C-states. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1e; - -/** Offset 0x0129 - Enable or Disable C1 Cstate Demotion - Enable or Disable C1 Cstate Demotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateAutoDemotion; - -/** Offset 0x012A - Enable or Disable C1 Cstate UnDemotion - Enable or Disable C1 Cstate UnDemotion. Disable; 1: Enable - $EN_DIS -**/ - UINT8 C1StateUnDemotion; - -/** Offset 0x012B - Enable or Disable Package Cstate Demotion - Enable or Disable Package Cstate Demotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateDemotion; - -/** Offset 0x012C - Enable or Disable Package Cstate UnDemotion - Enable or Disable Package Cstate UnDemotion. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 PkgCStateUnDemotion; - -/** Offset 0x012D - Enable or Disable CState-Pre wake - Enable or Disable CState-Pre wake. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 CStatePreWake; - -/** Offset 0x012E - Enable or Disable TimedMwait Support. - Enable or Disable TimedMwait Support. 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 TimedMwait; - -/** Offset 0x012F - Enable or Disable IO to MWAIT redirection - Enable or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 CstCfgCtrIoMwaitRedirection; - -/** Offset 0x0130 - Set the Max Pkg Cstate - Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep - C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S , - 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto -**/ - UINT8 PkgCStateLimit; - -/** Offset 0x0131 - TimeUnit for C-State Latency Control1 - TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl1TimeUnit; - -/** Offset 0x0132 - TimeUnit for C-State Latency Control2 - TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl2TimeUnit; - -/** Offset 0x0133 - TimeUnit for C-State Latency Control3 - TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl3TimeUnit; - -/** Offset 0x0134 - TimeUnit for C-State Latency Control4 - Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl4TimeUnit; - -/** Offset 0x0135 - TimeUnit for C-State Latency Control5 - TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns - , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns -**/ - UINT8 CstateLatencyControl5TimeUnit; - -/** Offset 0x0136 - Interrupt Redirection Mode Select - Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7: - No change. -**/ - UINT8 PpmIrmSetting; - -/** Offset 0x0137 - Lock prochot configuration - Lock prochot configuration Enable/Disable; 0: Disable; 1: Enable - $EN_DIS -**/ - UINT8 ProcHotLock; - -/** Offset 0x0138 - Race To Halt - Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency - in order to enter pkg C-State faster to reduce overall power. (RTH is controlled - through MSR 1FC bit 20)Disable; 1: Enable - $EN_DIS -**/ - UINT8 RaceToHalt; - -/** Offset 0x0139 - Configuration for boot TDP selection - Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP - Up;0xFF : Deactivate -**/ - UINT8 ConfigTdpLevel; - -/** Offset 0x013A - Interrupt Response Time Limit of C-State LatencyContol1 - Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl1Irtl; - -/** Offset 0x013C - Interrupt Response Time Limit of C-State LatencyContol2 - Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl2Irtl; - -/** Offset 0x013E - Interrupt Response Time Limit of C-State LatencyContol3 - Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl3Irtl; - -/** Offset 0x0140 - Interrupt Response Time Limit of C-State LatencyContol4 - Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl4Irtl; - -/** Offset 0x0142 - Interrupt Response Time Limit of C-State LatencyContol5. 0 is Auto. - Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF. - 0 is Auto. -**/ - UINT16 CstateLatencyControl5Irtl; - -/** Offset 0x0144 - P-state ratios for max 16 version of custom P-state table - P-state ratios for max 16 version of custom P-state table. This table is used for - OS versions limited to a max of 16 P-States. If the first entry of this table is - 0, or if Number of Entries is 16 or less, then this table will be ignored, and - up to the top 16 values of the StateRatio table will be used instead. Valid Range - of each entry is 0 to 0x7F -**/ - UINT8 StateRatioMax16[16]; - -/** Offset 0x0154 - CpuBistData - Pointer CPU BIST Data -**/ - UINT32 CpuBistData; - -/** Offset 0x0158 - CpuMpPpi - Pointer for CpuMpPpi -**/ - UINT32 CpuMpPpi; - -/** Offset 0x015C - CpuMpHob - Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage. -**/ - UINT32 CpuMpHob; - -/** Offset 0x0160 -**/ - UINT8 CpuPostMemRsvd[16]; - -/** Offset 0x0170 - BgpdtHash[4] - BgpdtHash values -**/ - UINT64 BgpdtHash[4]; - -/** Offset 0x0190 - BiosGuardAttr - BiosGuardAttr default values -**/ - UINT32 BiosGuardAttr; - -/** Offset 0x0194 -**/ - UINT8 UnusedUpdSpace7[4]; - -/** Offset 0x0198 - BiosGuardModulePtr - BiosGuardModulePtr default values -**/ - UINT64 BiosGuardModulePtr; - -/** Offset 0x01A0 - SendEcCmd - SendEcCmd function pointer. \n - @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE - EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode -**/ - UINT64 SendEcCmd; - -/** Offset 0x01A8 - EcCmdProvisionEav - Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC -**/ - UINT8 EcCmdProvisionEav; - -/** Offset 0x01A9 - EcCmdLock - EcCmdLock default values. Locks Ephemeral Authorization Value sent previously -**/ - UINT8 EcCmdLock; - -/** Offset 0x01AA -**/ - UINT8 UnusedUpdSpace8[6]; - -/** Offset 0x01B0 - SgxEpoch0 - SgxEpoch0 default values -**/ - UINT64 SgxEpoch0; - -/** Offset 0x01B8 - SgxEpoch1 - SgxEpoch1 default values -**/ - UINT64 SgxEpoch1; - -/** Offset 0x01C0 - SgxSinitNvsData - SgxSinitNvsData default values -**/ - UINT8 SgxSinitNvsData; - -/** Offset 0x01C1 - SgxSinitDataFromTpm - SgxSinitDataFromTpm default values -**/ - UINT8 SgxSinitDataFromTpm; - -/** Offset 0x01C2 -**/ - UINT8 SecurityPostMemRsvd[16]; - -/** Offset 0x01D2 - Enable Device 4 - Enable/disable Device 4 - $EN_DIS -**/ - UINT8 Device4Enable; - -/** Offset 0x01D3 - DEPRECATED SA CRID - Deprecated, use FSPM_UPD.FspmConfig.CridEnable instead - $EN_DIS -**/ - UINT8 CridEnableDeprecated; - -/** Offset 0x01D4 - Skip PAM register lock - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - $EN_DIS -**/ - UINT8 SkipPamLock; - -/** Offset 0x01D5 - EDRAM Test Mode - Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default): - PAM registers will be locked by RC - 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode -**/ - UINT8 EdramTestMode; - -/** Offset 0x01D6 - DMI ASPM - 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1 - 0:Disable, 1:L0s, 2:L1, 3:L0sL1 -**/ - UINT8 DmiAspm; - -/** Offset 0x01D7 - PchDmiCwbEnable - Central Write Buffer feature configurable and disabled by default - $EN_DIS -**/ - UINT8 PchDmiCwbEnable; - -/** Offset 0x01D8 - DMI Extended Sync Control - Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended - Sync Control - $EN_DIS -**/ - UINT8 DmiExtSync; - -/** Offset 0x01D9 - DMI IOT Control - Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control - $EN_DIS -**/ - UINT8 DmiIot; - -/** Offset 0x01DA - PCIe DeEmphasis control per root port - 0: -6dB, 1(Default): -3.5dB - 0:-6dB, 1:-3.5dB -**/ - UINT8 PegDeEmphasis[4]; - -/** Offset 0x01DE - PCIe Slot Power Limit value per root port - Slot power limit value per root port -**/ - UINT8 PegSlotPowerLimitValue[4]; - -/** Offset 0x01E2 - PCIe Slot Power Limit scale per root port - Slot power limit scale per root port - 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x -**/ - UINT8 PegSlotPowerLimitScale[4]; - -/** Offset 0x01E6 - PCIe Physical Slot Number per root port - Physical Slot Number per root port -**/ - UINT16 PegPhysicalSlotNumber[4]; - -/** Offset 0x01EE - PEG Max Payload size per root port - 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B - 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B -**/ - UINT8 PegMaxPayload[4]; - -/** Offset 0x01F2 -**/ - UINT8 UnusedUpdSpace9[2]; - -/** Offset 0x01F4 - Graphics Configuration Ptr - Points to VBT -**/ - UINT32 GraphicsConfigPtr; - -/** Offset 0x01F8 - Logo Pointer - Points to PEI Display Logo Image -**/ - UINT32 LogoPtr; - -/** Offset 0x01FC - Logo Size - Size of PEI Display Logo Image -**/ - UINT32 LogoSize; - -/** Offset 0x0200 - Blt Buffer Address - Address of Blt buffer -**/ - UINT32 BltBufferAddress; - -/** Offset 0x0204 - Blt Buffer Size - Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of - EFI_GRAPHICS_OUTPUT_BLT_PIXEL) -**/ - UINT32 BltBufferSize; - -/** Offset 0x0208 - Enable/Disable PavpEnable - Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable - $EN_DIS -**/ - UINT8 PavpEnable; - -/** Offset 0x0209 - CdClock Frequency selection - 0: (Default) Auto (Max based on reference clock frequency), 1: 307.2, 2: 312 Mhz, - 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz - 0: Auto (Max based on reference clock frequency), 1: 307.2, 2: 312 Mhz, 3: 552 Mhz, - 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz -**/ - UINT8 CdClock; - -/** Offset 0x020A - Enable/Disable PeiGraphicsPeimInit - Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit - $EN_DIS -**/ - UINT8 PeiGraphicsPeimInit; - -/** Offset 0x020B - Enable/Disable IGFX RenderStandby - Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby - $EN_DIS -**/ - UINT8 RenderStandby; - -/** Offset 0x020C - Enable/Disable IGFX PmSupport - Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport - $EN_DIS -**/ - UINT8 PmSupport; - -/** Offset 0x020D - Enable/Disable CdynmaxClamp - Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp - $EN_DIS -**/ - UINT8 CdynmaxClampEnable; - -/** Offset 0x020E - GT Frequency Limit - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz - 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, - 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: - 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, - 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz, - 0x18: 1200 Mhz -**/ - UINT8 GtFreqMax; - -/** Offset 0x020F - Disable Turbo GT - 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency - $EN_DIS -**/ - UINT8 DisableTurboGt; - -/** Offset 0x0210 - Enable/Disable CdClock Init - Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full - CD clock if not initialized by Gfx PEIM - $EN_DIS -**/ - UINT8 SkipCdClockInit; - -/** Offset 0x0211 - Enable or disable HPD of DDI port-A device - 0=Disabled,1(Default)=eDP, 2=MIPI DSI - 0:Disabled, 1:eDP, 2:MIPI DSI -**/ - UINT8 DdiPortAConfig; - -/** Offset 0x0212 - Enable or disable HPD of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBHpd; - -/** Offset 0x0213 - Enable or disable HPD of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCHpd; - -/** Offset 0x0214 - Enable or disable HPD of DDI port 1 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort1Hpd; - -/** Offset 0x0215 - Enable or disable HPD of DDI port 2 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort2Hpd; - -/** Offset 0x0216 - Enable or disable HPD of DDI port 3 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort3Hpd; - -/** Offset 0x0217 - Enable or disable HPD of DDI port 4 - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPort4Hpd; - -/** Offset 0x0218 - Enable or disable DDC of DDI port B - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortBDdc; - -/** Offset 0x0219 - Enable or disable DDC of DDI port C - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 DdiPortCDdc; - -/** Offset 0x021A - Enable DDC setting of DDI Port 1 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort1Ddc; - -/** Offset 0x021B - Enable DDC setting of DDI Port 2 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort2Ddc; - -/** Offset 0x021C - Enable DDC setting of DDI Port 3 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort3Ddc; - -/** Offset 0x021D - Enable DDC setting of DDI Port 4 - 0=Disable, 1=DDC(Default) - 0: Disable, 1: DDC -**/ - UINT8 DdiPort4Ddc; - -/** Offset 0x021E - Enable or disable GNA device - 0=Disable, 1(Default)=Enable - $EN_DIS -**/ - UINT8 GnaEnable; - -/** Offset 0x021F - USB override in IOM - This policy will enable/disable USB Connect override in IOM - $EN_DIS -**/ - UINT8 UsbOverride; - -/** Offset 0x0220 - VCCST request for IOM - This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5 - $EN_DIS -**/ - UINT8 VccSt; - -/** Offset 0x0221 - Enable D3 Hot in TCSS - This policy will enable/disable D3 hot support in IOM - $EN_DIS -**/ - UINT8 D3HotEnable; - -/** Offset 0x0222 - Enable D3 Cold in TCSS - This policy will enable/disable D3 cold support in IOM - $EN_DIS -**/ - UINT8 D3ColdEnable; - -/** Offset 0x0223 - Enable/Disable PMC-PD Solution - This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution - $EN_DIS -**/ - UINT8 PmcPdEnable; - -/** Offset 0x0224 - Enable/Disable PTM - This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports - $EN_DIS -**/ - UINT8 PtmEnabled[4]; - -/** Offset 0x0228 - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 SaPcieItbtRpLtrEnable[4]; - -/** Offset 0x022C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4]; - -/** Offset 0x0230 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4]; - -/** Offset 0x0234 - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4]; - -/** Offset 0x023C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4]; - -/** Offset 0x0240 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4]; - -/** Offset 0x0244 - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4]; - -/** Offset 0x024C - Force LTR Override - Force LTR Override. -**/ - UINT8 SaPcieItbtRpForceLtrOverride[4]; - -/** Offset 0x0250 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 SaPcieItbtRpLtrConfigLock[4]; - -/** Offset 0x0254 - Enable VMD controller - Enable/disable to VMD controller. - $EN_DIS -**/ - UINT8 VmdEnable; - -/** Offset 0x0255 - Enable VMD portA Support - Enable/disable to VMD portA Support. - $EN_DIS -**/ - UINT8 VmdPortA; - -/** Offset 0x0256 - Enable VMD portB Support - Enable/disable to VMD portB Support. - $EN_DIS -**/ - UINT8 VmdPortB; - -/** Offset 0x0257 - Enable VMD portC Support - Enable/disable to VMD portC Support. - $EN_DIS -**/ - UINT8 VmdPortC; - -/** Offset 0x0258 - Enable VMD portD Support - Enable/disable to VMD portD Support. - $EN_DIS -**/ - UINT8 VmdPortD; - -/** Offset 0x0259 - VMD Config Bar size - Set The VMD Config Bar Size. -**/ - UINT8 VmdCfgBarSz; - -/** Offset 0x025A - VMD Config Bar Attributes - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default) - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH -**/ - UINT8 VmdCfgBarAttr; - -/** Offset 0x025B - VMD Mem Bar1 size - Set The VMD Mem Bar1 Size. -**/ - UINT8 VmdMemBarSz1; - -/** Offset 0x025C - VMD Mem Bar1 Attributes - 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH -**/ - UINT8 VmdMemBar1Attr; - -/** Offset 0x025D - VMD Mem Bar2 size - Set The VMD Mem Bar2 Size. -**/ - UINT8 VmdMemBarSz2; - -/** Offset 0x025E - VMD Mem Bar2 Attributes - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH - 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH -**/ - UINT8 VmdMemBar2Attr; - -/** Offset 0x025F -**/ - UINT8 UnusedUpdSpace10[1]; - -/** Offset 0x0260 - TypeC port GPIO setting - GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined - in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Icl - = IceLake) -**/ - UINT32 IomTypeCPortPadCfg[8]; - -/** Offset 0x0280 - TCSS Aux Orientation Override Enable - Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides -**/ - UINT16 TcssAuxOri; - -/** Offset 0x0282 - TCSS HSL Orientation Override Enable - Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides -**/ - UINT16 TcssHslOri; - -/** Offset 0x0284 - PCH USB OverCurrent mapping enable - 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin - mapping allow for NOA usage of OC pins - $EN_DIS -**/ - UINT8 PchUsbOverCurrentEnable; - -/** Offset 0x0285 - CPU USB3 Port Over Current Pin - Describe the specific over current pin number of USBC Port N. -**/ - UINT8 CpuUsb3OverCurrentPin[8]; - -/** Offset 0x028D - TCSS USB Port Enable - Bits 0, 1, ... max Type C port control enables -**/ - UINT8 UsbTcPortEn; - -/** Offset 0x028E -**/ - UINT8 UnusedUpdSpace11[2]; - -/** Offset 0x0290 - ITBT DMA UUID - TCSS DMA1, DMA2 UUID Number -**/ - UINT32 IclAxITbtDmaUuid[2]; - -/** Offset 0x0298 - ITBT Root Port Enable - ITBT Root Port Enable, 0:Disable, 1:Enable - 0:Disable, 1:Enable -**/ - UINT8 ITbtPcieRootPortEn[4]; - -/** Offset 0x029C - ITBTForcePowerOn Timeout value - ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000. - 100 = 100 ms. -**/ - UINT16 ITbtForcePowerOnTimeoutInMs; - -/** Offset 0x029E - ITbtConnectTopology Timeout value - ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range - is 0-10000. 100 = 100 ms. -**/ - UINT16 ITbtConnectTopologyTimeoutInMs; - -/** Offset 0x02A0 - TcssXhciEnableComplianceMode - Set Compliance Mode. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssXhciEnableComplianceMode; - -/** Offset 0x02A1 - Enable/Disable PEG GEN3 Static EQ Phase1 programming - Program Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets - Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 SaPcieGen3ProgramStaticEq; - -/** Offset 0x02A2 - Enable/Disable GEN4 Static EQ Phase1 programming - Program Gen4 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static Presets - Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming - $EN_DIS -**/ - UINT8 SaPcieGen4ProgramStaticEq; - -/** Offset 0x02A3 - TcssLoopbackModeBitMap - Set Loopback Mode Bit Map. 0:Disabled 1:Enabled - $EN_DIS -**/ - UINT8 TcssLoopbackModeBitMap; - -/** Offset 0x02A4 - ITBT DMA UUID - TCSS DMA1, DMA2 LTR value -**/ - UINT16 ITbtDmaLtr[2]; - -/** Offset 0x02A8 -**/ - UINT8 SaPostMemRsvd[3]; - -/** Offset 0x02AB - HECI3 state - The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable - $EN_DIS -**/ - UINT8 Heci3Enabled; - -/** Offset 0x02AC - ME Unconfig on RTC clear - 0: Disable ME Unconfig On Rtc Clear. 1: Enable ME Unconfig On Rtc Clear. - 2: Cmos is clear, status unkonwn. 3: Reserved - 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos - is clear, 3: Reserved -**/ - UINT8 MeUnconfigOnRtcClear; - -/** Offset 0x02AD - End of Post message - Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): - EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE - 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved -**/ - UINT8 EndOfPostMessage; - -/** Offset 0x02AE - D0I3 Setting for HECI Disable - Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all - HECI devices - $EN_DIS -**/ - UINT8 DisableD0I3SettingForHeci; - -/** Offset 0x02AF - Mctp Broadcast Cycle - Test, Determine if MCTP Broadcast is enabled 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 MctpBroadcastCycle; - -/** Offset 0x02B0 -**/ - UINT8 MePostMemRsvd[10]; - -/** Offset 0x02BA - AMT Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality. - $EN_DIS -**/ - UINT8 AmtEnabled; - -/** Offset 0x02BB - WatchDog Timer Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. - $EN_DIS -**/ - UINT8 WatchDog; - -/** Offset 0x02BC - ASF Switch - Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality. - $EN_DIS -**/ - UINT8 AsfEnabled; - -/** Offset 0x02BD - PET Progress - Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive - PET Events. - $EN_DIS -**/ - UINT8 FwProgress; - -/** Offset 0x02BE - OS Timer - 16 bits Value, Set OS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerOs; - -/** Offset 0x02C0 - BIOS Timer - 16 bits Value, Set BIOS watchdog timer. - $EN_DIS -**/ - UINT16 WatchDogTimerBios; - -/** Offset 0x02C2 - Manageability Mode set by Mebx - Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode. - $EN_DIS -**/ - UINT8 ManageabilityMode; - -/** Offset 0x02C3 - SOL Switch - Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtSolEnabled; - -/** Offset 0x02C4 - Remote Assistance Trigger Availablilty - Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx - $EN_DIS -**/ - UINT8 RemoteAssistance; - -/** Offset 0x02C5 - KVM Switch - Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx - $EN_DIS -**/ - UINT8 AmtKvmEnabled; - -/** Offset 0x02C6 - MEBX execution - Enable/Disable. 0: Disable, 1: enable, Force MEBX execution - $EN_DIS -**/ - UINT8 ForcMebxSyncUp; - -/** Offset 0x02C7 -**/ - UINT8 AmtPostMemRsvd[10]; - -/** Offset 0x02D1 - SPI0 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi0CsPolarity[2]; - -/** Offset 0x02D3 - SPI1 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi1CsPolarity[2]; - -/** Offset 0x02D5 - SPI2 Chip Select Polarity - Sets polarity for each chip Select. Available options: 0:PchSerialIoCsActiveLow, - 1:PchSerialIoCsActiveHigh -**/ - UINT8 SerialIoSpi2CsPolarity[2]; - -/** Offset 0x02D7 - SPI0 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi0CsEnable[2]; - -/** Offset 0x02D9 - SPI1 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi1CsEnable[2]; - -/** Offset 0x02DB - SPI2 Chip Select Enable - 0:Disabled, 1:Enabled. Enables GPIO for CS0 or CS1 if it is Enabled -**/ - UINT8 SerialIoSpi2CsEnable[2]; - -/** Offset 0x02DD - SPIn Device Mode - Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available - modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden -**/ - UINT8 SerialIoSpiMode[3]; - -/** Offset 0x02E0 - SPIn Default Chip Select Output - Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available - options: 0:CS0, 1:CS1 -**/ - UINT8 SerialIoSpiDefaultCsOutput[3]; - -/** Offset 0x02E3 - SPIn Default Chip Select Mode HW/SW - Sets Default CS Mode Hardware or Software. N represents controller index: SPI0, - SPI1, ... Available options: 0:HW, 1:SW -**/ - UINT8 SerialIoSpiCsMode[3]; - -/** Offset 0x02E6 - SPIn Default Chip Select State Low/High - Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ... - Available options: 0:Low, 1:High -**/ - UINT8 SerialIoSpiCsState[3]; - -/** Offset 0x02E9 - PCH SerialIo I2C Pads Termination - 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up, - 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5 - pads termination respectively. One byte for each controller, byte0 for I2C0, byte1 - for I2C1, and so on. -**/ - UINT8 PchSerialIoI2cPadsTermination[6]; - -/** Offset 0x02EF - I2Cn Device Mode - Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available - modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden -**/ - UINT8 SerialIoI2cMode[6]; - -/** Offset 0x02F5 - UARTn Device Mode - Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available - modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, - 4:SerialIoUartSkipInit -**/ - UINT8 SerialIoUartMode[3]; - -/** Offset 0x02F8 - Default BaudRate for each Serial IO UART - Set default BaudRate Supported from 0 - default to 6000000 -**/ - UINT32 SerialIoUartBaudRate[3]; - -/** Offset 0x0304 - Default ParityType for each Serial IO UART - Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity -**/ - UINT8 SerialIoUartParity[3]; - -/** Offset 0x0307 - Default DataBits for each Serial IO UART - Set default word length. 0: Default, 5,6,7,8 -**/ - UINT8 SerialIoUartDataBits[3]; - -/** Offset 0x030A - Default StopBits for each Serial IO UART - Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: - TwoStopBits -**/ - UINT8 SerialIoUartStopBits[3]; - -/** Offset 0x030D - Power Gating mode for each Serial IO UART that works in COM mode - Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto -**/ - UINT8 SerialIoUartPowerGating[3]; - -/** Offset 0x0310 - Enable Dma for each Serial IO UART that supports it - Set DMA/PIO mode. 0: Disabled, 1: Enabled -**/ - UINT8 SerialIoUartDmaEnable[3]; - -/** Offset 0x0313 - Enables UART hardware flow control, CTS and RTS lines - Enables UART hardware flow control, CTS and RTS lines. -**/ - UINT8 SerialIoUartAutoFlow[3]; - -/** Offset 0x0316 -**/ - UINT8 UnusedUpdSpace12[2]; - -/** Offset 0x0318 - SerialIoUartRxPinMux - Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for - possible values. -**/ - UINT32 SerialIoUartRxPinMux[3]; - -/** Offset 0x0324 - SerialIoUartTxPinMux - Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for - possible values. -**/ - UINT32 SerialIoUartTxPinMux[3]; - -/** Offset 0x0330 - SerialIoUartRtsPinMux - Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* - for possible values. -**/ - UINT32 SerialIoUartRtsPinMux[3]; - -/** Offset 0x033C - SerialIoUartCtsPinMux - Select SerialIo Uart Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* - for possible values. -**/ - UINT32 SerialIoUartCtsPinMux[3]; - -/** Offset 0x0348 - UART Number For Debug Purpose - UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected - as CNVi BT Core interface, it cannot be used for debug purpose. - 0:UART0, 1:UART1, 2:UART2 -**/ - UINT8 SerialIoDebugUartNumber; - -/** Offset 0x0349 - Enable LAN - Enable/disable LAN controller. - $EN_DIS -**/ - UINT8 PchLanEnable; - -/** Offset 0x034A - Enable PCH Lan LTR capabilty of PCH internal LAN - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchLanLtrEnable; - -/** Offset 0x034B - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. - $EN_DIS -**/ - UINT8 PchHdaDspEnable; - -/** Offset 0x034C - Enable Pme - Enable Azalia wake-on-ring. - $EN_DIS -**/ - UINT8 PchHdaPme; - -/** Offset 0x034D - VC Type - Virtual Channel Type Select: 0: VC0, 1: VC1. - 0: VC0, 1: VC1 -**/ - UINT8 PchHdaVcType; - -/** Offset 0x034E - HD Audio Link Frequency - HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz. - 0: 6MHz, 1: 12MHz, 2: 24MHz -**/ - UINT8 PchHdaLinkFrequency; - -/** Offset 0x034F - iDisp-Link Frequency - iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. - 4: 96MHz, 3: 48MHz -**/ - UINT8 PchHdaIDispLinkFrequency; - -/** Offset 0x0350 - iDisp-Link T-mode - iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T - 0: 2T, 2: 4T, 3: 8T, 4: 16T -**/ - UINT8 PchHdaIDispLinkTmode; - -/** Offset 0x0351 - Universal Audio Architecture compliance for DSP enabled system - 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox - driver or SST driver supported). - $EN_DIS -**/ - UINT8 PchHdaDspUaaCompliance; - -/** Offset 0x0352 - iDisplay Audio Codec disconnection - 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. - $EN_DIS -**/ - UINT8 PchHdaIDispCodecDisconnect; - -/** Offset 0x0353 - PCH HDA Codec Sx Wake Capability - Capability to detect wake initiated by a codec in Sx -**/ - UINT8 PchHdaCodecSxWakeCapability; - -/** Offset 0x0354 - HD Audio Reset Wait Timer - The delay timer after Azalia reset, the value is number of microseconds. Default is 600. -**/ - UINT16 PchHdaResetWaitTimer; - -/** Offset 0x0356 - PCH HDA Verb Table Entry Number - Number of Entries in Verb Table. -**/ - UINT8 PchHdaVerbTableEntryNum; - -/** Offset 0x0357 -**/ - UINT8 UnusedUpdSpace13; - -/** Offset 0x0358 - PCH HDA Verb Table Pointer - Pointer to Array of pointers to Verb Table. -**/ - UINT32 PchHdaVerbTablePtr; - -/** Offset 0x035C - Enable HD Audio Link - Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkHda; - -/** Offset 0x035D - Enable HD Audio DMIC0 Link - Enable/disable HD Audio DMIC0 link. Muxed with SNDW4. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic0; - -/** Offset 0x035E - Enable HD Audio DMIC1 Link - Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkDmic1; - -/** Offset 0x035F - Enable HD Audio SSP0 Link - Enable/disable HD Audio SSP0/I2S link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp0; - -/** Offset 0x0360 - Enable HD Audio SSP1 Link - Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp1; - -/** Offset 0x0361 - Enable HD Audio SSP2 Link - Enable/disable HD Audio SSP2/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp2; - -/** Offset 0x0362 - Enable HD Audio SSP3 Link - Enable/disable HD Audio SSP3/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp3; - -/** Offset 0x0363 - Enable HD Audio SSP4 Link - Enable/disable HD Audio SSP4/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp4; - -/** Offset 0x0364 - Enable HD Audio SSP5 Link - Enable/disable HD Audio SSP5/I2S link. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSsp5; - -/** Offset 0x0365 - Enable HD Audio SoundWire#1 Link - Enable/disable HD Audio SNDW1 link. Muxed with HDA. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw1; - -/** Offset 0x0366 - Enable HD Audio SoundWire#2 Link - Enable/disable HD Audio SNDW2 link. Muxed with SSP1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw2; - -/** Offset 0x0367 - Enable HD Audio SoundWire#3 Link - Enable/disable HD Audio SNDW3 link. Muxed with DMIC1. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw3; - -/** Offset 0x0368 - Enable HD Audio SoundWire#4 Link - Enable/disable HD Audio SNDW4 link. Muxed with DMIC0. - $EN_DIS -**/ - UINT8 PchHdaAudioLinkSndw4; - -/** Offset 0x0369 - CNVi Configuration - This option allows for automatic detection of Connectivity Solution. [Auto Detection] - assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi. - 0:Disable, 1:Auto -**/ - UINT8 CnviMode; - -/** Offset 0x036A - CNVi BT Core - Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtCore; - -/** Offset 0x036B - CNVi BT Audio Offload - Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE - $EN_DIS -**/ - UINT8 CnviBtAudioOffload; - -/** Offset 0x036C - CNVi RF_RESET pin muxing - Select CNVi RF_RESET# pin depending on board routing. ICP-LP: GPP_A8 = 0x2640E408(default) - or GPP_F4 = 0x1645E404. ICP-H: 0. ICP-N: GPP_H12 = 0x2746E40C(default) or GPP_H1 - = 0x3746E401. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h. -**/ - UINT32 CnviRfResetPinMux; - -/** Offset 0x0370 - CNVi CLKREQ pin muxing - Select CNVi CLKREQ pin depending on board routing. ICP-LP: GPP_A9 = 0x2640E609(default) - or GPP_F5 = 0x2645E605. ICP-H: 0. ICP-N: GPP_H13 = 0x2746E60D(default) or GPP_H2 - = 0x3746E602. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in GpioPins*.h. -**/ - UINT32 CnviClkreqPinMux; - -/** Offset 0x0374 - Espi Lgmr Memory Range decode - This option enables or disables espi lgmr - $EN_DIS -**/ - UINT8 PchEspiLgmrEnable; - -/** Offset 0x0375 - PCH eSPI Master and Slave BME enabled - PCH eSPI Master and Slave BME enabled - $EN_DIS -**/ - UINT8 PchEspiBmeMasterSlaveEnabled; - -/** Offset 0x0376 - Enable Host C10 reporting through eSPI - Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire. - $EN_DIS -**/ - UINT8 PchEspiHostC10ReportEnable; - -/** Offset 0x0377 - Enable SdCard Controller - Enable/disable SD Card Controller. - $EN_DIS -**/ - UINT8 ScsSdCardEnabled; - -/** Offset 0x0378 - SdCard power enable polarity - Choose SD_PWREN# polarity - 0: Active low, 1: Active high -**/ - UINT8 SdCardPowerEnableActiveHigh; - -/** Offset 0x0379 - Use tuned DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 SdCardUseCustomDlls; - -/** Offset 0x037A -**/ - UINT8 UnusedUpdSpace14[2]; - -/** Offset 0x037C - SdCard Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 SdCardTxCmdDelayRegValue; - -/** Offset 0x0380 - SdCard Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 SdCardTxDataDelay1RegValue; - -/** Offset 0x0384 - SdCard Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 SdCardTxDataDelay2RegValue; - -/** Offset 0x0388 - SdCard Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay1RegValue; - -/** Offset 0x038C - SdCard Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 SdCardRxCmdDataDelay2RegValue; - -/** Offset 0x0390 - Enable eMMC Controller - Enable/disable eMMC Controller. - $EN_DIS -**/ - UINT8 ScsEmmcEnabled; - -/** Offset 0x0391 - Enable eMMC HS400 Mode - Enable eMMC HS400 Mode. - $EN_DIS -**/ - UINT8 ScsEmmcHs400Enabled; - -/** Offset 0x0392 - Use DLL values from policy - Set if FSP should use HS400 DLL values from policy - $EN_DIS -**/ - UINT8 EmmcUseCustomDlls; - -/** Offset 0x0393 -**/ - UINT8 UnusedUpdSpace15; - -/** Offset 0x0394 - Emmc Tx CMD Delay control register value - Please see Tx CMD Delay Control register definition for help -**/ - UINT32 EmmcTxCmdDelayRegValue; - -/** Offset 0x0398 - Emmc Tx DATA Delay control 1 register value - Please see Tx DATA Delay control 1 register definition for help -**/ - UINT32 EmmcTxDataDelay1RegValue; - -/** Offset 0x039C - Emmc Tx DATA Delay control 2 register value - Please see Tx DATA Delay control 2 register definition for help -**/ - UINT32 EmmcTxDataDelay2RegValue; - -/** Offset 0x03A0 - Emmc Rx CMD + DATA Delay control 1 register value - Please see Rx CMD + DATA Delay control 1 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay1RegValue; - -/** Offset 0x03A4 - Emmc Rx CMD + DATA Delay control 2 register value - Please see Rx CMD + DATA Delay control 2 register definition for help -**/ - UINT32 EmmcRxCmdDataDelay2RegValue; - -/** Offset 0x03A8 - Emmc Rx Strobe Delay control register value - Please see Rx Strobe Delay control register definition for help -**/ - UINT32 EmmcRxStrobeDelayRegValue; - -/** Offset 0x03AC - UFS enable/disable - Please see Rx Strobe Delay control register definition for help - $EN_DIS -**/ - UINT8 UfsEnable[2]; - -/** Offset 0x03AE - Enable PCH ISH SPI GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshSpiGpioAssign; - -/** Offset 0x03AF - Enable PCH ISH UART0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart0GpioAssign; - -/** Offset 0x03B0 - Enable PCH ISH UART1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshUart1GpioAssign; - -/** Offset 0x03B1 - Enable PCH ISH I2C0 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c0GpioAssign; - -/** Offset 0x03B2 - Enable PCH ISH I2C1 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c1GpioAssign; - -/** Offset 0x03B3 - Enable PCH ISH I2C2 GPIO pins assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshI2c2GpioAssign; - -/** Offset 0x03B4 - Enable PCH ISH GP_0 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp0GpioAssign; - -/** Offset 0x03B5 - Enable PCH ISH GP_1 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp1GpioAssign; - -/** Offset 0x03B6 - Enable PCH ISH GP_2 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp2GpioAssign; - -/** Offset 0x03B7 - Enable PCH ISH GP_3 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp3GpioAssign; - -/** Offset 0x03B8 - Enable PCH ISH GP_4 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp4GpioAssign; - -/** Offset 0x03B9 - Enable PCH ISH GP_5 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp5GpioAssign; - -/** Offset 0x03BA - Enable PCH ISH GP_6 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp6GpioAssign; - -/** Offset 0x03BB - Enable PCH ISH GP_7 GPIO pin assigned - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIshGp7GpioAssign; - -/** Offset 0x03BC - PCH ISH PDT Unlock Msg - 0: False; 1: True. - $EN_DIS -**/ - UINT8 PchIshPdtUnlock; - -/** Offset 0x03BD - Enable SATA - Enable/disable SATA controller. - $EN_DIS -**/ - UINT8 SataEnable; - -/** Offset 0x03BE - PCH Sata Test Mode - Allow entrance to the PCH SATA test modes. - $EN_DIS -**/ - UINT8 SataTestMode; - -/** Offset 0x03BF - Enable SATA SALP Support - Enable/disable SATA Aggressive Link Power Management. - $EN_DIS -**/ - UINT8 SataSalpSupport; - -/** Offset 0x03C0 - PCH Sata Pwr Opt Enable - SATA Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 SataPwrOptEnable; - -/** Offset 0x03C1 - PCH Sata eSATA Speed Limit - When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. - $EN_DIS -**/ - UINT8 EsataSpeedLimit; - -/** Offset 0x03C2 - SATA LED - SATA LED indicating SATA controller activity. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 SataLedEnable; - -/** Offset 0x03C3 - SATA Mode - Select SATA controller working mode. - 0:AHCI, 1:RAID -**/ - UINT8 SataMode; - -/** Offset 0x03C4 - PCH Sata Speed Limit - Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault. -**/ - UINT8 SataSpeedLimit; - -/** Offset 0x03C5 - Enable SATA ports - Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, - and so on. -**/ - UINT8 SataPortsEnable[8]; - -/** Offset 0x03CD - Enable SATA Port HotPlug - Enable SATA Port HotPlug. -**/ - UINT8 SataPortsHotPlug[8]; - -/** Offset 0x03D5 - Enable SATA Port Interlock Sw - Enable SATA Port Interlock Sw. -**/ - UINT8 SataPortsInterlockSw[8]; - -/** Offset 0x03DD - Enable SATA Port External - Enable SATA Port External. -**/ - UINT8 SataPortsExternal[8]; - -/** Offset 0x03E5 - Enable SATA Port SpinUp - Enable the COMRESET initialization Sequence to the device. -**/ - UINT8 SataPortsSpinUp[8]; - -/** Offset 0x03ED - Enable SATA Port Solid State Drive - 0: HDD; 1: SSD. -**/ - UINT8 SataPortsSolidStateDrive[8]; - -/** Offset 0x03F5 - Enable SATA DEVSLP Feature - Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each - port, byte0 for port0, byte1 for port1, and so on. -**/ - UINT8 SataPortsDevSlp[8]; - -/** Offset 0x03FD - Enable SATA Port Enable Dito Config - Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). -**/ - UINT8 SataPortsEnableDitoConfig[8]; - -/** Offset 0x0405 - Enable SATA Port DmVal - DITO multiplier. Default is 15. -**/ - UINT8 SataPortsDmVal[8]; - -/** Offset 0x040D -**/ - UINT8 UnusedUpdSpace16[1]; - -/** Offset 0x040E - Enable SATA Port DmVal - DEVSLP Idle Timeout (DITO), Default is 625. -**/ - UINT16 SataPortsDitoVal[8]; - -/** Offset 0x041E - Enable SATA Port ZpOdd - Support zero power ODD. -**/ - UINT8 SataPortsZpOdd[8]; - -/** Offset 0x0426 - PCH Sata Rst Raid Alternate Id - Enable RAID Alternate ID. - $EN_DIS -**/ - UINT8 SataRstRaidDeviceId; - -/** Offset 0x0427 - PCH Sata Rst Raid0 - RAID0. - $EN_DIS -**/ - UINT8 SataRstRaid0; - -/** Offset 0x0428 - PCH Sata Rst Raid1 - RAID1. - $EN_DIS -**/ - UINT8 SataRstRaid1; - -/** Offset 0x0429 - PCH Sata Rst Raid10 - RAID10. - $EN_DIS -**/ - UINT8 SataRstRaid10; - -/** Offset 0x042A - PCH Sata Rst Raid5 - RAID5. - $EN_DIS -**/ - UINT8 SataRstRaid5; - -/** Offset 0x042B - PCH Sata Rst Irrt - Intel Rapid Recovery Technology. - $EN_DIS -**/ - UINT8 SataRstIrrt; - -/** Offset 0x042C - PCH Sata Rst Orom Ui Banner - OROM UI and BANNER. - $EN_DIS -**/ - UINT8 SataRstOromUiBanner; - -/** Offset 0x042D - PCH Sata Rst Orom Ui Delay - 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY). -**/ - UINT8 SataRstOromUiDelay; - -/** Offset 0x042E - PCH Sata Rst Hdd Unlock - Indicates that the HDD password unlock in the OS is enabled. - $EN_DIS -**/ - UINT8 SataRstHddUnlock; - -/** Offset 0x042F - PCH Sata Rst Led Locate - Indicates that the LED/SGPIO hardware is attached and ping to locate feature is - enabled on the OS. - $EN_DIS -**/ - UINT8 SataRstLedLocate; - -/** Offset 0x0430 - PCH Sata Rst Irrt Only - Allow only IRRT drives to span internal and external ports. - $EN_DIS -**/ - UINT8 SataRstIrrtOnly; - -/** Offset 0x0431 - PCH Sata Rst Smart Storage - RST Smart Storage caching Bit. - $EN_DIS -**/ - UINT8 SataRstSmartStorage; - -/** Offset 0x0432 - SATA RST Interrupt Mode - Allowes to choose which interrupts will be implemented by SATA controller in RAID mode. - 0:Msix, 1:Msi, 2:Legacy -**/ - UINT8 SataRstInterrupt; - -/** Offset 0x0433 - PCH Sata Rst Optane Memory - Optane Memory - $EN_DIS -**/ - UINT8 SataRstOptaneMemory; - -/** Offset 0x0434 - PCH SATA use RST Legacy OROM - Use PCH SATA RST Legacy OROM when CSM is Enabled - $EN_DIS -**/ - UINT8 SataRstLegacyOrom; - -/** Offset 0x0435 - PCH Sata Rst CPU Attached Storage - CPU Attached Storage - $EN_DIS -**/ - UINT8 SataRstCpuAttachedStorage; - -/** Offset 0x0436 - PCH Sata Rst Pcie Storage Remap enable - Enable Intel RST for PCIe Storage remapping. -**/ - UINT8 SataRstPcieEnable[3]; - -/** Offset 0x0439 - PCH Sata Rst Pcie Storage Port - Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect). -**/ - UINT8 SataRstPcieStoragePort[3]; - -/** Offset 0x043C - PCH Sata Rst Pcie Device Reset Delay - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms -**/ - UINT8 SataRstPcieDeviceResetDelay[3]; - -/** Offset 0x043F - Port 0 T1 Multipler - Port 0 T1 Multipler. -**/ - UINT8 SataP0T1M; - -/** Offset 0x0440 - Port 0 T2 Multipler - Port 0 T2 Multipler. -**/ - UINT8 SataP0T2M; - -/** Offset 0x0441 - Port 0 T3 Multipler - Port 0 T3 Multipler. -**/ - UINT8 SataP0T3M; - -/** Offset 0x0442 - Port 0 Tdispatch - Port 0 Tdispatch. -**/ - UINT8 SataP0TDisp; - -/** Offset 0x0443 - Port 1 T1 Multipler - Port 1 T1 Multipler. -**/ - UINT8 SataP1T1M; - -/** Offset 0x0444 - Port 1 T2 Multipler - Port 1 T2 Multipler. -**/ - UINT8 SataP1T2M; - -/** Offset 0x0445 - Port 1 T3 Multipler - Port 1 T3 Multipler. -**/ - UINT8 SataP1T3M; - -/** Offset 0x0446 - Port 1 Tdispatch - Port 1 Tdispatch. -**/ - UINT8 SataP1TDisp; - -/** Offset 0x0447 - Port 0 Tinactive - Port 0 Tinactive. -**/ - UINT8 SataP0Tinact; - -/** Offset 0x0448 - Port 0 Alternate Fast Init Tdispatch - Port 0 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP0TDispFinit; - -/** Offset 0x0449 - Port 1 Tinactive - Port 1 Tinactive. -**/ - UINT8 SataP1Tinact; - -/** Offset 0x044A - Port 1 Alternate Fast Init Tdispatch - Port 1 Alternate Fast Init Tdispatch. - $EN_DIS -**/ - UINT8 SataP1TDispFinit; - -/** Offset 0x044B - Sata Thermal Throttling Suggested Setting - Sata Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 SataThermalSuggestedSetting; - -/** Offset 0x044C - Enable xHCI Compliance Mode - Compliance Mode can be enabled for testing through this option but this is disabled - by default. - $EN_DIS -**/ - UINT8 PchEnableComplianceMode; - -/** Offset 0x044D - USB PDO Programming - Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming - during later phase. 1: enable, 0: disable - $EN_DIS -**/ - UINT8 UsbPdoProgramming; - -/** Offset 0x044E - USB Overcurrent Override for DbC - This option overrides USB Over Current enablement state that USB OC will be disabled - after enabling this option. Enable when DbC is used to avoid signaling conflicts. - $EN_DIS -**/ - UINT8 PchEnableDbcObs; - -/** Offset 0x044F - PCH USB OverCurrent mapping lock enable - If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning - that OC mapping data will be consumed by xHCI and OC mapping registers will be locked. - $EN_DIS -**/ - UINT8 PchXhciOcLock; - -/** Offset 0x0450 - Enable USB2 ports - Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb20Enable[16]; - -/** Offset 0x0460 - USB2 Port Over Current Pin - Describe the specific over current pin number of USB 2.0 Port N. -**/ - UINT8 Usb2OverCurrentPin[16]; - -/** Offset 0x0470 - Enable USB3 ports - Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for - port1, and so on. -**/ - UINT8 PortUsb30Enable[10]; - -/** Offset 0x047A - USB3 Port Over Current Pin - Describe the specific over current pin number of USB 3.0 Port N. -**/ - UINT8 Usb3OverCurrentPin[10]; - -/** Offset 0x0484 - Enable xDCI controller - Enable/disable to xDCI controller. - $EN_DIS -**/ - UINT8 XdciEnable; - -/** Offset 0x0485 - USB Per Port HS Preemphasis Bias - USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port. -**/ - UINT8 Usb2PhyPetxiset[16]; - -/** Offset 0x0495 - USB Per Port HS Transmitter Bias - USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV, - 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port. -**/ - UINT8 Usb2PhyTxiset[16]; - -/** Offset 0x04A5 - USB Per Port HS Transmitter Emphasis - USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON, - 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port. -**/ - UINT8 Usb2PhyPredeemp[16]; - -/** Offset 0x04B5 - USB Per Port Half Bit Pre-emphasis - USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis. - One byte for each port. -**/ - UINT8 Usb2PhyPehalfbit[16]; - -/** Offset 0x04C5 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmphEnable[10]; - -/** Offset 0x04CF - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16], - Default = 29h (approximately -3.5dB De-Emphasis). One byte for each port. -**/ - UINT8 Usb3HsioTxDeEmph[10]; - -/** Offset 0x04D9 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value - in arrary can be between 0-1. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmpEnable[10]; - -/** Offset 0x04E3 - USB 3.0 TX Output Downscale Amplitude Adjustment - USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], Default - = 00h. One byte for each port. -**/ - UINT8 Usb3HsioTxDownscaleAmp[10]; - -/** Offset 0x04ED -**/ - UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10]; - -/** Offset 0x04F7 -**/ - UINT8 PchUsb3HsioFilterSelNEnable[10]; - -/** Offset 0x0501 -**/ - UINT8 PchUsb3HsioFilterSelPEnable[10]; - -/** Offset 0x050B -**/ - UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10]; - -/** Offset 0x0515 -**/ - UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10]; - -/** Offset 0x051F -**/ - UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10]; - -/** Offset 0x0529 -**/ - UINT8 PchUsb3HsioFilterSelN[10]; - -/** Offset 0x0533 -**/ - UINT8 PchUsb3HsioFilterSelP[10]; - -/** Offset 0x053D - Enable PCIE RP HotPlug - Indicate whether the root port is hot plug available. -**/ - UINT8 PcieRpHotPlug[24]; - -/** Offset 0x0555 - Enable PCIE RP Pm Sci - Indicate whether the root port power manager SCI is enabled. -**/ - UINT8 PcieRpPmSci[24]; - -/** Offset 0x056D - Enable PCIE RP Transmitter Half Swing - Indicate whether the Transmitter Half Swing is enabled. -**/ - UINT8 PcieRpTransmitterHalfSwing[24]; - -/** Offset 0x0585 - Enable PCIE RP Clk Req Detect - Probe CLKREQ# signal before enabling CLKREQ# based power management. -**/ - UINT8 PcieRpClkReqDetect[24]; - -/** Offset 0x059D - PCIE RP Advanced Error Report - Indicate whether the Advanced Error Reporting is enabled. -**/ - UINT8 PcieRpAdvancedErrorReporting[24]; - -/** Offset 0x05B5 - PCIE RP Unsupported Request Report - Indicate whether the Unsupported Request Report is enabled. -**/ - UINT8 PcieRpUnsupportedRequestReport[24]; - -/** Offset 0x05CD - PCIE RP Fatal Error Report - Indicate whether the Fatal Error Report is enabled. -**/ - UINT8 PcieRpFatalErrorReport[24]; - -/** Offset 0x05E5 - PCIE RP No Fatal Error Report - Indicate whether the No Fatal Error Report is enabled. -**/ - UINT8 PcieRpNoFatalErrorReport[24]; - -/** Offset 0x05FD - PCIE RP Correctable Error Report - Indicate whether the Correctable Error Report is enabled. -**/ - UINT8 PcieRpCorrectableErrorReport[24]; - -/** Offset 0x0615 - PCIE RP System Error On Fatal Error - Indicate whether the System Error on Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnFatalError[24]; - -/** Offset 0x062D - PCIE RP System Error On Non Fatal Error - Indicate whether the System Error on Non Fatal Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnNonFatalError[24]; - -/** Offset 0x0645 - PCIE RP System Error On Correctable Error - Indicate whether the System Error on Correctable Error is enabled. -**/ - UINT8 PcieRpSystemErrorOnCorrectableError[24]; - -/** Offset 0x065D - PCIE RP Max Payload - Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD. -**/ - UINT8 PcieRpMaxPayload[24]; - -/** Offset 0x0675 -**/ - UINT8 UnusedUpdSpace17[3]; - -/** Offset 0x0678 - DPC for PCIE RP Mask - Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcMask; - -/** Offset 0x067C - DPC Extensions PCIE RP Mask - Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit - for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpDpcExtensionsMask; - -/** Offset 0x0680 - PTM for PCIE RP Mask - Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable. - One bit for each port, bit0 for port1, bit1 for port2, and so on. -**/ - UINT32 PcieRpPtmMask; - -/** Offset 0x0684 - PCIE RP Pcie Speed - Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: - PCH_PCIE_SPEED). -**/ - UINT8 PcieRpPcieSpeed[24]; - -/** Offset 0x069C - PCIE RP Gen3 Equalization Phase Method - PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization; - 1: hardware equalization; 4: Fixed Coeficients. -**/ - UINT8 PcieRpGen3EqPh3Method[24]; - -/** Offset 0x06B4 - PCIE RP Physical Slot Number - Indicates the slot number for the root port. Default is the value as root port index. -**/ - UINT8 PcieRpPhysicalSlotNumber[24]; - -/** Offset 0x06CC - PCH PCIe root port connection type - 0: built-in device, 1:slot -**/ - UINT8 PcieRpSlotImplemented[24]; - -/** Offset 0x06E4 - PCIE RP Completion Timeout - The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default. -**/ - UINT8 PcieRpCompletionTimeout[24]; - -/** Offset 0x06FC - PCIE RP Aspm - The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is - PchPcieAspmAutoConfig. -**/ - UINT8 PcieRpAspm[24]; - -/** Offset 0x0714 - PCIE RP L1 Substates - The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). - Default is PchPcieL1SubstatesL1_1_2. -**/ - UINT8 PcieRpL1Substates[24]; - -/** Offset 0x072C - PCIE RP Ltr Enable - Latency Tolerance Reporting Mechanism. -**/ - UINT8 PcieRpLtrEnable[24]; - -/** Offset 0x0744 - PCIE RP Ltr Config Lock - 0: Disable; 1: Enable. -**/ - UINT8 PcieRpLtrConfigLock[24]; - -/** Offset 0x075C - PCIE RP Access Control Services Extended Capability - Enable/Disable PCIE RP Access Control Services Extended Capability -**/ - UINT8 PcieRpAcsEnabled[24]; - -/** Offset 0x0774 - PCIE RP Clock Power Management - Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal - can still be controlled by L1 PM substates mechanism -**/ - UINT8 PcieRpEnableCpm[24]; - -/** Offset 0x078C - PCIE RP Detect Timeout Ms - The number of milliseconds within 0~65535 in reference code will wait for link to - exit Detect state for enabled ports before assuming there is no device and potentially - disabling the port. -**/ - UINT16 PcieRpDetectTimeoutMs[24]; - -/** Offset 0x07BC - PCIE RP Ltr Max Snoop Latency - Latency Tolerance Reporting, Max Snoop Latency. -**/ - UINT16 PcieRpLtrMaxSnoopLatency[24]; - -/** Offset 0x07EC - PCIE RP Ltr Max No Snoop Latency - Latency Tolerance Reporting, Max Non-Snoop Latency. -**/ - UINT16 PcieRpLtrMaxNoSnoopLatency[24]; - -/** Offset 0x081C - PCIE RP Snoop Latency Override Mode - Latency Tolerance Reporting, Snoop Latency Override Mode. -**/ - UINT8 PcieRpSnoopLatencyOverrideMode[24]; - -/** Offset 0x0834 - PCIE RP Snoop Latency Override Multiplier - Latency Tolerance Reporting, Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x084C - PCIE RP Snoop Latency Override Value - Latency Tolerance Reporting, Snoop Latency Override Value. -**/ - UINT16 PcieRpSnoopLatencyOverrideValue[24]; - -/** Offset 0x087C - PCIE RP Non Snoop Latency Override Mode - Latency Tolerance Reporting, Non-Snoop Latency Override Mode. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMode[24]; - -/** Offset 0x0894 - PCIE RP Non Snoop Latency Override Multiplier - Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier. -**/ - UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24]; - -/** Offset 0x08AC - PCIE RP Non Snoop Latency Override Value - Latency Tolerance Reporting, Non-Snoop Latency Override Value. -**/ - UINT16 PcieRpNonSnoopLatencyOverrideValue[24]; - -/** Offset 0x08DC - PCIE RP Slot Power Limit Scale - Specifies scale used for slot power limit value. Leave as 0 to set to default. -**/ - UINT8 PcieRpSlotPowerLimitScale[24]; - -/** Offset 0x08F4 - PCIE RP Slot Power Limit Value - Specifies upper limit on power supplie by slot. Leave as 0 to set to default. -**/ - UINT16 PcieRpSlotPowerLimitValue[24]; - -/** Offset 0x0924 - PCIE RP Upstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 5. -**/ - UINT8 PcieRpUptp[24]; - -/** Offset 0x093C - PCIE RP Downstream Port Transmiter Preset - Used during Gen3 Link Equalization. Used for all lanes. Default is 7. -**/ - UINT8 PcieRpDptp[24]; - -/** Offset 0x0954 - Usage type for ClkSrc - 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use - (free running), 0xFF: not used -**/ - UINT8 PcieClkSrcUsage[16]; - -/** Offset 0x0964 - ClkReq-to-ClkSrc mapping - Number of ClkReq signal assigned to ClkSrc -**/ - UINT8 PcieClkSrcClkReq[16]; - -/** Offset 0x0974 - PCIE Eq Ph3 Lane Param Cm - PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1. -**/ - UINT8 PcieEqPh3LaneParamCm[24]; - -/** Offset 0x098C - PCIE Eq Ph3 Lane Param Cp - PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1. -**/ - UINT8 PcieEqPh3LaneParamCp[24]; - -/** Offset 0x09A4 - PCIE Sw Eq CoeffList Cm - PCH_PCIE_EQ_PARAM. Coefficient C-1. -**/ - UINT8 PcieSwEqCoeffListCm[5]; - -/** Offset 0x09A9 - PCIE Sw Eq CoeffList Cp - PCH_PCIE_EQ_PARAM. Coefficient C+1. -**/ - UINT8 PcieSwEqCoeffListCp[5]; - -/** Offset 0x09AE - PCIE RP Enable Port8xh Decode - This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable; - 1: Enable. - $EN_DIS -**/ - UINT8 PcieEnablePort8xhDecode; - -/** Offset 0x09AF - PCIE Port8xh Decode Port Index - The Index of PCIe Port that is selected for Port8xh Decode (0 Based). -**/ - UINT8 PchPciePort8xhDecodePortIndex; - -/** Offset 0x09B0 - PCIE Enable Peer Memory Write - This member describes whether Peer Memory Writes are enabled on the platform. - $EN_DIS -**/ - UINT8 PcieEnablePeerMemoryWrite; - -/** Offset 0x09B1 - PCIE Compliance Test Mode - Compliance Test Mode shall be enabled when using Compliance Load Board. - $EN_DIS -**/ - UINT8 PcieComplianceTestMode; - -/** Offset 0x09B2 - PCIE Rp Function Swap - Allows BIOS to use root port function number swapping when root port of function - 0 is disabled. - $EN_DIS -**/ - UINT8 PcieRpFunctionSwap; - -/** Offset 0x09B3 - Number of DevIntConfig Entry - Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr - must not be NULL. -**/ - UINT8 NumOfDevIntConfig; - -/** Offset 0x09B4 - Address of PCH_DEVICE_INTERRUPT_CONFIG table. - The address of the table of PCH_DEVICE_INTERRUPT_CONFIG. -**/ - UINT32 DevIntConfigPtr; - -/** Offset 0x09B8 - PIRQx to IRQx Map Config - PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for - PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy - 8259 PCI mode. -**/ - UINT8 PxRcConfig[8]; - -/** Offset 0x09C0 - Select GPIO IRQ Route - GPIO IRQ Select. The valid value is 14 or 15. -**/ - UINT8 GpioIrqRoute; - -/** Offset 0x09C1 - Select SciIrqSelect - SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only. -**/ - UINT8 SciIrqSelect; - -/** Offset 0x09C2 - Select TcoIrqSelect - TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23. -**/ - UINT8 TcoIrqSelect; - -/** Offset 0x09C3 - Enable/Disable Tco IRQ - Enable/disable TCO IRQ - $EN_DIS -**/ - UINT8 TcoIrqEnable; - -/** Offset 0x09C4 - Enable LOCKDOWN SMI - Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. - $EN_DIS -**/ - UINT8 PchLockDownGlobalSmi; - -/** Offset 0x09C5 - Enable LOCKDOWN BIOS Interface - Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. - $EN_DIS -**/ - UINT8 PchLockDownBiosInterface; - -/** Offset 0x09C6 - Enable LOCKDOWN BIOS LOCK - Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region - protection. - $EN_DIS -**/ - UINT8 PchLockDownBiosLock; - -/** Offset 0x09C7 - RTC CMOS MEMORY LOCK - Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper - and and lower 128-byte bank of RTC RAM. - $EN_DIS -**/ - UINT8 PchLockDownRtcMemoryLock; - -/** Offset 0x09C8 - Unlock all GPIO pads - Force all GPIO pads to be unlocked for debug purpose. - $EN_DIS -**/ - UINT8 PchUnlockGpioPads; - -/** Offset 0x09C9 - Enable Power Optimizer - Enable DMI Power Optimizer on PCH side. - $EN_DIS -**/ - UINT8 PchPwrOptEnable; - -/** Offset 0x09CA - Pch Dmi Aspm Ctrl - ASPM configuration on the PCH side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig - 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto -**/ - UINT8 PchDmiAspmCtrl; - -/** Offset 0x09CB - PCH Flash Protection Ranges Write Enble - Write or erase is blocked by hardware. -**/ - UINT8 PchWriteProtectionEnable[5]; - -/** Offset 0x09D0 - PCH Flash Protection Ranges Read Enble - Read is blocked by hardware. -**/ - UINT8 PchReadProtectionEnable[5]; - -/** Offset 0x09D5 -**/ - UINT8 UnusedUpdSpace18[1]; - -/** Offset 0x09D6 - PCH Protect Range Limit - Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for - limit comparison. -**/ - UINT16 PchProtectedRangeLimit[5]; - -/** Offset 0x09E0 - PCH Protect Range Base - Left shifted address by 12 bits with address bits 11:0 are assumed to be 0. -**/ - UINT16 PchProtectedRangeBase[5]; - -/** Offset 0x09EA - Enable PCH Io Apic Entry 24-119 - 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PchIoApicEntry24_119; - -/** Offset 0x09EB - Enable 8254 Static Clock Gating - Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time - might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support - legacy OS using 8254 timer. Also enable this while S0ix is enabled. - $EN_DIS -**/ - UINT8 Enable8254ClockGating; - -/** Offset 0x09EC - Enable 8254 Static Clock Gating On S3 - This is only applicable when Enable8254ClockGating is disabled. FSP will do the - 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This - avoids the SMI requirement for the programming. - $EN_DIS -**/ - UINT8 Enable8254ClockGatingOnS3; - -/** Offset 0x09ED - PCH Io Apic ID - This member determines IOAPIC ID. Default is 0x02. -**/ - UINT8 PchIoApicId; - -/** Offset 0x09EE - PCH Unlock SideBand access - The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before - 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access. - $EN_DIS -**/ - UINT8 PchSbAccessUnlock; - -/** Offset 0x09EF - PCH Compatibility Revision ID - This member describes whether or not the CRID feature of PCH should be enabled. - $EN_DIS -**/ - UINT8 PchCrid; - -/** Offset 0x09F0 - PCH Pm PME_B0_S5_DIS - When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1. - $EN_DIS -**/ - UINT8 PchPmPmeB0S5Dis; - -/** Offset 0x09F1 - PCH Pm Wol Enable Override - Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register. - $EN_DIS -**/ - UINT8 PchPmWolEnableOverride; - -/** Offset 0x09F2 - PCH Pm Pcie Wake From DeepSx - Determine if enable PCIe to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmPcieWakeFromDeepSx; - -/** Offset 0x09F3 - PCH Pm WoW lan Enable - Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanEnable; - -/** Offset 0x09F4 - PCH Pm WoW lan DeepSx Enable - Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the - PWRM_CFG3 register. - $EN_DIS -**/ - UINT8 PchPmWoWlanDeepSxEnable; - -/** Offset 0x09F5 - PCH Pm Lan Wake From DeepSx - Determine if enable LAN to wake from deep Sx. - $EN_DIS -**/ - UINT8 PchPmLanWakeFromDeepSx; - -/** Offset 0x09F6 - PCH Pm Deep Sx Pol - Deep Sx Policy. - $EN_DIS -**/ - UINT8 PchPmDeepSxPol; - -/** Offset 0x09F7 - PCH Pm Slp S3 Min Assert - SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms. -**/ - UINT8 PchPmSlpS3MinAssert; - -/** Offset 0x09F8 - PCH Pm Slp S4 Min Assert - SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s. -**/ - UINT8 PchPmSlpS4MinAssert; - -/** Offset 0x09F9 - PCH Pm Slp Sus Min Assert - SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s. -**/ - UINT8 PchPmSlpSusMinAssert; - -/** Offset 0x09FA - PCH Pm Slp A Min Assert - SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s. -**/ - UINT8 PchPmSlpAMinAssert; - -/** Offset 0x09FB - PCH Pm Slp Strch Sus Up - Enable SLP_X Stretching After SUS Well Power Up. - $EN_DIS -**/ - UINT8 PchPmSlpStrchSusUp; - -/** Offset 0x09FC - PCH Pm Slp Lan Low Dc - Enable/Disable SLP_LAN# Low on DC Power. - $EN_DIS -**/ - UINT8 PchPmSlpLanLowDc; - -/** Offset 0x09FD - PCH Pm Pwr Btn Override Period - PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s. -**/ - UINT8 PchPmPwrBtnOverridePeriod; - -/** Offset 0x09FE - PCH Energy Reporting - Disable/Enable PCH to CPU energy report feature. - $EN_DIS -**/ - UINT8 PchPmDisableEnergyReport; - -/** Offset 0x09FF - PCH Pm Disable Dsx Ac Present Pulldown - When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit. - $EN_DIS -**/ - UINT8 PchPmDisableDsxAcPresentPulldown; - -/** Offset 0x0A00 - PCH Pm Disable Native Power Button - Power button native mode disable. - $EN_DIS -**/ - UINT8 PchPmDisableNativePowerButton; - -/** Offset 0x0A01 -**/ - UINT8 UnusedUpdSpace19[3]; - -/** Offset 0x0A04 - Power button debounce configuration - Debounce time for PWRBTN in microseconds. For values not supported by HW, they will - be rounded down to closest supported on. 0: disable, 250-1024000us: supported range -**/ - UINT32 PmcPowerButtonDebounceTime; - -/** Offset 0x0A08 - Disable Power Button debounce in PMC module - Disable Power Button debounce for PWRBTN in PMC module. '0': The 16ms debounce period - applies to all usages of the PWRBTN# pin (legacy behavior). '1': When a falling - edge occurs on the PWRBTN# pin, an interrupt is generated and the 16ms debounce - timer starts. Subsequent interrupts are masked while the debounce timer is running. -**/ - UINT8 PmcDisablePowerButtonDebounce; - -/** Offset 0x0A09 - PCH Pm Slp S0 Enable - Indicates whether SLP_S0# is to be asserted when PCH reaches idle state. - $EN_DIS -**/ - UINT8 PchPmSlpS0Enable; - -/** Offset 0x0A0A - PCH Pm ME_WAKE_STS - Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmMeWakeSts; - -/** Offset 0x0A0B - PCH Pm WOL_OVR_WK_STS - Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. - $EN_DIS -**/ - UINT8 PchPmWolOvrWkSts; - -/** Offset 0x0A0C - Enable TCO timer. - When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have - huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer - emulation must be enabled, and WDAT table must not be exposed to the OS. - $EN_DIS -**/ - UINT8 EnableTcoTimer; - -/** Offset 0x0A0D - VRAlert# Pin - When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling - to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchPmVrAlert; - -/** Offset 0x0A0E - PCH Pm Reset Power Cycle Duration - Could be customized in the unit of second. Please refer to EDS for all support settings. - 0 is default, 1 is 1 second, 2 is 2 seconds, ... -**/ - UINT8 PchPmPwrCycDur; - -/** Offset 0x0A0F - PCH Pm Pcie Pll Ssc - Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No - BIOS override. -**/ - UINT8 PchPmPciePllSsc; - -/** Offset 0x0A10 - S0i3 support - S0i3 platform support. When enabled ASL code is used to determine if platform can - go to S0i2 or S0i3 state. 0:Disable(S0i2 only), 1:Enable (Runtime in ASL) - $EN_DIS -**/ - UINT8 PchPmS0i3Support; - -/** Offset 0x0A11 - SLP_S0# Override - DEPRECATED - 0:Disabled, 1:Enabled -**/ - UINT8 SlpS0Override; - -/** Offset 0x0A12 - S0ix Override Settings - DEPRECATED - 0:No Change, 1:DCI OOB, 2:USB2 DbC -**/ - UINT8 SlpS0DisQForDebug; - -/** Offset 0x0A13 - PMC Debug Message Enable - When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW - will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix - $EN_DIS -**/ - UINT8 PmcDbgMsgEn; - -/** Offset 0x0A14 - Pointer of ChipsetInit format v2 Binary - ChipsetInit Binary format v2 Pointer. -**/ - UINT32 ChipsetInitBinPtr; - -/** Offset 0x0A18 - Length of ChipsetInit format v2 Binary - ChipsetInit Binary format v2 Length. -**/ - UINT32 ChipsetInitBinLen; - -/** Offset 0x0A1C - Enable PS_ON. - PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power - target that will be required by the California Energy Commission (CEC). When FALSE, - PS_ON is to be disabled. - $EN_DIS -**/ - UINT8 PsOnEnable; - -/** Offset 0x0A1D - Pmc Cpu C10 Gate Pin Enable - Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO - and VccSTG rails instead of SLP_S0# pin. - $EN_DIS -**/ - UINT8 PmcCpuC10GatePinEnable; - -/** Offset 0x0A1E - ModPHY SUS Power Domain Dynamic Gating - Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on - PCH-H. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PmcModPhySusPgEnable; - -/** Offset 0x0A1F - PCH USB2 PHY Power Gating enable - 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY - Sus Well PG - $EN_DIS -**/ - UINT8 PmcUsb2PhySusPgEnable; - -/** Offset 0x0A20 - OS IDLE Mode Enable - Enable/Disable OS Idle Mode (PCH-N and PCH-H only) - $EN_DIS -**/ - UINT8 PmcOsIdleEnable; - -/** Offset 0x0A21 - Enable PMC CrashLog - Enable or Disable PMC CrashLog; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 PmcCrashLogEnable; - -/** Offset 0x0A22 - Enable CPPM Forced Alignment - Enable or Disable CPPM Forced Alignment; 0: Disable; 1: Enable. - $EN_DIS -**/ - UINT8 ForcedAlignmentEnable; - -/** Offset 0x0A23 - PCHHOT# pin - Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable - $EN_DIS -**/ - UINT8 PchHotEnable; - -/** Offset 0x0A24 - Thermal Throttling Custimized T0Level Value - Custimized T0Level value. -**/ - UINT16 PchT0Level; - -/** Offset 0x0A26 - Thermal Throttling Custimized T1Level Value - Custimized T1Level value. -**/ - UINT16 PchT1Level; - -/** Offset 0x0A28 - Thermal Throttling Custimized T2Level Value - Custimized T2Level value. -**/ - UINT16 PchT2Level; - -/** Offset 0x0A2A - Enable The Thermal Throttle - Enable the thermal throttle function. - $EN_DIS -**/ - UINT8 PchTTEnable; - -/** Offset 0x0A2B - PMSync State 13 - When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force - at least T2 state. - $EN_DIS -**/ - UINT8 PchTTState13Enable; - -/** Offset 0x0A2C - Thermal Throttle Lock - Thermal Throttle Lock. - $EN_DIS -**/ - UINT8 PchTTLock; - -/** Offset 0x0A2D - Thermal Throttling Suggested Setting - Thermal Throttling Suggested Setting. - $EN_DIS -**/ - UINT8 TTSuggestedSetting; - -/** Offset 0x0A2E - Enable PCH Cross Throttling - Enable/Disable PCH Cross Throttling - $EN_DIS -**/ - UINT8 TTCrossThrottling; - -/** Offset 0x0A2F - DMI Thermal Sensor Autonomous Width Enable - DMI Thermal Sensor Autonomous Width Enable. - $EN_DIS -**/ - UINT8 PchDmiTsawEn; - -/** Offset 0x0A30 - DMI Thermal Sensor Suggested Setting - DMT thermal sensor suggested representative values. - $EN_DIS -**/ - UINT8 DmiSuggestedSetting; - -/** Offset 0x0A31 - Thermal Sensor 0 Target Width - Thermal Sensor 0 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS0TW; - -/** Offset 0x0A32 - Thermal Sensor 1 Target Width - Thermal Sensor 1 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS1TW; - -/** Offset 0x0A33 - Thermal Sensor 2 Target Width - Thermal Sensor 2 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS2TW; - -/** Offset 0x0A34 - Thermal Sensor 3 Target Width - Thermal Sensor 3 Target Width. - 0:x1, 1:x2, 2:x4, 3:x8, 4:x16 -**/ - UINT8 DmiTS3TW; - -/** Offset 0x0A35 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. - $EN_DIS -**/ - UINT8 PchMemoryThrottlingEnable; - -/** Offset 0x0A36 - Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPmsyncEnable[2]; - -/** Offset 0x0A38 - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryC0TransmitEnable[2]; - -/** Offset 0x0A3A - Enable Memory Thermal Throttling - Enable Memory Thermal Throttling. -**/ - UINT8 PchMemoryPinSelection[2]; - -/** Offset 0x0A3C - Thermal Device Temperature - Decides the temperature. -**/ - UINT16 PchTemperatureHotLevel; - -/** Offset 0x0A3E - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states - Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtV1p05RailEnabledStates; - -/** Offset 0x0A3F -**/ - UINT8 UnusedUpdSpace20; - -/** Offset 0x0A40 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states - Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtV1p05RailVoltage; - -/** Offset 0x0A42 - External V1P05 Icc Max Value - Granularity of this setting is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtV1p05RailIccMax; - -/** Offset 0x0A43 - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states - Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtVnnRailEnabledStates; - -/** Offset 0x0A44 - External Vnn Voltage Value that will be used in S0ix/Sx states - Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtVnnRailVoltage; - -/** Offset 0x0A46 - External Vnn Icc Max Value that will be used in S0ix/Sx states - Granularity of this setting is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtVnnRailIccMax; - -/** Offset 0x0A47 - Mask to enable the usage of external Vnn VR rail in Sx states - Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in - Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5 -**/ - UINT8 PchFivrExtVnnRailSxEnabledStates; - -/** Offset 0x0A48 - External Vnn Voltage Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments - (0=0mV, 1=2.5mV, 2=5mV...) -**/ - UINT16 PchFivrExtVnnRailSxVoltage; - -/** Offset 0x0A4A - External Vnn Icc Max Value that will be used in Sx states - Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting - is 1mA and maximal possible value is 200mA -**/ - UINT8 PchFivrExtVnnRailSxIccMax; - -/** Offset 0x0A4B - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to low current mode voltage,for PCH-LP ICL U/Y board with D0 stepping need to program - it to 12us -**/ - UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime; - -/** Offset 0x0A4C - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to retention mode voltage. -**/ - UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime; - -/** Offset 0x0A4D - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage - This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX - to retention mode voltage. -**/ - UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime; - -/** Offset 0x0A4E - Transition time in microseconds from Off (0V) to High Current Mode Voltage - This field has 1us resolution. When value is 0 Transition to 0V is disabled,for - PCH-LP ICL U/Y board with D0 stepping need to program it to 120us -**/ - UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime; - -/** Offset 0x0A50 - FIVR Dynamic Power Management - Enable/Disable FIVR Dynamic Power Management. - $EN_DIS -**/ - UINT8 PchFivrDynPm; - -/** Offset 0x0A51 - Serial IO UART DBG2 table - Enable or disable Serial Io UART DBG2 table, default is Disable; 0: Disable; - 1: Enable. -**/ - UINT8 SerialIoUartDbg2[3]; - -/** Offset 0x0A54 - Trace Hub Memory Base - If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate - trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub - memory is configured properly. -**/ - UINT32 TraceHubMemBase; - -/** Offset 0x0A58 - ITSS IRQ Polarity. - Configuration for ITSS IPC[0-3] registers. -**/ - UINT32 ItssIrqPolarity[4]; - -/** Offset 0x0A68 - PCH PMC Energy Report Debug mode - Disable/Enable Energy Reporting Debug Mode. - $EN_DIS -**/ - UINT8 PchPmEnergyReportDebugMode; - -/** Offset 0x0A69 -**/ - UINT8 UnusedUpdSpace21[4]; - -/** Offset 0x0A6D -**/ - UINT8 ReservedFspsUpd[11]; -} FSP_S_CONFIG; - -/** Fsp S UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSP_S_CONFIG FspsConfig; - -/** Offset 0x0A78 -**/ - UINT8 UnusedUpdSpace22[6]; - -/** Offset 0x0A7E -**/ - UINT16 UpdTerminator; -} FSPS_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h deleted file mode 100644 index 022acafd6f..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/FsptUpd.h +++ /dev/null @@ -1,74 +0,0 @@ -/** @file - -Copyright (c) 2018, Intel Corporation. All rights reserved.
- -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. - - This file is automatically generated. Please do NOT modify !!! - -**/ - -#ifndef __FSPTUPD_H__ -#define __FSPTUPD_H__ - -#include - -#pragma pack(1) - - -/** Fsp T Core UPD -**/ -typedef struct { -} FSPT_CORE_UPD; - -/** Fsp T Configuration -**/ -typedef struct { -} FSP_T_CONFIG; - -/** Fsp T UPD Configuration -**/ -typedef struct { - -/** Offset 0x0000 -**/ - FSP_UPD_HEADER FspUpdHeader; - -/** Offset 0x0020 -**/ - FSPT_CORE_UPD FsptCoreUpd; - -/** Offset 0x0040 -**/ - FSP_T_CONFIG FsptConfig; - -/** Offset 0x0080 -**/ - UINT16 UpdTerminator; -} FSPT_UPD; - -#pragma pack() - -#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h deleted file mode 100644 index aa711a126a..0000000000 --- a/src/vendorcode/intel/fsp/fsp2_0/icelake/MemInfoHob.h +++ /dev/null @@ -1,280 +0,0 @@ -/** @file - This file contains definitions required for creation of - Memory S3 Save data, Memory Info data and Memory Platform - data hobs. - @copyright - Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
-Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. -* Redistributions in binary form must reproduce the above copyright notice, this - list of conditions and the following disclaimer in the documentation and/or - other materials provided with the distribution. -* Neither the name of Intel Corporation nor the names of its contributors may - be used to endorse or promote products derived from this software without - specific prior written permission. - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF - THE POSSIBILITY OF SUCH DAMAGE. -**/ -#ifndef _MEM_INFO_HOB_H_ -#define _MEM_INFO_HOB_H_ - -#include -#include -#include - -#pragma pack (push, 1) - -extern EFI_GUID gSiMemoryS3DataGuid; -extern EFI_GUID gSiMemoryInfoDataGuid; -extern EFI_GUID gSiMemoryPlatformDataGuid; - -#define MAX_NODE 1 -#define MAX_CH 2 -#define MAX_DIMM 2 - -/// -/// Host reset states from MRC. -/// -#define WARM_BOOT 2 - -#define R_MC_CHNL_RANK_PRESENT 0x7C -#define B_RANK0_PRS BIT0 -#define B_RANK1_PRS BIT1 -#define B_RANK2_PRS BIT4 -#define B_RANK3_PRS BIT5 - -/// -/// Defines taken from MRC so avoid having to include MrcInterface.h -/// - -// -// Matches MAX_SPD_SAVE define in MRC -// -#ifndef MAX_SPD_SAVE -#define MAX_SPD_SAVE 29 -#endif - -// -// MRC version description. -// -typedef struct { - UINT8 Major; ///< Major version number - UINT8 Minor; ///< Minor version number - UINT8 Rev; ///< Revision number - UINT8 Build; ///< Build number -} SiMrcVersion; - -// -// Matches MrcChannelSts enum in MRC -// -#ifndef CHANNEL_NOT_PRESENT -#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. -#endif -#ifndef CHANNEL_DISABLED -#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. -#endif -#ifndef CHANNEL_PRESENT -#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. -#endif - -// -// Matches MrcDimmSts enum in MRC -// -#ifndef DIMM_ENABLED -#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. -#endif -#ifndef DIMM_DISABLED -#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. -#endif -#ifndef DIMM_PRESENT -#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. -#endif -#ifndef DIMM_NOT_PRESENT -#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. -#endif - -// -// Matches MrcBootMode enum in MRC -// -#ifndef bmCold -#define bmCold 0 // Cold boot -#endif -#ifndef bmWarm -#define bmWarm 1 // Warm boot -#endif -#ifndef bmS3 -#define bmS3 2 // S3 resume -#endif -#ifndef bmFast -#define bmFast 3 // Fast boot -#endif - -// -// Matches MrcDdrType enum in MRC -// -#ifndef MRC_DDR_TYPE_DDR4 -#define MRC_DDR_TYPE_DDR4 0 -#endif -#ifndef MRC_DDR_TYPE_DDR3 -#define MRC_DDR_TYPE_DDR3 1 -#endif -#ifndef MRC_DDR_TYPE_LPDDR3 -#define MRC_DDR_TYPE_LPDDR3 2 -#endif -#ifndef CPU_CFL//CNL -#ifndef MRC_DDR_TYPE_LPDDR4 -#define MRC_DDR_TYPE_LPDDR4 3 -#endif -#else//CFL -#ifndef MRC_DDR_TYPE_UNKNOWN -#define MRC_DDR_TYPE_UNKNOWN 3 -#endif -#endif//CPU_CFL-endif - -#define MAX_PROFILE_NUM 4 // number of memory profiles supported -#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported - -// -// DIMM timings -// -typedef struct { - UINT32 tCK; ///< Memory cycle time, in femtoseconds. - UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. - UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. - UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. - UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. - UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. - UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. - UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. - UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. - UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. - UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. - UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. - UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. - UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. - UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. - UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. - UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. - UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. - UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. - UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. -} MRC_CH_TIMING; - -typedef struct { - UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group. - UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups. - UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM). - UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs. -} MRC_TA_TIMING; - -/// -/// Memory SMBIOS & OC Memory Data Hob -/// -typedef struct { - UINT8 Status; ///< See MrcDimmStatus for the definition of this field. - UINT8 DimmId; - UINT32 DimmCapacity; ///< DIMM size in MBytes. - UINT16 MfgId; - UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes - UINT8 RankInDimm; ///< The number of ranks in this DIMM. - UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. - UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. - UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. - UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. -} DIMM_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this channel should be used. - UINT8 ChannelId; - UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. - MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. - DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. -} CHANNEL_INFO; - -typedef struct { - UINT8 Status; ///< Indicates whether this controller should be used. - UINT16 DeviceId; ///< The PCI device id of this memory controller. - UINT8 RevisionId; ///< The PCI revision id of this memory controller. - UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. - CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. - MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings - MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings - MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings - MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings -} CONTROLLER_INFO; - -typedef struct { - UINT8 Revision; - UINT16 DataWidth; ///< Data width, in bits, of this memory device - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 - UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) - UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - UINT8 ErrorCorrectionType; - - SiMrcVersion Version; - BOOLEAN EccSupport; - UINT8 MemoryProfile; - UINT32 TotalPhysicalMemorySize; - UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. - UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. - UINT8 Ratio; - UINT8 RefClk; - UINT32 VddVoltage[MAX_PROFILE_NUM]; - CONTROLLER_INFO Controller[MAX_NODE]; -} MEMORY_INFO_DATA_HOB; - -/** - Memory Platform Data Hob - - Revision 1: - - Initial version. - Revision 2: - - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields -**/ -typedef struct { - UINT8 Revision; - UINT8 Reserved[3]; - UINT32 BootMode; - UINT32 TsegSize; - UINT32 TsegBase; - UINT32 PrmrrSize; - UINT32 PrmrrBase; - UINT32 GttBase; - UINT32 MmioSize; - UINT32 PciEBaseAddress; -#ifdef CPU_CFL - UINT32 GdxcIotBase; - UINT32 GdxcIotSize; - UINT32 GdxcMotBase; - UINT32 GdxcMotSize; -#endif //CPU_CFL -} MEMORY_PLATFORM_DATA; - -typedef struct { - EFI_HOB_GUID_TYPE EfiHobGuidType; - MEMORY_PLATFORM_DATA Data; - UINT8 *Buffer; -} MEMORY_PLATFORM_DATA_HOB; - -#pragma pack (pop) - -#endif // _MEM_INFO_HOB_H_ From 3d27705d2741d9406409e8f18c4b4b47ca3e5a1a Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Thu, 6 Feb 2020 14:21:49 +0530 Subject: [PATCH 141/151] soc/intel/{skl, common}: Move ME Firmware SKU Types to common code 1. Move ME firmware SKU types into common code. 2. Define ME_HFS3_FW_SKU_CUSTOM SKU. TEST=Verified on hatch & soraka. Change-Id: Iaa4cf8d5b41c1008da1e7aa63b5a6960bb9a727b Signed-off-by: Sridhar Siricilla Reviewed-on: https://review.coreboot.org/c/coreboot/+/38796 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/include/intelblocks/cse.h | 5 +++++ src/soc/intel/skylake/include/soc/me.h | 3 --- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index aff330a815..6f8f4ff34c 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -41,6 +41,11 @@ #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 +/* ME Firmware SKU Types */ +#define ME_HFS3_FW_SKU_CONSUMER 0x2 +#define ME_HFS3_FW_SKU_CORPORATE 0x3 +#define ME_HFS3_FW_SKU_CUSTOM 0x5 + /* HFSTS register offsets in PCI config space */ enum { PCI_ME_HFSTS1 = 0x40, diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 30de2197f5..e8de30dde9 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -168,9 +168,6 @@ union me_hfs2 { } __packed fields; }; -#define ME_HFS3_FW_SKU_CONSUMER 0x2 -#define ME_HFS3_FW_SKU_CORPORATE 0x3 - union me_hfs3 { u32 data; struct { From 516f0acbb0af1d837c7844fb625271360b4b65ba Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 11 Feb 2020 16:44:43 +0100 Subject: [PATCH 142/151] nb/intel/sandybridge/acpi: Update PEG code * Use new ACPI syntax * Return either 0 or 0xf for PCI root port. That will make the device show up in Windows. This might help users and possibly Windows drivers working with PCIe ports. Change-Id: I1e76b735ab1472f6a4ea493c733cd6b2e6fca29e Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38831 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Paul Menzel --- src/northbridge/intel/sandybridge/acpi/peg.asl | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index f98a4ce083..fcec00ec67 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -20,8 +20,7 @@ Device (PEGP) Method (_STA) { - ShiftRight (\_SB.PCI0.MCHC.DVEN, 3, Local0) - Return (And (Local0, 1)) + Return (((\_SB.PCI0.MCHC.DVEN >> 3) & 1) * 0xf) } Device (DEV0) @@ -36,8 +35,7 @@ Device (PEG1) Method (_STA) { - ShiftRight (\_SB.PCI0.MCHC.DVEN, 2, Local0) - Return (And (Local0, 1)) + Return (((\_SB.PCI0.MCHC.DVEN >> 2) & 1) * 0xf) } Device (DEV0) @@ -52,8 +50,7 @@ Device (PEG2) Method (_STA) { - ShiftRight (\_SB.PCI0.MCHC.DVEN, 1, Local0) - Return (And (Local0, 1)) + Return (((\_SB.PCI0.MCHC.DVEN >> 1) & 1) * 0xf) } Device (DEV0) @@ -68,8 +65,7 @@ Device (PEG6) Method (_STA) { - ShiftRight (\_SB.PCI0.MCHC.DVEN, 13, Local0) - Return (And (Local0, 1)) + Return (((\_SB.PCI0.MCHC.DVEN >> 13) & 1) * 0xf) } Device (DEV0) From 5a62427e1451bb5e6e2c397b4c5950fac90cda1c Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 11 Feb 2020 16:02:11 +0100 Subject: [PATCH 143/151] nb/intel/sandybridge/acpi: Fix MMCONF size computation Calculate the correct MMCONF size, which was only correct for 256MiB, but not for smaller values. Tested on HP Z220: Fixes "Not using MMCONF" warning in dmesg. Change-Id: I986681126637c28f6442ab7c34acea5bb58ea3d2 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/38830 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber Reviewed-by: Jonathan Kollasch --- src/northbridge/intel/sandybridge/acpi/sandybridge.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 3181fc0a3f..0670c7b0a6 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -62,7 +62,7 @@ Device (PDRC) XBR0 = \_SB.PCI0.MCHC.PXBR << 26 CreateDwordField (PDRS, ^PCIX._LEN, XSZ0) - XSZ0 = 0x10000000 << \_SB.PCI0.MCHC.PXSZ + XSZ0 = 0x10000000 >> \_SB.PCI0.MCHC.PXSZ Return(PDRS) } From 5aa043b800e85c61a93c386956eb4ac23daa91fb Mon Sep 17 00:00:00 2001 From: Patrik Tesarik Date: Fri, 3 Jan 2020 16:01:00 +0100 Subject: [PATCH 144/151] doc/tutorial/part1.md: Add commands for yum- & pacman-based distro * Add additional information on non-debian cli tools * Improve spellings and descriptions to the best of my knowledge Adding info about needed tools in other distribution's package managers was requested at the coreboot beginner's workshop at 36C3. Change-Id: Ifff3c8354b4bec9f195f075eb6b2f377195fc237 Signed-off-by: Patrik Tesarik Reviewed-on: https://review.coreboot.org/c/coreboot/+/38225 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- Documentation/tutorial/part1.md | 47 ++++++++++++++++++++------------- 1 file changed, 29 insertions(+), 18 deletions(-) diff --git a/Documentation/tutorial/part1.md b/Documentation/tutorial/part1.md index 48145c2dc3..0c7ef67cbb 100644 --- a/Documentation/tutorial/part1.md +++ b/Documentation/tutorial/part1.md @@ -1,14 +1,18 @@ Tutorial, part 1: Starting from scratch =========================================== -From a fresh Ubuntu 16.04 or 18.04 install, here are all the steps required for -a very basic build: +This tutorial will guide you through the process of setting up a working +coreboot toolchain. In same cases you will find specific instructions for Debian (apt-get), +Fedora (dnf) and Arch Linux (pacman) based package management systems. Use the +instructions according to your system. Download, configure, and build coreboot --------------------------------------- ### Step 1 - Install tools and libraries needed for coreboot $ sudo apt-get install -y bison build-essential curl flex git gnat libncurses5-dev m4 zlib1g-dev + $ sudo pacman -S base-devel curl git gcc-ada ncurses zlib + $ sudo dnf install git make gcc-gnat flex bison xz bzip2 gcc g++ ncurses-devel wget zlib-devel ### Step 2 - Download coreboot source tree $ git clone https://review.coreboot.org/coreboot @@ -78,6 +82,8 @@ Test the image using QEMU ### Step 7 - Install QEMU $ sudo apt-get install -y qemu + $ sudo pacman -S qemu + $ sudo dnf install qemu ### Step 8 - Run QEMU Start QEMU, and point it to the ROM you just built: @@ -91,20 +97,24 @@ Summary ------- ### Step 1 summary - Install tools and libraries needed for coreboot -You installed the minimum additional requirements for ubuntu to download and -build coreboot. Ubuntu already has most of the other tools that would be -required installed by default. +Depending on your distribution you have installed the minimum additional +software requirements to continue with downloading and building coreboot. +Not every distribution has the tools, that would be required, +installed by default. In the following we shortly introduce the purpose of the +installed packages: -* `build-essential` is the basic tools for doing builds. It comes pre-installed -on some Ubuntu flavors, and not on others. +* `build-essential` or `base-devel` are the basic tools for building software. * `git` is needed to download coreboot from the coreboot git repository. -* `libncurses5-dev` is needed to build the menu for 'make menuconfig' +* `libncurses5-dev` or `ncurses` is needed to build the menu for 'make menuconfig' * `m4, bison, curl, flex, zlib1g-dev, gcc, gnat` and `g++` or `clang` are needed to build the coreboot toolchain. `gcc` and `gnat` have to be of the same version. -If you started with a different distribution, you might need to install many -other items which vary by distribution. +If you started with a different distribution or package management system you +might need to install other packages. Most likely they are named sightly +different. If that is the case for you, we'd like to encourage you to contribute +to the project and submit a pull request with an update for this documentation +for your system. ### Step 2 summary - Download coreboot source tree This will download a 'read-only' copy of the coreboot tree. This just means @@ -124,12 +134,12 @@ system during the build process. ### Step 4 summary - Build the payload To actually do anything useful with coreboot, you need to build a payload to -include in the rom. The idea behind coreboot is that it does the minimum amount +include into the rom. The idea behind coreboot is that it does the minimum amount possible before passing control of the machine to a payload. There are various payloads such as grub or SeaBIOS that are typically used to boot the operating system. Instead, we used coreinfo, a small demonstration payload that allows the -user to look at various things such as memory and the contents of coreboot's -cbfs - the pieces that make up the coreboot rom. +user to look at various things such as memory and the contents of the coreboot +file system (CBFS) - the pieces that make up the coreboot rom. ### Step 5 summary - Configure the build This step configures coreboot's build options using the menuconfig interface to @@ -154,16 +164,17 @@ build directory as 'coreboot.rom'. At the end of the build process, the build displayed the contents of the rom file. ### Step 7 summary - Install QEMU -QEMU is a processor emulator which we can use to show coreboot +QEMU is a processor emulator which we can use to show the coreboot boot +process in a virtualised environment. ### Step 8 summary - Run QEMU -Here's the command line broken down: +Here's the command line instruction broken down: * `qemu-system-x86_64` This starts the QEMU emulator with the i440FX host PCI bridge and PIIX3 PCI to ISA bridge. * `-bios build/coreboot.rom` -Use the bios rom image that we just built. If this is left off, the standard -SeaBIOS image that comes with QEMU is used. +Use the bios rom image that we just built. If this flag is left out, the +standard SeaBIOS image that comes with QEMU is used. * `-serial stdio` Send the serial output to the console. This allows you to view the coreboot -debug output. +boot log. From 65718760faf95921467dfe882858076b472e4237 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 4 Feb 2020 07:33:47 +0100 Subject: [PATCH 145/151] crossgcc: Upgrade IASL to version 20200110 Changes: 20200110: https://acpica.org/node/176 20191213: https://acpica.org/node/175 20191018: https://acpica.org/node/174 20190816: https://acpica.org/node/172 Change-Id: Ifaa0d1c79802872c1a822c1108d2a50bc60c8fd8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/38347 Reviewed-by: Martin Roth Reviewed-by: Paul Menzel Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 6 +----- ...20190703_iasl.patch => acpica-unix2-20200110_iasl.patch} | 0 util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum | 1 - util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum | 1 + 4 files changed, 2 insertions(+), 6 deletions(-) rename util/crossgcc/patches/{acpica-unix2-20190703_iasl.patch => acpica-unix2-20200110_iasl.patch} (100%) delete mode 100644 util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum create mode 100644 util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ab2ea899ff..150e616652 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -54,11 +54,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=8.3.1 - -# Conflicting use of _ADR and _HID in coreboot tree needs -# to be properly addressed before we can upgrade IASL version. -# Use IASL version 20190703 for now. -IASL_VERSION=20190703 +IASL_VERSION=20200110 PYTHON_VERSION=3.8.1 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20190703_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200110_iasl.patch similarity index 100% rename from util/crossgcc/patches/acpica-unix2-20190703_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200110_iasl.patch diff --git a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum deleted file mode 100644 index 9a89796d53..0000000000 --- a/util/crossgcc/sum/acpica-unix2-20190703.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c5594944f933265a53695204a0672d0808e4a580 tarballs/acpica-unix2-20190703.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum new file mode 100644 index 0000000000..48c0a2f7b7 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200110.tar.gz.cksum @@ -0,0 +1 @@ +50c163d965aa2cbee9a3a5d9244d1a0d16c06ec0 tarballs/acpica-unix2-20200110.tar.gz From cccb2d76c5ec5088e52c7913801a4bbd6661945b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 9 Feb 2020 12:09:18 +0100 Subject: [PATCH 146/151] arch/arm64/Makefile.inc: Avoid # in variable definition Interpretation if # starts a comment inside a variable definition varies between GNU make versions. Use a wildcard to match the first # and use `sed` instead of `grep | cut` to avoid unbalanced quoting chars. Tested with GNU make 4.2.1 and 4.3. Both produce the same output as 4.2.1 did before the patch. Change-Id: Ib7c4d7323e112968d3f14ea0590b7dabc57c9c45 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38794 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Julius Werner --- src/arch/arm64/Makefile.inc | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 1aee6b83f7..a8742f2e13 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -184,10 +184,7 @@ BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)" BL31_MAKEARGS += IS_ANYTHING_TO_BUILD=1 # Set a consistent build timestamp: the same coreboot has -# The \# \" complications exist to satisfy both gnu make's parser and editors -# with non-semantic quote-handling (that would assume that this line starts a -# multi line string. -BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell grep "\#define COREBOOT_BUILD\>" $(obj)/build.h |cut -d\" -f2 \# \")"' +BL31_MAKEARGS += BUILD_MESSAGE_TIMESTAMP='"$(shell sed -n 's/^.define COREBOOT_BUILD\>.*"\(.*\)".*/\1/p' $(obj)/build.h)"' BL31_CFLAGS := -fno-pic -fno-stack-protector -Wno-deprecated-declarations -Wno-unused-function BL31_LDFLAGS := --emit-relocs From 1c08a9a9c4986f2b3c47322f041e289121536dc0 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 9 Feb 2020 11:44:27 +0100 Subject: [PATCH 147/151] Makefile.inc: Use `define` for cbfs-files-processor-defconfig The body contains a `#` and GNU make 4.3 disagrees with earlier versions if it should be treated as a comment. Turn it into a `define` which has clearer semantics regarding comments (interpretation is supposed to be deferred until the variable is expanded). Change-Id: I589542abbd14082c3ecc4a2456ebd809fb6911ea Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38793 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Makefile.inc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 2690e8f462..648bc4f7f2 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -316,15 +316,16 @@ cbfs-files-processor-vsa= \ # Reduce a .config file to its minimal representation # arg1: input # arg2: output -cbfs-files-processor-defconfig= \ +define cbfs-files-processor-defconfig $(eval $(2): $(1) $(obj)/build.h $(objutil)/kconfig/conf; \ +printf " CREATE $(2) (from $(1))\n"; \ - printf "\# This image was built using coreboot " > $(2).tmp && \ + printf "# This image was built using coreboot " > $(2).tmp && \ grep "\" $(obj)/build.h |cut -d\" -f2 >> $(2).tmp && \ $(MAKE) DOTCONFIG=$(1) DEFCONFIG=$(2).tmp2 savedefconfig && \ cat $(2).tmp2 >> $(2).tmp && \ rm -f $(2).tmp2 && \ \mv -f $(2).tmp $(2)) +endef ####################################################################### # Compile a C file with a bare struct definition into binary From 0f6f70c3942c152c512b1aa51b6f6079a05e003b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sun, 9 Feb 2020 11:24:32 +0100 Subject: [PATCH 148/151] Makefile.inc: Adapt $(spc) definition GNU Make 4.3 is more picky about the $(spc) definition. It seems, the variable ends up empty. The old definition worked for nearly 8 years, RIP. Tested with GNU Make 4.2.1 and 4.3. Change-Id: I7981e0066b550251ae4a98d7b50e83049fc5586a Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/38790 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 648bc4f7f2..1f18726e5d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -159,7 +159,7 @@ ws_to_under=$(shell echo '$1' | tr ' \t' '_') ####################################################################### # Helper functions for ramstage postprocess spc := -spc += +spc := $(spc) $(spc) comma := , # Returns all files and dirs below `dir` (recursively). From a71071c96bd76c0021d702eb174e94e6d902ea66 Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 8 Feb 2020 17:09:14 +0100 Subject: [PATCH 149/151] mb/pcengines/apu2: Use variable `len` holding same value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia5916f191a7b1a846231b7e36924a16f3a658961 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38784 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/pcengines/apu2/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index a13ded959a..9bf58a78b9 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -169,7 +169,7 @@ static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, t = (struct smbios_type16 *)*current; len = sizeof(struct smbios_type16); - memset(t, 0, sizeof(struct smbios_type16)); + memset(t, 0, len); max_capacity = get_spd_offset() ? 4 : 2; /* 4GB or 2GB variant */ t->type = SMBIOS_PHYS_MEMORY_ARRAY; From 61b46a2dd75b7d4d56f6e7a6982da48fb1f27e4f Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Sat, 8 Feb 2020 17:24:29 +0100 Subject: [PATCH 150/151] mb/pcengines/apu2: Remove unnecessary initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The variable is never read before being assigned a value at the end of the function. Change-Id: I3b42dcd564480005b2c520316933940d87b6e418 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/38785 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/pcengines/apu2/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 9bf58a78b9..bd2ca392f1 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -192,7 +192,7 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, unsigned long *current) { struct smbios_type17 *t; - int len = 0; + int len; t = (struct smbios_type17 *)*current; memset(t, 0, sizeof(struct smbios_type17)); From 820ad004bbebe406e845ec9cc5d186544601c3d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 11 Feb 2020 19:22:41 +0100 Subject: [PATCH 151/151] mainboard/supermicro/x11-lga1151: correct board ids MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X11SSM-F has a different board id (0896) than X11SSH-TF (089C). Use the right id for the right board. Change-Id: Ib0d5e66ce1a973f29a1da78f04f7ef677b260cd8 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38834 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/mainboard/supermicro/x11-lga1151-series/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/Kconfig b/src/mainboard/supermicro/x11-lga1151-series/Kconfig index 02c9c86441..e0f468c84b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Kconfig +++ b/src/mainboard/supermicro/x11-lga1151-series/Kconfig @@ -88,6 +88,7 @@ config DIMM_SPD_SIZE config SUPERMICRO_BOARDID string - default "089C" + default "0896" if BOARD_SUPERMICRO_X11SSM_F + default "089C" if BOARD_SUPERMICRO_X11SSH_TF endif # BOARD_SUPERMICRO_BASEBOARD_X11_LGA1151_SERIES