From adc5695c39444f2078fad9f136a58f237a109344 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Mon, 11 Jul 2022 14:43:57 -0600 Subject: [PATCH] mb/system76/adl-p: oryp9: HACK: Disable RTD3 on CPU PCIe RPs WD drives fail to resume from suspend. Known to affect: - WD Green SN350 - WD Blue SN550 Change-Id: I319d0a213dc76bf10105fa8e90a2c0e5a0f77f32 Signed-off-by: Tim Crawford --- .../adl-p/variants/oryp9/overridetree.cb | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb b/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb index 585f34a3f9..51fbfbb2b7 100644 --- a/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb +++ b/src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb @@ -41,12 +41,13 @@ chip soc/intel/alderlake .clk_req = 0, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "0" # SSD0_CLKREQ# - device generic 0 on end - end + # FIXME: WD drives fail to suspend + #chip soc/intel/common/block/pcie/rtd3 + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1 + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + # register "srcclk_pin" = "0" # SSD0_CLKREQ# + # device generic 0 on end + #end end device ref pcie4_1 on # CPU PCIe RP#3 x4, Clock 4 (SSD2) @@ -55,12 +56,13 @@ chip soc/intel/alderlake .clk_req = 4, .flags = PCIE_RP_LTR, }" - chip soc/intel/common/block/pcie/rtd3 - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2 - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# - register "srcclk_pin" = "4" # SSD1_CLKREQ# - device generic 0 on end - end + # FIXME: WD drives fail to suspend + #chip soc/intel/common/block/pcie/rtd3 + # register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2 + # register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + # register "srcclk_pin" = "4" # SSD1_CLKREQ# + # device generic 0 on end + #end end device ref tcss_xhci on register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"