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nb/intel/x4x: Use SPI flash to cache raminit results

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Stores information obtained from decoding dimms and receive enable
results for future use.

Depreciates using rtc nvram to store receive enable settings.

A notable change is that receive enable results are always reused, not
just on a resume from S3.

This requires cbmem to be initialized a bit earlier, right after the
raminit finished to be able to add the sysinfo struct to cbmem which
gets cached to the SPI flash in ramstage.

TESTED on Intel DG43GT with W25Q128.V. With 4 ddr2 dimms time in
raminit goes from 133,857ms (using i2c block read to fetch SPD) to
21,071ms for cached results.

Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Arthur Heymans
2017-09-25 09:40:54 +02:00
committed by Patrick Georgi
parent 0cdaad36eb
commit adc571a54c
6 changed files with 156 additions and 92 deletions
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7
src/northbridge/intel/x4x/rcven.c
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@@ -304,7 +304,7 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
return 0;
}
void rcven(const struct sysinfo *s)
void rcven(struct sysinfo *s)
{
int i;
u8 channel, lane, reg8;
@@ -354,6 +354,7 @@ void rcven(const struct sysinfo *s)
mincoarse = timing[lane].coarse;
}
printk(BIOS_DEBUG, "Found min coarse value = %d\n", mincoarse);
s->rcven_t[channel].min_common_coarse = mincoarse;
printk(BIOS_DEBUG, "Receive enable, final timings:\n");
/* Normalise coarse */
for (lane = 0; lane < 8; lane++) {
@@ -365,6 +366,10 @@ void rcven(const struct sysinfo *s)
"medium: %d; tap: %d\n",
channel, lane, reg8, timing[lane].medium,
timing[lane].tap);
s->rcven_t[channel].coarse_offset[lane] = reg8;
s->rcven_t[channel].medium[lane] = timing[lane].medium;
s->rcven_t[channel].tap[lane] = timing[lane].tap;
s->rcven_t[channel].pi[lane] = timing[lane].pi;
MCHBAR16(0x400 * channel + 0x5fa) =
(MCHBAR16(0x400 * channel + 0x5fa) &
~(3 << (lane * 2))) | (reg8 << (lane * 2));