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soc/intel/skylake: Configure L1 substates for PCH root ports

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Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration.

Tested on an Acer Aspire VN7-572G (Skylake-U).

Change-Id: I36150858485715016158595c832c142b0582ddb8
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Benjamin Doron
2020-03-14 01:53:25 +00:00
committed by Nico Huber
parent 3e314636a6
commit adcb870837
2 changed files with 10 additions and 0 deletions
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src/soc/intel/skylake/chip.c
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@@ -212,6 +212,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i];
if (config->PcieRpAspm[i])
params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1;
if (config->pcie_rp_l1substates[i])
params->PcieRpL1Substates[i] = config->pcie_rp_l1substates[i] - 1;
}
/*